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Yann Gautier9aea69e2018-07-24 17:13:36 +02001/*
Yann Gautier360e0e92020-09-16 16:40:34 +02002 * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
Yann Gautier9aea69e2018-07-24 17:13:36 +02003 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
Yann Gautier9aea69e2018-07-24 17:13:36 +02007#include <assert.h>
Yann Gautier9aea69e2018-07-24 17:13:36 +02008#include <errno.h>
Yann Gautier9aea69e2018-07-24 17:13:36 +02009#include <stdint.h>
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010010#include <stdio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
12#include <libfdt.h>
13
Yann Gautier57e282b2019-01-07 11:17:24 +010014#include <platform_def.h>
15
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <arch.h>
17#include <arch_helpers.h>
18#include <common/debug.h>
Andre Przywaracc99f3f2020-03-26 12:51:21 +000019#include <common/fdt_wrappers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <drivers/delay_timer.h>
21#include <drivers/generic_delay_timer.h>
Yann Gautier4d429472019-02-14 11:15:20 +010022#include <drivers/st/stm32mp_clkfunc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <drivers/st/stm32mp1_clk.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024#include <drivers/st/stm32mp1_rcc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000025#include <dt-bindings/clock/stm32mp1-clksrc.h>
26#include <lib/mmio.h>
Yann Gautiere4a3c352019-02-14 10:53:33 +010027#include <lib/spinlock.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000028#include <lib/utils_def.h>
29#include <plat/common/platform.h>
30
Yann Gautier2299d572019-02-14 11:14:39 +010031#define MAX_HSI_HZ 64000000
Yann Gautiere4a3c352019-02-14 10:53:33 +010032#define USB_PHY_48_MHZ 48000000
Yann Gautier9aea69e2018-07-24 17:13:36 +020033
Yann Gautier2299d572019-02-14 11:14:39 +010034#define TIMEOUT_US_200MS U(200000)
35#define TIMEOUT_US_1S U(1000000)
Yann Gautier9aea69e2018-07-24 17:13:36 +020036
Yann Gautier2299d572019-02-14 11:14:39 +010037#define PLLRDY_TIMEOUT TIMEOUT_US_200MS
38#define CLKSRC_TIMEOUT TIMEOUT_US_200MS
39#define CLKDIV_TIMEOUT TIMEOUT_US_200MS
40#define HSIDIV_TIMEOUT TIMEOUT_US_200MS
41#define OSCRDY_TIMEOUT TIMEOUT_US_1S
Yann Gautier9aea69e2018-07-24 17:13:36 +020042
Yann Gautier5f2e8742019-05-17 15:57:56 +020043const char *stm32mp_osc_node_label[NB_OSC] = {
44 [_LSI] = "clk-lsi",
45 [_LSE] = "clk-lse",
46 [_HSI] = "clk-hsi",
47 [_HSE] = "clk-hse",
48 [_CSI] = "clk-csi",
49 [_I2S_CKIN] = "i2s_ckin",
50};
51
Yann Gautier9aea69e2018-07-24 17:13:36 +020052enum stm32mp1_parent_id {
53/* Oscillators are defined in enum stm32mp_osc_id */
54
55/* Other parent source */
56 _HSI_KER = NB_OSC,
57 _HSE_KER,
58 _HSE_KER_DIV2,
Gabriel Fernandez4e3a51a2021-07-27 15:39:16 +020059 _HSE_RTC,
Yann Gautier9aea69e2018-07-24 17:13:36 +020060 _CSI_KER,
61 _PLL1_P,
62 _PLL1_Q,
63 _PLL1_R,
64 _PLL2_P,
65 _PLL2_Q,
66 _PLL2_R,
67 _PLL3_P,
68 _PLL3_Q,
69 _PLL3_R,
70 _PLL4_P,
71 _PLL4_Q,
72 _PLL4_R,
73 _ACLK,
74 _PCLK1,
75 _PCLK2,
76 _PCLK3,
77 _PCLK4,
78 _PCLK5,
79 _HCLK6,
80 _HCLK2,
81 _CK_PER,
82 _CK_MPU,
Yann Gautiered342322019-02-15 17:33:27 +010083 _CK_MCU,
Yann Gautiere4a3c352019-02-14 10:53:33 +010084 _USB_PHY_48,
Yann Gautier9aea69e2018-07-24 17:13:36 +020085 _PARENT_NB,
86 _UNKNOWN_ID = 0xff,
87};
88
Yann Gautiere4a3c352019-02-14 10:53:33 +010089/* Lists only the parent clock we are interested in */
Yann Gautier9aea69e2018-07-24 17:13:36 +020090enum stm32mp1_parent_sel {
Yann Gautiere4a3c352019-02-14 10:53:33 +010091 _I2C12_SEL,
92 _I2C35_SEL,
93 _STGEN_SEL,
Yann Gautier9aea69e2018-07-24 17:13:36 +020094 _I2C46_SEL,
Yann Gautiere4a3c352019-02-14 10:53:33 +010095 _SPI6_SEL,
Yann Gautier9d8bbcd2019-05-07 18:49:33 +020096 _UART1_SEL,
Yann Gautiere4a3c352019-02-14 10:53:33 +010097 _RNG1_SEL,
Yann Gautier9aea69e2018-07-24 17:13:36 +020098 _UART6_SEL,
99 _UART24_SEL,
100 _UART35_SEL,
101 _UART78_SEL,
102 _SDMMC12_SEL,
103 _SDMMC3_SEL,
104 _QSPI_SEL,
105 _FMC_SEL,
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200106 _AXIS_SEL,
107 _MCUS_SEL,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200108 _USBPHY_SEL,
109 _USBO_SEL,
Etienne Carriere04132612019-12-08 08:20:12 +0100110 _MPU_SEL,
Yann Gautierfaa9bcf2021-08-31 18:23:13 +0200111 _CKPER_SEL,
Etienne Carrierebccc7d02019-12-08 08:22:31 +0100112 _RTC_SEL,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200113 _PARENT_SEL_NB,
114 _UNKNOWN_SEL = 0xff,
115};
116
Etienne Carriere04132612019-12-08 08:20:12 +0100117/* State the parent clock ID straight related to a clock */
118static const uint8_t parent_id_clock_id[_PARENT_NB] = {
119 [_HSE] = CK_HSE,
120 [_HSI] = CK_HSI,
121 [_CSI] = CK_CSI,
122 [_LSE] = CK_LSE,
123 [_LSI] = CK_LSI,
124 [_I2S_CKIN] = _UNKNOWN_ID,
125 [_USB_PHY_48] = _UNKNOWN_ID,
126 [_HSI_KER] = CK_HSI,
127 [_HSE_KER] = CK_HSE,
128 [_HSE_KER_DIV2] = CK_HSE_DIV2,
Gabriel Fernandez4e3a51a2021-07-27 15:39:16 +0200129 [_HSE_RTC] = _UNKNOWN_ID,
Etienne Carriere04132612019-12-08 08:20:12 +0100130 [_CSI_KER] = CK_CSI,
131 [_PLL1_P] = PLL1_P,
132 [_PLL1_Q] = PLL1_Q,
133 [_PLL1_R] = PLL1_R,
134 [_PLL2_P] = PLL2_P,
135 [_PLL2_Q] = PLL2_Q,
136 [_PLL2_R] = PLL2_R,
137 [_PLL3_P] = PLL3_P,
138 [_PLL3_Q] = PLL3_Q,
139 [_PLL3_R] = PLL3_R,
140 [_PLL4_P] = PLL4_P,
141 [_PLL4_Q] = PLL4_Q,
142 [_PLL4_R] = PLL4_R,
143 [_ACLK] = CK_AXI,
144 [_PCLK1] = CK_AXI,
145 [_PCLK2] = CK_AXI,
146 [_PCLK3] = CK_AXI,
147 [_PCLK4] = CK_AXI,
148 [_PCLK5] = CK_AXI,
149 [_CK_PER] = CK_PER,
150 [_CK_MPU] = CK_MPU,
151 [_CK_MCU] = CK_MCU,
152};
153
154static unsigned int clock_id2parent_id(unsigned long id)
155{
156 unsigned int n;
157
158 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) {
159 if (parent_id_clock_id[n] == id) {
160 return n;
161 }
162 }
163
164 return _UNKNOWN_ID;
165}
166
Yann Gautier9aea69e2018-07-24 17:13:36 +0200167enum stm32mp1_pll_id {
168 _PLL1,
169 _PLL2,
170 _PLL3,
171 _PLL4,
172 _PLL_NB
173};
174
175enum stm32mp1_div_id {
176 _DIV_P,
177 _DIV_Q,
178 _DIV_R,
179 _DIV_NB,
180};
181
182enum stm32mp1_clksrc_id {
183 CLKSRC_MPU,
184 CLKSRC_AXI,
Yann Gautiered342322019-02-15 17:33:27 +0100185 CLKSRC_MCU,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200186 CLKSRC_PLL12,
187 CLKSRC_PLL3,
188 CLKSRC_PLL4,
189 CLKSRC_RTC,
190 CLKSRC_MCO1,
191 CLKSRC_MCO2,
192 CLKSRC_NB
193};
194
195enum stm32mp1_clkdiv_id {
196 CLKDIV_MPU,
197 CLKDIV_AXI,
Yann Gautiered342322019-02-15 17:33:27 +0100198 CLKDIV_MCU,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200199 CLKDIV_APB1,
200 CLKDIV_APB2,
201 CLKDIV_APB3,
202 CLKDIV_APB4,
203 CLKDIV_APB5,
204 CLKDIV_RTC,
205 CLKDIV_MCO1,
206 CLKDIV_MCO2,
207 CLKDIV_NB
208};
209
210enum stm32mp1_pllcfg {
211 PLLCFG_M,
212 PLLCFG_N,
213 PLLCFG_P,
214 PLLCFG_Q,
215 PLLCFG_R,
216 PLLCFG_O,
217 PLLCFG_NB
218};
219
220enum stm32mp1_pllcsg {
221 PLLCSG_MOD_PER,
222 PLLCSG_INC_STEP,
223 PLLCSG_SSCG_MODE,
224 PLLCSG_NB
225};
226
227enum stm32mp1_plltype {
228 PLL_800,
229 PLL_1600,
230 PLL_TYPE_NB
231};
232
233struct stm32mp1_pll {
234 uint8_t refclk_min;
235 uint8_t refclk_max;
236 uint8_t divn_max;
237};
238
239struct stm32mp1_clk_gate {
240 uint16_t offset;
241 uint8_t bit;
242 uint8_t index;
243 uint8_t set_clr;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100244 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */
245 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */
Yann Gautier9aea69e2018-07-24 17:13:36 +0200246};
247
248struct stm32mp1_clk_sel {
249 uint16_t offset;
250 uint8_t src;
251 uint8_t msk;
252 uint8_t nb_parent;
253 const uint8_t *parent;
254};
255
256#define REFCLK_SIZE 4
257struct stm32mp1_clk_pll {
258 enum stm32mp1_plltype plltype;
259 uint16_t rckxselr;
260 uint16_t pllxcfgr1;
261 uint16_t pllxcfgr2;
262 uint16_t pllxfracr;
263 uint16_t pllxcr;
264 uint16_t pllxcsgr;
265 enum stm32mp_osc_id refclk[REFCLK_SIZE];
266};
267
Yann Gautiere4a3c352019-02-14 10:53:33 +0100268/* Clocks with selectable source and non set/clr register access */
269#define _CLK_SELEC(off, b, idx, s) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200270 { \
271 .offset = (off), \
272 .bit = (b), \
273 .index = (idx), \
274 .set_clr = 0, \
275 .sel = (s), \
276 .fixed = _UNKNOWN_ID, \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200277 }
278
Yann Gautiere4a3c352019-02-14 10:53:33 +0100279/* Clocks with fixed source and non set/clr register access */
280#define _CLK_FIXED(off, b, idx, f) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200281 { \
282 .offset = (off), \
283 .bit = (b), \
284 .index = (idx), \
285 .set_clr = 0, \
286 .sel = _UNKNOWN_SEL, \
287 .fixed = (f), \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200288 }
289
Yann Gautiere4a3c352019-02-14 10:53:33 +0100290/* Clocks with selectable source and set/clr register access */
291#define _CLK_SC_SELEC(off, b, idx, s) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200292 { \
293 .offset = (off), \
294 .bit = (b), \
295 .index = (idx), \
296 .set_clr = 1, \
297 .sel = (s), \
298 .fixed = _UNKNOWN_ID, \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200299 }
300
Yann Gautiere4a3c352019-02-14 10:53:33 +0100301/* Clocks with fixed source and set/clr register access */
302#define _CLK_SC_FIXED(off, b, idx, f) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200303 { \
304 .offset = (off), \
305 .bit = (b), \
306 .index = (idx), \
307 .set_clr = 1, \
308 .sel = _UNKNOWN_SEL, \
309 .fixed = (f), \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200310 }
311
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200312#define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \
313 [_ ## _label ## _SEL] = { \
314 .offset = _rcc_selr, \
315 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \
Etienne Carrierec164ce22019-12-08 08:20:40 +0100316 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \
317 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200318 .parent = (_parents), \
319 .nb_parent = ARRAY_SIZE(_parents) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200320 }
321
Yann Gautiere4a3c352019-02-14 10:53:33 +0100322#define _CLK_PLL(idx, type, off1, off2, off3, \
323 off4, off5, off6, \
324 p1, p2, p3, p4) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200325 [(idx)] = { \
326 .plltype = (type), \
327 .rckxselr = (off1), \
328 .pllxcfgr1 = (off2), \
329 .pllxcfgr2 = (off3), \
330 .pllxfracr = (off4), \
331 .pllxcr = (off5), \
332 .pllxcsgr = (off6), \
333 .refclk[0] = (p1), \
334 .refclk[1] = (p2), \
335 .refclk[2] = (p3), \
336 .refclk[3] = (p4), \
337 }
338
Yann Gautiere4a3c352019-02-14 10:53:33 +0100339#define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate)
340
Yann Gautier9aea69e2018-07-24 17:13:36 +0200341static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
Yann Gautiere4a3c352019-02-14 10:53:33 +0100342 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK),
343 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK),
344 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK),
345 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK),
346 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
347 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R),
348 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4),
349 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4),
350 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK),
351 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4),
352 _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4),
353
354 _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1),
355 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
356 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
357 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
358 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
359 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
360 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
361 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
362 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
363 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
364 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
365
366 _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2),
367 _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
368
Yann Gautier3edc7c32019-05-20 19:17:08 +0200369 _CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID),
370
Yann Gautiere4a3c352019-02-14 10:53:33 +0100371 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
372 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
373 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
374
375 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
376 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
377 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200378 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL),
Yann Gautiere4a3c352019-02-14 10:53:33 +0100379 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
380 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5),
381 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5),
382 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5),
383 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5),
384 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5),
385 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
386
387 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
388 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
389
390 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
391 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
392 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
393 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
394 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
395 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
396 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
397 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
398 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
399 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
400 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
401
402 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5),
403 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5),
404 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5),
405 _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL),
406 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5),
407
408 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
409 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
410 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
411 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
412 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
413
Etienne Carrierebccc7d02019-12-08 08:22:31 +0100414 _CLK_SELEC(RCC_BDCR, 20, RTC, _RTC_SEL),
Yann Gautiere4a3c352019-02-14 10:53:33 +0100415 _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
416};
417
418static const uint8_t i2c12_parents[] = {
419 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
420};
421
422static const uint8_t i2c35_parents[] = {
423 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
424};
425
426static const uint8_t stgen_parents[] = {
427 _HSI_KER, _HSE_KER
428};
429
430static const uint8_t i2c46_parents[] = {
431 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER
432};
433
434static const uint8_t spi6_parents[] = {
435 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q
436};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200437
Yann Gautiere4a3c352019-02-14 10:53:33 +0100438static const uint8_t usart1_parents[] = {
439 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER
440};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200441
Yann Gautiere4a3c352019-02-14 10:53:33 +0100442static const uint8_t rng1_parents[] = {
443 _CSI, _PLL4_R, _LSE, _LSI
444};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200445
Yann Gautiere4a3c352019-02-14 10:53:33 +0100446static const uint8_t uart6_parents[] = {
447 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
448};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200449
Yann Gautiere4a3c352019-02-14 10:53:33 +0100450static const uint8_t uart234578_parents[] = {
451 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
452};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200453
Yann Gautiere4a3c352019-02-14 10:53:33 +0100454static const uint8_t sdmmc12_parents[] = {
455 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER
456};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200457
Yann Gautiere4a3c352019-02-14 10:53:33 +0100458static const uint8_t sdmmc3_parents[] = {
459 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER
460};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200461
Yann Gautiere4a3c352019-02-14 10:53:33 +0100462static const uint8_t qspi_parents[] = {
463 _ACLK, _PLL3_R, _PLL4_P, _CK_PER
464};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200465
Yann Gautiere4a3c352019-02-14 10:53:33 +0100466static const uint8_t fmc_parents[] = {
467 _ACLK, _PLL3_R, _PLL4_P, _CK_PER
468};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200469
Yann Gautiere4a3c352019-02-14 10:53:33 +0100470static const uint8_t ass_parents[] = {
471 _HSI, _HSE, _PLL2
Yann Gautier9aea69e2018-07-24 17:13:36 +0200472};
473
Yann Gautiered342322019-02-15 17:33:27 +0100474static const uint8_t mss_parents[] = {
475 _HSI, _HSE, _CSI, _PLL3
476};
477
Yann Gautiere4a3c352019-02-14 10:53:33 +0100478static const uint8_t usbphy_parents[] = {
479 _HSE_KER, _PLL4_R, _HSE_KER_DIV2
480};
481
482static const uint8_t usbo_parents[] = {
483 _PLL4_R, _USB_PHY_48
484};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200485
Etienne Carriere04132612019-12-08 08:20:12 +0100486static const uint8_t mpu_parents[] = {
487 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */
488};
489
490static const uint8_t per_parents[] = {
491 _HSI, _HSE, _CSI,
492};
493
Etienne Carrierebccc7d02019-12-08 08:22:31 +0100494static const uint8_t rtc_parents[] = {
Gabriel Fernandez4e3a51a2021-07-27 15:39:16 +0200495 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC
Etienne Carrierebccc7d02019-12-08 08:22:31 +0100496};
497
Yann Gautier9aea69e2018-07-24 17:13:36 +0200498static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200499 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents),
500 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents),
501 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents),
502 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents),
503 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents),
504 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents),
505 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents),
Etienne Carriere04132612019-12-08 08:20:12 +0100506 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents),
Yann Gautierfaa9bcf2021-08-31 18:23:13 +0200507 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents),
Etienne Carrierebccc7d02019-12-08 08:22:31 +0100508 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents),
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200509 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents),
510 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents),
511 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents),
512 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents),
513 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents),
514 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents),
515 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents),
516 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents),
517 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents),
518 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents),
519 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents),
520 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents),
Yann Gautier9aea69e2018-07-24 17:13:36 +0200521};
522
523/* Define characteristic of PLL according type */
524#define DIVN_MIN 24
525static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
526 [PLL_800] = {
527 .refclk_min = 4,
528 .refclk_max = 16,
529 .divn_max = 99,
530 },
531 [PLL_1600] = {
532 .refclk_min = 8,
533 .refclk_max = 16,
534 .divn_max = 199,
535 },
536};
537
538/* PLLNCFGR2 register divider by output */
539static const uint8_t pllncfgr2[_DIV_NB] = {
540 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
541 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
Yann Gautiere4a3c352019-02-14 10:53:33 +0100542 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200543};
544
545static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
Yann Gautiere4a3c352019-02-14 10:53:33 +0100546 _CLK_PLL(_PLL1, PLL_1600,
547 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
548 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
549 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
550 _CLK_PLL(_PLL2, PLL_1600,
551 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
552 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
553 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
554 _CLK_PLL(_PLL3, PLL_800,
555 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
556 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
557 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID),
558 _CLK_PLL(_PLL4, PLL_800,
559 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
560 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
561 _HSI, _HSE, _CSI, _I2S_CKIN),
Yann Gautier9aea69e2018-07-24 17:13:36 +0200562};
563
564/* Prescaler table lookups for clock computation */
Yann Gautiered342322019-02-15 17:33:27 +0100565/* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
566static const uint8_t stm32mp1_mcu_div[16] = {
567 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
568};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200569
570/* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */
571#define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
572#define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
573static const uint8_t stm32mp1_mpu_apbx_div[8] = {
574 0, 1, 2, 3, 4, 4, 4, 4
575};
576
577/* div = /1 /2 /3 /4 */
578static const uint8_t stm32mp1_axi_div[8] = {
579 1, 2, 3, 4, 4, 4, 4, 4
580};
581
Etienne Carriere1368ada2020-05-13 11:49:49 +0200582static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = {
583 [_HSI] = "HSI",
584 [_HSE] = "HSE",
585 [_CSI] = "CSI",
586 [_LSI] = "LSI",
587 [_LSE] = "LSE",
588 [_I2S_CKIN] = "I2S_CKIN",
589 [_HSI_KER] = "HSI_KER",
590 [_HSE_KER] = "HSE_KER",
591 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
Gabriel Fernandez4e3a51a2021-07-27 15:39:16 +0200592 [_HSE_RTC] = "HSE_RTC",
Etienne Carriere1368ada2020-05-13 11:49:49 +0200593 [_CSI_KER] = "CSI_KER",
594 [_PLL1_P] = "PLL1_P",
595 [_PLL1_Q] = "PLL1_Q",
596 [_PLL1_R] = "PLL1_R",
597 [_PLL2_P] = "PLL2_P",
598 [_PLL2_Q] = "PLL2_Q",
599 [_PLL2_R] = "PLL2_R",
600 [_PLL3_P] = "PLL3_P",
601 [_PLL3_Q] = "PLL3_Q",
602 [_PLL3_R] = "PLL3_R",
603 [_PLL4_P] = "PLL4_P",
604 [_PLL4_Q] = "PLL4_Q",
605 [_PLL4_R] = "PLL4_R",
606 [_ACLK] = "ACLK",
607 [_PCLK1] = "PCLK1",
608 [_PCLK2] = "PCLK2",
609 [_PCLK3] = "PCLK3",
610 [_PCLK4] = "PCLK4",
611 [_PCLK5] = "PCLK5",
612 [_HCLK6] = "KCLK6",
613 [_HCLK2] = "HCLK2",
614 [_CK_PER] = "CK_PER",
615 [_CK_MPU] = "CK_MPU",
616 [_CK_MCU] = "CK_MCU",
617 [_USB_PHY_48] = "USB_PHY_48",
618};
619
Yann Gautiere4a3c352019-02-14 10:53:33 +0100620/* RCC clock device driver private */
621static unsigned long stm32mp1_osc[NB_OSC];
622static struct spinlock reg_lock;
623static unsigned int gate_refcounts[NB_GATES];
624static struct spinlock refcount_lock;
625
626static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx)
627{
628 return &stm32mp1_clk_gate[idx];
629}
Yann Gautier9aea69e2018-07-24 17:13:36 +0200630
Yann Gautiere4a3c352019-02-14 10:53:33 +0100631static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx)
632{
633 return &stm32mp1_clk_sel[idx];
634}
Yann Gautier9aea69e2018-07-24 17:13:36 +0200635
Yann Gautiere4a3c352019-02-14 10:53:33 +0100636static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx)
637{
638 return &stm32mp1_clk_pll[idx];
639}
640
Yann Gautiere4a3c352019-02-14 10:53:33 +0100641static void stm32mp1_clk_lock(struct spinlock *lock)
642{
Yann Gautierf540a592019-05-22 19:13:51 +0200643 if (stm32mp_lock_available()) {
644 /* Assume interrupts are masked */
645 spin_lock(lock);
Yann Gautiere4a3c352019-02-14 10:53:33 +0100646 }
Yann Gautiere4a3c352019-02-14 10:53:33 +0100647}
648
649static void stm32mp1_clk_unlock(struct spinlock *lock)
650{
Yann Gautierf540a592019-05-22 19:13:51 +0200651 if (stm32mp_lock_available()) {
652 spin_unlock(lock);
Yann Gautiere4a3c352019-02-14 10:53:33 +0100653 }
Yann Gautiere4a3c352019-02-14 10:53:33 +0100654}
655
656bool stm32mp1_rcc_is_secure(void)
657{
658 uintptr_t rcc_base = stm32mp_rcc_base();
Etienne Carriere5e68f6b2020-02-05 10:03:27 +0100659 uint32_t mask = RCC_TZCR_TZEN;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100660
Etienne Carriere5e68f6b2020-02-05 10:03:27 +0100661 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100662}
663
Yann Gautiered342322019-02-15 17:33:27 +0100664bool stm32mp1_rcc_is_mckprot(void)
665{
666 uintptr_t rcc_base = stm32mp_rcc_base();
Etienne Carriere5e68f6b2020-02-05 10:03:27 +0100667 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT;
Yann Gautiered342322019-02-15 17:33:27 +0100668
Etienne Carriere5e68f6b2020-02-05 10:03:27 +0100669 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;
Yann Gautiered342322019-02-15 17:33:27 +0100670}
671
Yann Gautiere4a3c352019-02-14 10:53:33 +0100672void stm32mp1_clk_rcc_regs_lock(void)
673{
674 stm32mp1_clk_lock(&reg_lock);
675}
676
677void stm32mp1_clk_rcc_regs_unlock(void)
678{
679 stm32mp1_clk_unlock(&reg_lock);
680}
681
682static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200683{
684 if (idx >= NB_OSC) {
685 return 0;
686 }
687
Yann Gautiere4a3c352019-02-14 10:53:33 +0100688 return stm32mp1_osc[idx];
Yann Gautier9aea69e2018-07-24 17:13:36 +0200689}
690
Yann Gautiere4a3c352019-02-14 10:53:33 +0100691static int stm32mp1_clk_get_gated_id(unsigned long id)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200692{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100693 unsigned int i;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200694
Yann Gautiere4a3c352019-02-14 10:53:33 +0100695 for (i = 0U; i < NB_GATES; i++) {
696 if (gate_ref(i)->index == id) {
Yann Gautier9aea69e2018-07-24 17:13:36 +0200697 return i;
698 }
699 }
700
701 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id);
702
703 return -EINVAL;
704}
705
Yann Gautiere4a3c352019-02-14 10:53:33 +0100706static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200707{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100708 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200709}
710
Yann Gautiere4a3c352019-02-14 10:53:33 +0100711static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200712{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100713 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200714}
715
Yann Gautiere4a3c352019-02-14 10:53:33 +0100716static int stm32mp1_clk_get_parent(unsigned long id)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200717{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100718 const struct stm32mp1_clk_sel *sel;
Etienne Carriere04132612019-12-08 08:20:12 +0100719 uint32_t p_sel;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200720 int i;
721 enum stm32mp1_parent_id p;
722 enum stm32mp1_parent_sel s;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100723 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200724
Etienne Carriere04132612019-12-08 08:20:12 +0100725 /* Few non gateable clock have a static parent ID, find them */
726 i = (int)clock_id2parent_id(id);
727 if (i != _UNKNOWN_ID) {
728 return i;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200729 }
730
Yann Gautiere4a3c352019-02-14 10:53:33 +0100731 i = stm32mp1_clk_get_gated_id(id);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200732 if (i < 0) {
Yann Gautiere4a3c352019-02-14 10:53:33 +0100733 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200734 }
735
Yann Gautiere4a3c352019-02-14 10:53:33 +0100736 p = stm32mp1_clk_get_fixed_parent(i);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200737 if (p < _PARENT_NB) {
738 return (int)p;
739 }
740
Yann Gautiere4a3c352019-02-14 10:53:33 +0100741 s = stm32mp1_clk_get_sel(i);
742 if (s == _UNKNOWN_SEL) {
Yann Gautier9aea69e2018-07-24 17:13:36 +0200743 return -EINVAL;
744 }
Yann Gautiere4a3c352019-02-14 10:53:33 +0100745 if (s >= _PARENT_SEL_NB) {
746 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200747 }
748
Yann Gautiere4a3c352019-02-14 10:53:33 +0100749 sel = clk_sel_ref(s);
Etienne Carrierec164ce22019-12-08 08:20:40 +0100750 p_sel = (mmio_read_32(rcc_base + sel->offset) &
751 (sel->msk << sel->src)) >> sel->src;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100752 if (p_sel < sel->nb_parent) {
753 return (int)sel->parent[p_sel];
754 }
Yann Gautier9aea69e2018-07-24 17:13:36 +0200755
756 return -EINVAL;
757}
758
Yann Gautiere4a3c352019-02-14 10:53:33 +0100759static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200760{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100761 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr);
762 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200763
Yann Gautiere4a3c352019-02-14 10:53:33 +0100764 return stm32mp1_clk_get_fixed(pll->refclk[src]);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200765}
766
767/*
768 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
769 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
770 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
771 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
772 */
Yann Gautiere4a3c352019-02-14 10:53:33 +0100773static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200774{
Yann Gautier9aea69e2018-07-24 17:13:36 +0200775 unsigned long refclk, fvco;
776 uint32_t cfgr1, fracr, divm, divn;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100777 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200778
Yann Gautiere4a3c352019-02-14 10:53:33 +0100779 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1);
780 fracr = mmio_read_32(rcc_base + pll->pllxfracr);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200781
782 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
783 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
784
Yann Gautiere4a3c352019-02-14 10:53:33 +0100785 refclk = stm32mp1_pll_get_fref(pll);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200786
787 /*
788 * With FRACV :
789 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
790 * Without FRACV
791 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
792 */
793 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) {
Yann Gautiere4a3c352019-02-14 10:53:33 +0100794 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >>
795 RCC_PLLNFRACR_FRACV_SHIFT;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200796 unsigned long long numerator, denominator;
797
Yann Gautiere4a3c352019-02-14 10:53:33 +0100798 numerator = (((unsigned long long)divn + 1U) << 13) + fracv;
799 numerator = refclk * numerator;
800 denominator = ((unsigned long long)divm + 1U) << 13;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200801 fvco = (unsigned long)(numerator / denominator);
802 } else {
803 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U));
804 }
805
806 return fvco;
807}
808
Yann Gautiere4a3c352019-02-14 10:53:33 +0100809static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200810 enum stm32mp1_div_id div_id)
811{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100812 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200813 unsigned long dfout;
814 uint32_t cfgr2, divy;
815
816 if (div_id >= _DIV_NB) {
817 return 0;
818 }
819
Yann Gautiere4a3c352019-02-14 10:53:33 +0100820 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200821 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
822
Yann Gautiere4a3c352019-02-14 10:53:33 +0100823 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200824
825 return dfout;
826}
827
Yann Gautiere4a3c352019-02-14 10:53:33 +0100828static unsigned long get_clock_rate(int p)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200829{
830 uint32_t reg, clkdiv;
831 unsigned long clock = 0;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100832 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200833
834 switch (p) {
835 case _CK_MPU:
836 /* MPU sub system */
Yann Gautiere4a3c352019-02-14 10:53:33 +0100837 reg = mmio_read_32(rcc_base + RCC_MPCKSELR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200838 switch (reg & RCC_SELR_SRC_MASK) {
839 case RCC_MPCKSELR_HSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100840 clock = stm32mp1_clk_get_fixed(_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200841 break;
842 case RCC_MPCKSELR_HSE:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100843 clock = stm32mp1_clk_get_fixed(_HSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200844 break;
845 case RCC_MPCKSELR_PLL:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100846 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200847 break;
848 case RCC_MPCKSELR_PLL_MPUDIV:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100849 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200850
Yann Gautiere4a3c352019-02-14 10:53:33 +0100851 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200852 clkdiv = reg & RCC_MPUDIV_MASK;
853 if (clkdiv != 0U) {
854 clock /= stm32mp1_mpu_div[clkdiv];
855 }
Yann Gautier9aea69e2018-07-24 17:13:36 +0200856 break;
857 default:
858 break;
859 }
860 break;
861 /* AXI sub system */
862 case _ACLK:
863 case _HCLK2:
864 case _HCLK6:
865 case _PCLK4:
866 case _PCLK5:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100867 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200868 switch (reg & RCC_SELR_SRC_MASK) {
869 case RCC_ASSCKSELR_HSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100870 clock = stm32mp1_clk_get_fixed(_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200871 break;
872 case RCC_ASSCKSELR_HSE:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100873 clock = stm32mp1_clk_get_fixed(_HSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200874 break;
875 case RCC_ASSCKSELR_PLL:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100876 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200877 break;
878 default:
879 break;
880 }
881
882 /* System clock divider */
Yann Gautiere4a3c352019-02-14 10:53:33 +0100883 reg = mmio_read_32(rcc_base + RCC_AXIDIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200884 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
885
886 switch (p) {
887 case _PCLK4:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100888 reg = mmio_read_32(rcc_base + RCC_APB4DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200889 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
890 break;
891 case _PCLK5:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100892 reg = mmio_read_32(rcc_base + RCC_APB5DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200893 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
894 break;
895 default:
896 break;
897 }
898 break;
Yann Gautiered342322019-02-15 17:33:27 +0100899 /* MCU sub system */
900 case _CK_MCU:
901 case _PCLK1:
902 case _PCLK2:
903 case _PCLK3:
904 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR);
905 switch (reg & RCC_SELR_SRC_MASK) {
906 case RCC_MSSCKSELR_HSI:
907 clock = stm32mp1_clk_get_fixed(_HSI);
908 break;
909 case RCC_MSSCKSELR_HSE:
910 clock = stm32mp1_clk_get_fixed(_HSE);
911 break;
912 case RCC_MSSCKSELR_CSI:
913 clock = stm32mp1_clk_get_fixed(_CSI);
914 break;
915 case RCC_MSSCKSELR_PLL:
916 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
917 break;
918 default:
919 break;
920 }
921
922 /* MCU clock divider */
923 reg = mmio_read_32(rcc_base + RCC_MCUDIVR);
924 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
925
926 switch (p) {
927 case _PCLK1:
928 reg = mmio_read_32(rcc_base + RCC_APB1DIVR);
929 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
930 break;
931 case _PCLK2:
932 reg = mmio_read_32(rcc_base + RCC_APB2DIVR);
933 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
934 break;
935 case _PCLK3:
936 reg = mmio_read_32(rcc_base + RCC_APB3DIVR);
937 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
938 break;
939 case _CK_MCU:
940 default:
941 break;
942 }
943 break;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200944 case _CK_PER:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100945 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200946 switch (reg & RCC_SELR_SRC_MASK) {
947 case RCC_CPERCKSELR_HSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100948 clock = stm32mp1_clk_get_fixed(_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200949 break;
950 case RCC_CPERCKSELR_HSE:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100951 clock = stm32mp1_clk_get_fixed(_HSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200952 break;
953 case RCC_CPERCKSELR_CSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100954 clock = stm32mp1_clk_get_fixed(_CSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200955 break;
956 default:
957 break;
958 }
959 break;
960 case _HSI:
961 case _HSI_KER:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100962 clock = stm32mp1_clk_get_fixed(_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200963 break;
964 case _CSI:
965 case _CSI_KER:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100966 clock = stm32mp1_clk_get_fixed(_CSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200967 break;
968 case _HSE:
969 case _HSE_KER:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100970 clock = stm32mp1_clk_get_fixed(_HSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200971 break;
972 case _HSE_KER_DIV2:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100973 clock = stm32mp1_clk_get_fixed(_HSE) >> 1;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200974 break;
Gabriel Fernandez4e3a51a2021-07-27 15:39:16 +0200975 case _HSE_RTC:
976 clock = stm32mp1_clk_get_fixed(_HSE);
977 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U;
978 break;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200979 case _LSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100980 clock = stm32mp1_clk_get_fixed(_LSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200981 break;
982 case _LSE:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100983 clock = stm32mp1_clk_get_fixed(_LSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200984 break;
985 /* PLL */
986 case _PLL1_P:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100987 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200988 break;
989 case _PLL1_Q:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100990 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200991 break;
992 case _PLL1_R:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100993 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200994 break;
995 case _PLL2_P:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100996 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200997 break;
998 case _PLL2_Q:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100999 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001000 break;
1001 case _PLL2_R:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001002 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001003 break;
1004 case _PLL3_P:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001005 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001006 break;
1007 case _PLL3_Q:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001008 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001009 break;
1010 case _PLL3_R:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001011 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001012 break;
1013 case _PLL4_P:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001014 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001015 break;
1016 case _PLL4_Q:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001017 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001018 break;
1019 case _PLL4_R:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001020 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001021 break;
1022 /* Other */
1023 case _USB_PHY_48:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001024 clock = USB_PHY_48_MHZ;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001025 break;
1026 default:
1027 break;
1028 }
1029
1030 return clock;
1031}
1032
Yann Gautiere4a3c352019-02-14 10:53:33 +01001033static void __clk_enable(struct stm32mp1_clk_gate const *gate)
1034{
1035 uintptr_t rcc_base = stm32mp_rcc_base();
1036
Etienne Carriere8a668892019-12-08 08:21:08 +01001037 VERBOSE("Enable clock %u\n", gate->index);
1038
Yann Gautiere4a3c352019-02-14 10:53:33 +01001039 if (gate->set_clr != 0U) {
1040 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit));
1041 } else {
1042 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit));
1043 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001044}
1045
1046static void __clk_disable(struct stm32mp1_clk_gate const *gate)
1047{
1048 uintptr_t rcc_base = stm32mp_rcc_base();
1049
Etienne Carriere8a668892019-12-08 08:21:08 +01001050 VERBOSE("Disable clock %u\n", gate->index);
1051
Yann Gautiere4a3c352019-02-14 10:53:33 +01001052 if (gate->set_clr != 0U) {
1053 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET,
1054 BIT(gate->bit));
1055 } else {
1056 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit));
1057 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001058}
1059
1060static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate)
1061{
1062 uintptr_t rcc_base = stm32mp_rcc_base();
1063
1064 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit);
1065}
1066
1067unsigned int stm32mp1_clk_get_refcount(unsigned long id)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001068{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001069 int i = stm32mp1_clk_get_gated_id(id);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001070
1071 if (i < 0) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001072 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001073 }
1074
Yann Gautiere4a3c352019-02-14 10:53:33 +01001075 return gate_refcounts[i];
Yann Gautier9aea69e2018-07-24 17:13:36 +02001076}
1077
Etienne Carriere481aa002019-12-08 08:21:44 +01001078/* Oscillators and PLLs are not gated at runtime */
1079static bool clock_is_always_on(unsigned long id)
1080{
1081 switch (id) {
1082 case CK_HSE:
1083 case CK_CSI:
1084 case CK_LSI:
1085 case CK_LSE:
1086 case CK_HSI:
1087 case CK_HSE_DIV2:
1088 case PLL1_Q:
1089 case PLL1_R:
1090 case PLL2_P:
1091 case PLL2_Q:
1092 case PLL2_R:
1093 case PLL3_P:
1094 case PLL3_Q:
1095 case PLL3_R:
1096 return true;
1097 default:
1098 return false;
1099 }
1100}
1101
Yann Gautiere4a3c352019-02-14 10:53:33 +01001102void __stm32mp1_clk_enable(unsigned long id, bool secure)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001103{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001104 const struct stm32mp1_clk_gate *gate;
Etienne Carriere481aa002019-12-08 08:21:44 +01001105 int i;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001106 unsigned int *refcnt;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001107
Etienne Carriere481aa002019-12-08 08:21:44 +01001108 if (clock_is_always_on(id)) {
1109 return;
1110 }
1111
1112 i = stm32mp1_clk_get_gated_id(id);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001113 if (i < 0) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001114 ERROR("Clock %d can't be enabled\n", (uint32_t)id);
1115 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001116 }
1117
Yann Gautiere4a3c352019-02-14 10:53:33 +01001118 gate = gate_ref(i);
1119 refcnt = &gate_refcounts[i];
1120
1121 stm32mp1_clk_lock(&refcount_lock);
1122
1123 if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) {
1124 __clk_enable(gate);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001125 }
1126
Yann Gautiere4a3c352019-02-14 10:53:33 +01001127 stm32mp1_clk_unlock(&refcount_lock);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001128}
1129
Yann Gautiere4a3c352019-02-14 10:53:33 +01001130void __stm32mp1_clk_disable(unsigned long id, bool secure)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001131{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001132 const struct stm32mp1_clk_gate *gate;
Etienne Carriere481aa002019-12-08 08:21:44 +01001133 int i;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001134 unsigned int *refcnt;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001135
Etienne Carriere481aa002019-12-08 08:21:44 +01001136 if (clock_is_always_on(id)) {
1137 return;
1138 }
1139
1140 i = stm32mp1_clk_get_gated_id(id);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001141 if (i < 0) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001142 ERROR("Clock %d can't be disabled\n", (uint32_t)id);
1143 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001144 }
1145
Yann Gautiere4a3c352019-02-14 10:53:33 +01001146 gate = gate_ref(i);
1147 refcnt = &gate_refcounts[i];
1148
1149 stm32mp1_clk_lock(&refcount_lock);
1150
1151 if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) {
1152 __clk_disable(gate);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001153 }
1154
Yann Gautiere4a3c352019-02-14 10:53:33 +01001155 stm32mp1_clk_unlock(&refcount_lock);
1156}
1157
1158void stm32mp_clk_enable(unsigned long id)
1159{
1160 __stm32mp1_clk_enable(id, true);
1161}
1162
1163void stm32mp_clk_disable(unsigned long id)
1164{
1165 __stm32mp1_clk_disable(id, true);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001166}
1167
Yann Gautiere4a3c352019-02-14 10:53:33 +01001168bool stm32mp_clk_is_enabled(unsigned long id)
1169{
Etienne Carriere481aa002019-12-08 08:21:44 +01001170 int i;
1171
1172 if (clock_is_always_on(id)) {
1173 return true;
1174 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001175
Etienne Carriere481aa002019-12-08 08:21:44 +01001176 i = stm32mp1_clk_get_gated_id(id);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001177 if (i < 0) {
1178 panic();
1179 }
1180
1181 return __clk_is_enabled(gate_ref(i));
1182}
1183
Yann Gautiera2e2a302019-02-14 11:13:39 +01001184unsigned long stm32mp_clk_get_rate(unsigned long id)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001185{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001186 int p = stm32mp1_clk_get_parent(id);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001187
1188 if (p < 0) {
1189 return 0;
1190 }
1191
Yann Gautiere4a3c352019-02-14 10:53:33 +01001192 return get_clock_rate(p);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001193}
1194
Yann Gautiere4a3c352019-02-14 10:53:33 +01001195static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001196{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001197 uintptr_t address = stm32mp_rcc_base() + offset;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001198
Yann Gautiere4a3c352019-02-14 10:53:33 +01001199 if (enable) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001200 mmio_setbits_32(address, mask_on);
1201 } else {
1202 mmio_clrbits_32(address, mask_on);
1203 }
1204}
1205
Yann Gautiere4a3c352019-02-14 10:53:33 +01001206static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001207{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001208 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR;
1209 uintptr_t address = stm32mp_rcc_base() + offset;
1210
1211 mmio_write_32(address, mask_on);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001212}
1213
Yann Gautiere4a3c352019-02-14 10:53:33 +01001214static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001215{
Yann Gautier2299d572019-02-14 11:14:39 +01001216 uint64_t timeout;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001217 uint32_t mask_test;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001218 uintptr_t address = stm32mp_rcc_base() + offset;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001219
Yann Gautiere4a3c352019-02-14 10:53:33 +01001220 if (enable) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001221 mask_test = mask_rdy;
1222 } else {
1223 mask_test = 0;
1224 }
1225
Yann Gautier2299d572019-02-14 11:14:39 +01001226 timeout = timeout_init_us(OSCRDY_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001227 while ((mmio_read_32(address) & mask_rdy) != mask_test) {
Yann Gautier2299d572019-02-14 11:14:39 +01001228 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001229 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001230 mask_rdy, address, enable, mmio_read_32(address));
1231 return -ETIMEDOUT;
1232 }
1233 }
1234
1235 return 0;
1236}
1237
Yann Gautiere4a3c352019-02-14 10:53:33 +01001238static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001239{
1240 uint32_t value;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001241 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001242
Yann Gautiere4a3c352019-02-14 10:53:33 +01001243 if (digbyp) {
1244 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001245 }
1246
Yann Gautiere4a3c352019-02-14 10:53:33 +01001247 if (bypass || digbyp) {
1248 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP);
1249 }
1250
Yann Gautier9aea69e2018-07-24 17:13:36 +02001251 /*
1252 * Warning: not recommended to switch directly from "high drive"
1253 * to "medium low drive", and vice-versa.
1254 */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001255 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >>
Yann Gautier9aea69e2018-07-24 17:13:36 +02001256 RCC_BDCR_LSEDRV_SHIFT;
1257
1258 while (value != lsedrv) {
1259 if (value > lsedrv) {
1260 value--;
1261 } else {
1262 value++;
1263 }
1264
Yann Gautiere4a3c352019-02-14 10:53:33 +01001265 mmio_clrsetbits_32(rcc_base + RCC_BDCR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001266 RCC_BDCR_LSEDRV_MASK,
1267 value << RCC_BDCR_LSEDRV_SHIFT);
1268 }
1269
Yann Gautiere4a3c352019-02-14 10:53:33 +01001270 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001271}
1272
Yann Gautiere4a3c352019-02-14 10:53:33 +01001273static void stm32mp1_lse_wait(void)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001274{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001275 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001276 VERBOSE("%s: failed\n", __func__);
1277 }
1278}
1279
Yann Gautiere4a3c352019-02-14 10:53:33 +01001280static void stm32mp1_lsi_set(bool enable)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001281{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001282 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION);
1283
1284 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001285 VERBOSE("%s: failed\n", __func__);
1286 }
1287}
1288
Yann Gautiere4a3c352019-02-14 10:53:33 +01001289static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001290{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001291 uintptr_t rcc_base = stm32mp_rcc_base();
1292
1293 if (digbyp) {
1294 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001295 }
1296
Yann Gautiere4a3c352019-02-14 10:53:33 +01001297 if (bypass || digbyp) {
1298 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1299 }
1300
1301 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON);
1302 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001303 VERBOSE("%s: failed\n", __func__);
1304 }
1305
1306 if (css) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001307 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001308 }
1309}
1310
Yann Gautiere4a3c352019-02-14 10:53:33 +01001311static void stm32mp1_csi_set(bool enable)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001312{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001313 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION);
1314 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001315 VERBOSE("%s: failed\n", __func__);
1316 }
1317}
1318
Yann Gautiere4a3c352019-02-14 10:53:33 +01001319static void stm32mp1_hsi_set(bool enable)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001320{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001321 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION);
1322 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001323 VERBOSE("%s: failed\n", __func__);
1324 }
1325}
1326
Yann Gautiere4a3c352019-02-14 10:53:33 +01001327static int stm32mp1_set_hsidiv(uint8_t hsidiv)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001328{
Yann Gautier2299d572019-02-14 11:14:39 +01001329 uint64_t timeout;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001330 uintptr_t rcc_base = stm32mp_rcc_base();
1331 uintptr_t address = rcc_base + RCC_OCRDYR;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001332
Yann Gautiere4a3c352019-02-14 10:53:33 +01001333 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001334 RCC_HSICFGR_HSIDIV_MASK,
1335 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv);
1336
Yann Gautier2299d572019-02-14 11:14:39 +01001337 timeout = timeout_init_us(HSIDIV_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001338 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001339 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001340 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001341 address, mmio_read_32(address));
1342 return -ETIMEDOUT;
1343 }
1344 }
1345
1346 return 0;
1347}
1348
Yann Gautiere4a3c352019-02-14 10:53:33 +01001349static int stm32mp1_hsidiv(unsigned long hsifreq)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001350{
1351 uint8_t hsidiv;
1352 uint32_t hsidivfreq = MAX_HSI_HZ;
1353
1354 for (hsidiv = 0; hsidiv < 4U; hsidiv++) {
1355 if (hsidivfreq == hsifreq) {
1356 break;
1357 }
1358
1359 hsidivfreq /= 2U;
1360 }
1361
1362 if (hsidiv == 4U) {
1363 ERROR("Invalid clk-hsi frequency\n");
1364 return -1;
1365 }
1366
1367 if (hsidiv != 0U) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001368 return stm32mp1_set_hsidiv(hsidiv);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001369 }
1370
1371 return 0;
1372}
1373
Yann Gautiere4a3c352019-02-14 10:53:33 +01001374static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id,
1375 unsigned int clksrc,
1376 uint32_t *pllcfg, int plloff)
1377{
1378 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1379 uintptr_t rcc_base = stm32mp_rcc_base();
1380 uintptr_t pllxcr = rcc_base + pll->pllxcr;
1381 enum stm32mp1_plltype type = pll->plltype;
1382 uintptr_t clksrc_address = rcc_base + (clksrc >> 4);
1383 unsigned long refclk;
1384 uint32_t ifrge = 0U;
Andre Przywara2d5690c2020-03-26 11:50:33 +00001385 uint32_t src, value, fracv = 0;
1386 void *fdt;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001387
1388 /* Check PLL output */
1389 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) {
1390 return false;
1391 }
1392
1393 /* Check current clksrc */
1394 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK;
1395 if (src != (clksrc & RCC_SELR_SRC_MASK)) {
1396 return false;
1397 }
1398
1399 /* Check Div */
1400 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK;
1401
1402 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
1403 (pllcfg[PLLCFG_M] + 1U);
1404
1405 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
1406 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
1407 return false;
1408 }
1409
1410 if ((type == PLL_800) && (refclk >= 8000000U)) {
1411 ifrge = 1U;
1412 }
1413
1414 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1415 RCC_PLLNCFGR1_DIVN_MASK;
1416 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1417 RCC_PLLNCFGR1_DIVM_MASK;
1418 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
1419 RCC_PLLNCFGR1_IFRGE_MASK;
1420 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) {
1421 return false;
1422 }
1423
1424 /* Fractional configuration */
Andre Przywara2d5690c2020-03-26 11:50:33 +00001425 if (fdt_get_address(&fdt) == 1) {
1426 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0);
1427 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001428
1429 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
1430 value |= RCC_PLLNFRACR_FRACLE;
1431 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) {
1432 return false;
1433 }
1434
1435 /* Output config */
1436 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1437 RCC_PLLNCFGR2_DIVP_MASK;
1438 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1439 RCC_PLLNCFGR2_DIVQ_MASK;
1440 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1441 RCC_PLLNCFGR2_DIVR_MASK;
1442 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) {
1443 return false;
1444 }
1445
1446 return true;
1447}
1448
1449static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001450{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001451 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1452 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001453
Yann Gautierd0dcbaa2019-06-04 15:55:37 +02001454 /* Preserve RCC_PLLNCR_SSCG_CTRL value */
1455 mmio_clrsetbits_32(pllxcr,
1456 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1457 RCC_PLLNCR_DIVREN,
1458 RCC_PLLNCR_PLLON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001459}
1460
Yann Gautiere4a3c352019-02-14 10:53:33 +01001461static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001462{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001463 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1464 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
Yann Gautier2299d572019-02-14 11:14:39 +01001465 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001466
Yann Gautier9aea69e2018-07-24 17:13:36 +02001467 /* Wait PLL lock */
1468 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001469 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001470 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001471 pll_id, pllxcr, mmio_read_32(pllxcr));
1472 return -ETIMEDOUT;
1473 }
1474 }
1475
1476 /* Start the requested output */
1477 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1478
1479 return 0;
1480}
1481
Yann Gautiere4a3c352019-02-14 10:53:33 +01001482static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001483{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001484 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1485 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
Yann Gautier2299d572019-02-14 11:14:39 +01001486 uint64_t timeout;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001487
1488 /* Stop all output */
1489 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1490 RCC_PLLNCR_DIVREN);
1491
1492 /* Stop PLL */
1493 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON);
1494
Yann Gautier2299d572019-02-14 11:14:39 +01001495 timeout = timeout_init_us(PLLRDY_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001496 /* Wait PLL stopped */
1497 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001498 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001499 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001500 pll_id, pllxcr, mmio_read_32(pllxcr));
1501 return -ETIMEDOUT;
1502 }
1503 }
1504
1505 return 0;
1506}
1507
Yann Gautiere4a3c352019-02-14 10:53:33 +01001508static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001509 uint32_t *pllcfg)
1510{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001511 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1512 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001513 uint32_t value;
1514
1515 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1516 RCC_PLLNCFGR2_DIVP_MASK;
1517 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1518 RCC_PLLNCFGR2_DIVQ_MASK;
1519 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1520 RCC_PLLNCFGR2_DIVR_MASK;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001521 mmio_write_32(rcc_base + pll->pllxcfgr2, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001522}
1523
Yann Gautiere4a3c352019-02-14 10:53:33 +01001524static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001525 uint32_t *pllcfg, uint32_t fracv)
1526{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001527 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1528 uintptr_t rcc_base = stm32mp_rcc_base();
1529 enum stm32mp1_plltype type = pll->plltype;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001530 unsigned long refclk;
1531 uint32_t ifrge = 0;
1532 uint32_t src, value;
1533
Yann Gautiere4a3c352019-02-14 10:53:33 +01001534 src = mmio_read_32(rcc_base + pll->rckxselr) &
Yann Gautier9aea69e2018-07-24 17:13:36 +02001535 RCC_SELR_REFCLK_SRC_MASK;
1536
Yann Gautiere4a3c352019-02-14 10:53:33 +01001537 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
Yann Gautier9aea69e2018-07-24 17:13:36 +02001538 (pllcfg[PLLCFG_M] + 1U);
1539
1540 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
1541 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
1542 return -EINVAL;
1543 }
1544
1545 if ((type == PLL_800) && (refclk >= 8000000U)) {
1546 ifrge = 1U;
1547 }
1548
1549 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1550 RCC_PLLNCFGR1_DIVN_MASK;
1551 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1552 RCC_PLLNCFGR1_DIVM_MASK;
1553 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
1554 RCC_PLLNCFGR1_IFRGE_MASK;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001555 mmio_write_32(rcc_base + pll->pllxcfgr1, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001556
1557 /* Fractional configuration */
1558 value = 0;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001559 mmio_write_32(rcc_base + pll->pllxfracr, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001560
1561 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001562 mmio_write_32(rcc_base + pll->pllxfracr, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001563
1564 value |= RCC_PLLNFRACR_FRACLE;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001565 mmio_write_32(rcc_base + pll->pllxfracr, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001566
Yann Gautiere4a3c352019-02-14 10:53:33 +01001567 stm32mp1_pll_config_output(pll_id, pllcfg);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001568
1569 return 0;
1570}
1571
Yann Gautiere4a3c352019-02-14 10:53:33 +01001572static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001573{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001574 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001575 uint32_t pllxcsg = 0;
1576
1577 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1578 RCC_PLLNCSGR_MOD_PER_MASK;
1579
1580 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1581 RCC_PLLNCSGR_INC_STEP_MASK;
1582
1583 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1584 RCC_PLLNCSGR_SSCG_MODE_MASK;
1585
Yann Gautiere4a3c352019-02-14 10:53:33 +01001586 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg);
Yann Gautierd0dcbaa2019-06-04 15:55:37 +02001587
1588 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr,
1589 RCC_PLLNCR_SSCG_CTRL);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001590}
1591
Yann Gautiere4a3c352019-02-14 10:53:33 +01001592static int stm32mp1_set_clksrc(unsigned int clksrc)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001593{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001594 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
Yann Gautier2299d572019-02-14 11:14:39 +01001595 uint64_t timeout;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001596
Yann Gautiere4a3c352019-02-14 10:53:33 +01001597 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001598 clksrc & RCC_SELR_SRC_MASK);
1599
Yann Gautier2299d572019-02-14 11:14:39 +01001600 timeout = timeout_init_us(CLKSRC_TIMEOUT);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001601 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001602 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001603 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc,
1604 clksrc_address, mmio_read_32(clksrc_address));
Yann Gautier9aea69e2018-07-24 17:13:36 +02001605 return -ETIMEDOUT;
1606 }
1607 }
1608
1609 return 0;
1610}
1611
Yann Gautiere4a3c352019-02-14 10:53:33 +01001612static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001613{
Yann Gautier2299d572019-02-14 11:14:39 +01001614 uint64_t timeout;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001615
1616 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK,
1617 clkdiv & RCC_DIVR_DIV_MASK);
1618
Yann Gautier2299d572019-02-14 11:14:39 +01001619 timeout = timeout_init_us(CLKDIV_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001620 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001621 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001622 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001623 clkdiv, address, mmio_read_32(address));
1624 return -ETIMEDOUT;
1625 }
1626 }
1627
1628 return 0;
1629}
1630
Yann Gautiere4a3c352019-02-14 10:53:33 +01001631static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001632{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001633 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001634
1635 /*
1636 * Binding clksrc :
1637 * bit15-4 offset
1638 * bit3: disable
1639 * bit2-0: MCOSEL[2:0]
1640 */
1641 if ((clksrc & 0x8U) != 0U) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001642 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001643 } else {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001644 mmio_clrsetbits_32(clksrc_address,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001645 RCC_MCOCFG_MCOSRC_MASK,
1646 clksrc & RCC_MCOCFG_MCOSRC_MASK);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001647 mmio_clrsetbits_32(clksrc_address,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001648 RCC_MCOCFG_MCODIV_MASK,
1649 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001650 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001651 }
1652}
1653
Yann Gautiere4a3c352019-02-14 10:53:33 +01001654static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001655{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001656 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001657
1658 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) ||
1659 (clksrc != (uint32_t)CLK_RTC_DISABLED)) {
1660 mmio_clrsetbits_32(address,
1661 RCC_BDCR_RTCSRC_MASK,
Yann Gautier74aa83a2021-04-06 13:41:19 +02001662 (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001663
1664 mmio_setbits_32(address, RCC_BDCR_RTCCKEN);
1665 }
1666
1667 if (lse_css) {
1668 mmio_setbits_32(address, RCC_BDCR_LSECSSON);
1669 }
1670}
1671
Yann Gautiere4a3c352019-02-14 10:53:33 +01001672static void stm32mp1_stgen_config(void)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001673{
Yann Gautier9aea69e2018-07-24 17:13:36 +02001674 uint32_t cntfid0;
1675 unsigned long rate;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001676 unsigned long long counter;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001677
Yann Gautiera18f61b2020-05-05 17:58:40 +02001678 cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001679 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K));
Yann Gautier9aea69e2018-07-24 17:13:36 +02001680
Yann Gautiere4a3c352019-02-14 10:53:33 +01001681 if (cntfid0 == rate) {
1682 return;
1683 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02001684
Yann Gautiera18f61b2020-05-05 17:58:40 +02001685 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
1686 counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF);
1687 counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001688 counter = (counter * rate / cntfid0);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001689
Yann Gautiera18f61b2020-05-05 17:58:40 +02001690 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter);
1691 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32));
1692 mmio_write_32(STGEN_BASE + CNTFID_OFF, rate);
1693 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001694
Yann Gautiere4a3c352019-02-14 10:53:33 +01001695 write_cntfrq((u_register_t)rate);
1696
1697 /* Need to update timer with new frequency */
1698 generic_delay_timer_init();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001699}
1700
1701void stm32mp1_stgen_increment(unsigned long long offset_in_ms)
1702{
Yann Gautier9aea69e2018-07-24 17:13:36 +02001703 unsigned long long cnt;
1704
Yann Gautiera18f61b2020-05-05 17:58:40 +02001705 cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) |
1706 mmio_read_32(STGEN_BASE + CNTCVL_OFF);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001707
Yann Gautiera18f61b2020-05-05 17:58:40 +02001708 cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001709
Yann Gautiera18f61b2020-05-05 17:58:40 +02001710 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
1711 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt);
1712 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32));
1713 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001714}
1715
Yann Gautiere4a3c352019-02-14 10:53:33 +01001716static void stm32mp1_pkcs_config(uint32_t pkcs)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001717{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001718 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001719 uint32_t value = pkcs & 0xFU;
1720 uint32_t mask = 0xFU;
1721
1722 if ((pkcs & BIT(31)) != 0U) {
1723 mask <<= 4;
1724 value <<= 4;
1725 }
1726
1727 mmio_clrsetbits_32(address, mask, value);
1728}
1729
1730int stm32mp1_clk_init(void)
1731{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001732 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001733 unsigned int clksrc[CLKSRC_NB];
1734 unsigned int clkdiv[CLKDIV_NB];
1735 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1736 int plloff[_PLL_NB];
1737 int ret, len;
1738 enum stm32mp1_pll_id i;
1739 bool lse_css = false;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001740 bool pll3_preserve = false;
1741 bool pll4_preserve = false;
1742 bool pll4_bootrom = false;
Yann Gautierf9af3bc2018-11-09 15:57:18 +01001743 const fdt32_t *pkcs_cell;
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001744 void *fdt;
1745
1746 if (fdt_get_address(&fdt) == 0) {
Yann Gautier360e0e92020-09-16 16:40:34 +02001747 return -FDT_ERR_NOTFOUND;
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001748 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02001749
1750 /* Check status field to disable security */
1751 if (!fdt_get_rcc_secure_status()) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001752 mmio_write_32(rcc_base + RCC_TZCR, 0);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001753 }
1754
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001755 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB,
1756 clksrc);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001757 if (ret < 0) {
1758 return -FDT_ERR_NOTFOUND;
1759 }
1760
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001761 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB,
1762 clkdiv);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001763 if (ret < 0) {
1764 return -FDT_ERR_NOTFOUND;
1765 }
1766
1767 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1768 char name[12];
1769
Antonio Nino Diaz00086e32018-08-16 16:46:06 +01001770 snprintf(name, sizeof(name), "st,pll@%d", i);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001771 plloff[i] = fdt_rcc_subnode_offset(name);
1772
1773 if (!fdt_check_node(plloff[i])) {
1774 continue;
1775 }
1776
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001777 ret = fdt_read_uint32_array(fdt, plloff[i], "cfg",
1778 (int)PLLCFG_NB, pllcfg[i]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001779 if (ret < 0) {
1780 return -FDT_ERR_NOTFOUND;
1781 }
1782 }
1783
Yann Gautiere4a3c352019-02-14 10:53:33 +01001784 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1785 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001786
1787 /*
1788 * Switch ON oscillator found in device-tree.
1789 * Note: HSI already ON after BootROM stage.
1790 */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001791 if (stm32mp1_osc[_LSI] != 0U) {
1792 stm32mp1_lsi_set(true);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001793 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001794 if (stm32mp1_osc[_LSE] != 0U) {
1795 bool bypass, digbyp;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001796 uint32_t lsedrv;
1797
1798 bypass = fdt_osc_read_bool(_LSE, "st,bypass");
Yann Gautiere4a3c352019-02-14 10:53:33 +01001799 digbyp = fdt_osc_read_bool(_LSE, "st,digbypass");
Yann Gautier9aea69e2018-07-24 17:13:36 +02001800 lse_css = fdt_osc_read_bool(_LSE, "st,css");
1801 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive",
1802 LSEDRV_MEDIUM_HIGH);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001803 stm32mp1_lse_enable(bypass, digbyp, lsedrv);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001804 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001805 if (stm32mp1_osc[_HSE] != 0U) {
1806 bool bypass, digbyp, css;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001807
Yann Gautiere4a3c352019-02-14 10:53:33 +01001808 bypass = fdt_osc_read_bool(_HSE, "st,bypass");
1809 digbyp = fdt_osc_read_bool(_HSE, "st,digbypass");
1810 css = fdt_osc_read_bool(_HSE, "st,css");
1811 stm32mp1_hse_enable(bypass, digbyp, css);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001812 }
1813 /*
1814 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1815 * => switch on CSI even if node is not present in device tree
1816 */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001817 stm32mp1_csi_set(true);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001818
1819 /* Come back to HSI */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001820 ret = stm32mp1_set_clksrc(CLK_MPU_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001821 if (ret != 0) {
1822 return ret;
1823 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001824 ret = stm32mp1_set_clksrc(CLK_AXI_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001825 if (ret != 0) {
1826 return ret;
1827 }
Yann Gautiered342322019-02-15 17:33:27 +01001828 ret = stm32mp1_set_clksrc(CLK_MCU_HSI);
1829 if (ret != 0) {
1830 return ret;
1831 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02001832
Yann Gautiere4a3c352019-02-14 10:53:33 +01001833 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) &
1834 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) {
1835 pll3_preserve = stm32mp1_check_pll_conf(_PLL3,
1836 clksrc[CLKSRC_PLL3],
1837 pllcfg[_PLL3],
1838 plloff[_PLL3]);
1839 pll4_preserve = stm32mp1_check_pll_conf(_PLL4,
1840 clksrc[CLKSRC_PLL4],
1841 pllcfg[_PLL4],
1842 plloff[_PLL4]);
1843 }
1844
Yann Gautier9aea69e2018-07-24 17:13:36 +02001845 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001846 if (((i == _PLL3) && pll3_preserve) ||
1847 ((i == _PLL4) && pll4_preserve)) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001848 continue;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001849 }
1850
1851 ret = stm32mp1_pll_stop(i);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001852 if (ret != 0) {
1853 return ret;
1854 }
1855 }
1856
1857 /* Configure HSIDIV */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001858 if (stm32mp1_osc[_HSI] != 0U) {
1859 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001860 if (ret != 0) {
1861 return ret;
1862 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001863 stm32mp1_stgen_config();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001864 }
1865
1866 /* Select DIV */
1867 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001868 mmio_write_32(rcc_base + RCC_MPCKDIVR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001869 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001870 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001871 if (ret != 0) {
1872 return ret;
1873 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001874 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001875 if (ret != 0) {
1876 return ret;
1877 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001878 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001879 if (ret != 0) {
1880 return ret;
1881 }
Yann Gautiered342322019-02-15 17:33:27 +01001882 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR);
1883 if (ret != 0) {
1884 return ret;
1885 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001886 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001887 if (ret != 0) {
1888 return ret;
1889 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001890 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001891 if (ret != 0) {
1892 return ret;
1893 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001894 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001895 if (ret != 0) {
1896 return ret;
1897 }
1898
1899 /* No ready bit for RTC */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001900 mmio_write_32(rcc_base + RCC_RTCDIVR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001901 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK);
1902
1903 /* Configure PLLs source */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001904 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001905 if (ret != 0) {
1906 return ret;
1907 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001908
1909 if (!pll3_preserve) {
1910 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]);
1911 if (ret != 0) {
1912 return ret;
1913 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02001914 }
1915
Yann Gautiere4a3c352019-02-14 10:53:33 +01001916 if (!pll4_preserve) {
1917 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]);
1918 if (ret != 0) {
1919 return ret;
1920 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02001921 }
1922
1923 /* Configure and start PLLs */
1924 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1925 uint32_t fracv;
1926 uint32_t csg[PLLCSG_NB];
1927
Yann Gautiere4a3c352019-02-14 10:53:33 +01001928 if (((i == _PLL3) && pll3_preserve) ||
1929 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) {
1930 continue;
1931 }
1932
Yann Gautier9aea69e2018-07-24 17:13:36 +02001933 if (!fdt_check_node(plloff[i])) {
1934 continue;
1935 }
1936
Yann Gautiere4a3c352019-02-14 10:53:33 +01001937 if ((i == _PLL4) && pll4_bootrom) {
1938 /* Set output divider if not done by the Bootrom */
1939 stm32mp1_pll_config_output(i, pllcfg[i]);
1940 continue;
1941 }
1942
Andre Przywara2d5690c2020-03-26 11:50:33 +00001943 fracv = fdt_read_uint32_default(fdt, plloff[i], "frac", 0);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001944
Yann Gautiere4a3c352019-02-14 10:53:33 +01001945 ret = stm32mp1_pll_config(i, pllcfg[i], fracv);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001946 if (ret != 0) {
1947 return ret;
1948 }
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001949 ret = fdt_read_uint32_array(fdt, plloff[i], "csg",
1950 (uint32_t)PLLCSG_NB, csg);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001951 if (ret == 0) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001952 stm32mp1_pll_csg(i, csg);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001953 } else if (ret != -FDT_ERR_NOTFOUND) {
1954 return ret;
1955 }
1956
Yann Gautiere4a3c352019-02-14 10:53:33 +01001957 stm32mp1_pll_start(i);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001958 }
1959 /* Wait and start PLLs ouptut when ready */
1960 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1961 if (!fdt_check_node(plloff[i])) {
1962 continue;
1963 }
1964
Yann Gautiere4a3c352019-02-14 10:53:33 +01001965 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001966 if (ret != 0) {
1967 return ret;
1968 }
1969 }
1970 /* Wait LSE ready before to use it */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001971 if (stm32mp1_osc[_LSE] != 0U) {
1972 stm32mp1_lse_wait();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001973 }
1974
1975 /* Configure with expected clock source */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001976 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001977 if (ret != 0) {
1978 return ret;
1979 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001980 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001981 if (ret != 0) {
1982 return ret;
1983 }
Yann Gautiered342322019-02-15 17:33:27 +01001984 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]);
1985 if (ret != 0) {
1986 return ret;
1987 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001988 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001989
1990 /* Configure PKCK */
1991 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len);
1992 if (pkcs_cell != NULL) {
1993 bool ckper_disabled = false;
1994 uint32_t j;
1995
Yann Gautier9aea69e2018-07-24 17:13:36 +02001996 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) {
Yann Gautierf9af3bc2018-11-09 15:57:18 +01001997 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001998
1999 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) {
2000 ckper_disabled = true;
2001 continue;
2002 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01002003 stm32mp1_pkcs_config(pkcs);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002004 }
2005
2006 /*
2007 * CKPER is source for some peripheral clocks
2008 * (FMC-NAND / QPSI-NOR) and switching source is allowed
2009 * only if previous clock is still ON
2010 * => deactivated CKPER only after switching clock
2011 */
2012 if (ckper_disabled) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01002013 stm32mp1_pkcs_config(CLK_CKPER_DISABLED);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002014 }
2015 }
2016
2017 /* Switch OFF HSI if not found in device-tree */
Yann Gautiere4a3c352019-02-14 10:53:33 +01002018 if (stm32mp1_osc[_HSI] == 0U) {
2019 stm32mp1_hsi_set(false);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002020 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01002021 stm32mp1_stgen_config();
Yann Gautier9aea69e2018-07-24 17:13:36 +02002022
2023 /* Software Self-Refresh mode (SSR) during DDR initilialization */
Yann Gautiere4a3c352019-02-14 10:53:33 +01002024 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02002025 RCC_DDRITFCR_DDRCKMOD_MASK,
2026 RCC_DDRITFCR_DDRCKMOD_SSR <<
2027 RCC_DDRITFCR_DDRCKMOD_SHIFT);
2028
2029 return 0;
2030}
2031
2032static void stm32mp1_osc_clk_init(const char *name,
Yann Gautier9aea69e2018-07-24 17:13:36 +02002033 enum stm32mp_osc_id index)
2034{
2035 uint32_t frequency;
2036
Yann Gautiere4a3c352019-02-14 10:53:33 +01002037 if (fdt_osc_read_freq(name, &frequency) == 0) {
2038 stm32mp1_osc[index] = frequency;
Yann Gautier9aea69e2018-07-24 17:13:36 +02002039 }
2040}
2041
2042static void stm32mp1_osc_init(void)
2043{
Yann Gautier9aea69e2018-07-24 17:13:36 +02002044 enum stm32mp_osc_id i;
2045
2046 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01002047 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002048 }
2049}
Etienne Carriere1368ada2020-05-13 11:49:49 +02002050
2051#ifdef STM32MP_SHARED_RESOURCES
2052/*
2053 * Get the parent ID of the target parent clock, for tagging as secure
2054 * shared clock dependencies.
2055 */
2056static int get_parent_id_parent(unsigned int parent_id)
2057{
2058 enum stm32mp1_parent_sel s = _UNKNOWN_SEL;
2059 enum stm32mp1_pll_id pll_id;
2060 uint32_t p_sel;
2061 uintptr_t rcc_base = stm32mp_rcc_base();
2062
2063 switch (parent_id) {
2064 case _ACLK:
2065 case _PCLK4:
2066 case _PCLK5:
2067 s = _AXIS_SEL;
2068 break;
2069 case _PLL1_P:
2070 case _PLL1_Q:
2071 case _PLL1_R:
2072 pll_id = _PLL1;
2073 break;
2074 case _PLL2_P:
2075 case _PLL2_Q:
2076 case _PLL2_R:
2077 pll_id = _PLL2;
2078 break;
2079 case _PLL3_P:
2080 case _PLL3_Q:
2081 case _PLL3_R:
2082 pll_id = _PLL3;
2083 break;
2084 case _PLL4_P:
2085 case _PLL4_Q:
2086 case _PLL4_R:
2087 pll_id = _PLL4;
2088 break;
2089 case _PCLK1:
2090 case _PCLK2:
2091 case _HCLK2:
2092 case _HCLK6:
2093 case _CK_PER:
2094 case _CK_MPU:
2095 case _CK_MCU:
2096 case _USB_PHY_48:
2097 /* We do not expect to access these */
2098 panic();
2099 break;
2100 default:
2101 /* Other parents have no parent */
2102 return -1;
2103 }
2104
2105 if (s != _UNKNOWN_SEL) {
2106 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s);
2107
2108 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) &
2109 sel->msk;
2110
2111 if (p_sel < sel->nb_parent) {
2112 return (int)sel->parent[p_sel];
2113 }
2114 } else {
2115 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
2116
2117 p_sel = mmio_read_32(rcc_base + pll->rckxselr) &
2118 RCC_SELR_REFCLK_SRC_MASK;
2119
2120 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) {
2121 return (int)pll->refclk[p_sel];
2122 }
2123 }
2124
2125 VERBOSE("No parent selected for %s\n",
2126 stm32mp1_clk_parent_name[parent_id]);
2127
2128 return -1;
2129}
2130
2131static void secure_parent_clocks(unsigned long parent_id)
2132{
2133 int grandparent_id;
2134
2135 switch (parent_id) {
2136 case _PLL3_P:
2137 case _PLL3_Q:
2138 case _PLL3_R:
2139 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3);
2140 break;
2141
2142 /* These clocks are always secure when RCC is secure */
2143 case _ACLK:
2144 case _HCLK2:
2145 case _HCLK6:
2146 case _PCLK4:
2147 case _PCLK5:
2148 case _PLL1_P:
2149 case _PLL1_Q:
2150 case _PLL1_R:
2151 case _PLL2_P:
2152 case _PLL2_Q:
2153 case _PLL2_R:
2154 case _HSI:
2155 case _HSI_KER:
2156 case _LSI:
2157 case _CSI:
2158 case _CSI_KER:
2159 case _HSE:
2160 case _HSE_KER:
2161 case _HSE_KER_DIV2:
Gabriel Fernandez4e3a51a2021-07-27 15:39:16 +02002162 case _HSE_RTC:
Etienne Carriere1368ada2020-05-13 11:49:49 +02002163 case _LSE:
2164 break;
2165
2166 default:
2167 VERBOSE("Cannot secure parent clock %s\n",
2168 stm32mp1_clk_parent_name[parent_id]);
2169 panic();
2170 }
2171
2172 grandparent_id = get_parent_id_parent(parent_id);
2173 if (grandparent_id >= 0) {
2174 secure_parent_clocks(grandparent_id);
2175 }
2176}
2177
2178void stm32mp1_register_clock_parents_secure(unsigned long clock_id)
2179{
2180 int parent_id;
2181
2182 if (!stm32mp1_rcc_is_secure()) {
2183 return;
2184 }
2185
2186 switch (clock_id) {
2187 case PLL1:
2188 case PLL2:
2189 /* PLL1/PLL2 are always secure: nothing to do */
2190 break;
2191 case PLL3:
2192 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3);
2193 break;
2194 case PLL4:
2195 ERROR("PLL4 cannot be secured\n");
2196 panic();
2197 break;
2198 default:
2199 /* Others are expected gateable clock */
2200 parent_id = stm32mp1_clk_get_parent(clock_id);
2201 if (parent_id < 0) {
2202 INFO("No parent found for clock %lu\n", clock_id);
2203 } else {
2204 secure_parent_clocks(parent_id);
2205 }
2206 break;
2207 }
2208}
2209#endif /* STM32MP_SHARED_RESOURCES */
Yann Gautier9aea69e2018-07-24 17:13:36 +02002210
Yann Gautierc7f9e962019-05-20 14:39:26 +02002211static void sync_earlyboot_clocks_state(void)
2212{
Etienne Carriere2a756c22019-12-08 08:23:35 +01002213 unsigned int idx;
2214 const unsigned long secure_enable[] = {
2215 AXIDCG,
2216 BSEC,
2217 DDRC1, DDRC1LP,
2218 DDRC2, DDRC2LP,
2219 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP,
2220 DDRPHYC, DDRPHYCLP,
Lionel Debievecfa88cc2019-09-02 18:15:45 +02002221 RTCAPB,
Etienne Carriere2a756c22019-12-08 08:23:35 +01002222 TZC1, TZC2,
2223 TZPC,
2224 STGEN_K,
2225 };
2226
2227 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) {
2228 stm32mp_clk_enable(secure_enable[idx]);
2229 }
Yann Gautierc7f9e962019-05-20 14:39:26 +02002230}
2231
Yann Gautier9aea69e2018-07-24 17:13:36 +02002232int stm32mp1_clk_probe(void)
2233{
Yann Gautier9aea69e2018-07-24 17:13:36 +02002234 stm32mp1_osc_init();
2235
Yann Gautierc7f9e962019-05-20 14:39:26 +02002236 sync_earlyboot_clocks_state();
2237
Yann Gautier9aea69e2018-07-24 17:13:36 +02002238 return 0;
2239}