blob: e4cc9b9e8c9d68616fe0a12fdbd96927ed078b1a [file] [log] [blame]
Yann Gautier9aea69e2018-07-24 17:13:36 +02001/*
2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
Yann Gautier9aea69e2018-07-24 17:13:36 +02007#include <assert.h>
Yann Gautier9aea69e2018-07-24 17:13:36 +02008#include <errno.h>
Yann Gautier9aea69e2018-07-24 17:13:36 +02009#include <stdint.h>
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010010#include <stdio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
12#include <libfdt.h>
13
Yann Gautier57e282b2019-01-07 11:17:24 +010014#include <platform_def.h>
15
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <arch.h>
17#include <arch_helpers.h>
18#include <common/debug.h>
19#include <drivers/delay_timer.h>
20#include <drivers/generic_delay_timer.h>
21#include <drivers/st/stm32mp1_clk.h>
22#include <drivers/st/stm32mp1_clkfunc.h>
23#include <drivers/st/stm32mp1_rcc.h>
24#include <dt-bindings/clock/stm32mp1-clks.h>
25#include <dt-bindings/clock/stm32mp1-clksrc.h>
26#include <lib/mmio.h>
27#include <lib/utils_def.h>
28#include <plat/common/platform.h>
29
Yann Gautier9aea69e2018-07-24 17:13:36 +020030#define MAX_HSI_HZ 64000000
31
32#define TIMEOUT_200MS (plat_get_syscnt_freq2() / 5U)
33#define TIMEOUT_1S plat_get_syscnt_freq2()
34
35#define PLLRDY_TIMEOUT TIMEOUT_200MS
36#define CLKSRC_TIMEOUT TIMEOUT_200MS
37#define CLKDIV_TIMEOUT TIMEOUT_200MS
38#define HSIDIV_TIMEOUT TIMEOUT_200MS
39#define OSCRDY_TIMEOUT TIMEOUT_1S
40
41enum stm32mp1_parent_id {
42/* Oscillators are defined in enum stm32mp_osc_id */
43
44/* Other parent source */
45 _HSI_KER = NB_OSC,
46 _HSE_KER,
47 _HSE_KER_DIV2,
48 _CSI_KER,
49 _PLL1_P,
50 _PLL1_Q,
51 _PLL1_R,
52 _PLL2_P,
53 _PLL2_Q,
54 _PLL2_R,
55 _PLL3_P,
56 _PLL3_Q,
57 _PLL3_R,
58 _PLL4_P,
59 _PLL4_Q,
60 _PLL4_R,
61 _ACLK,
62 _PCLK1,
63 _PCLK2,
64 _PCLK3,
65 _PCLK4,
66 _PCLK5,
67 _HCLK6,
68 _HCLK2,
69 _CK_PER,
70 _CK_MPU,
71 _PARENT_NB,
72 _UNKNOWN_ID = 0xff,
73};
74
75enum stm32mp1_parent_sel {
76 _I2C46_SEL,
77 _UART6_SEL,
78 _UART24_SEL,
79 _UART35_SEL,
80 _UART78_SEL,
81 _SDMMC12_SEL,
82 _SDMMC3_SEL,
83 _QSPI_SEL,
84 _FMC_SEL,
85 _USBPHY_SEL,
86 _USBO_SEL,
87 _STGEN_SEL,
88 _PARENT_SEL_NB,
89 _UNKNOWN_SEL = 0xff,
90};
91
92enum stm32mp1_pll_id {
93 _PLL1,
94 _PLL2,
95 _PLL3,
96 _PLL4,
97 _PLL_NB
98};
99
100enum stm32mp1_div_id {
101 _DIV_P,
102 _DIV_Q,
103 _DIV_R,
104 _DIV_NB,
105};
106
107enum stm32mp1_clksrc_id {
108 CLKSRC_MPU,
109 CLKSRC_AXI,
110 CLKSRC_PLL12,
111 CLKSRC_PLL3,
112 CLKSRC_PLL4,
113 CLKSRC_RTC,
114 CLKSRC_MCO1,
115 CLKSRC_MCO2,
116 CLKSRC_NB
117};
118
119enum stm32mp1_clkdiv_id {
120 CLKDIV_MPU,
121 CLKDIV_AXI,
122 CLKDIV_APB1,
123 CLKDIV_APB2,
124 CLKDIV_APB3,
125 CLKDIV_APB4,
126 CLKDIV_APB5,
127 CLKDIV_RTC,
128 CLKDIV_MCO1,
129 CLKDIV_MCO2,
130 CLKDIV_NB
131};
132
133enum stm32mp1_pllcfg {
134 PLLCFG_M,
135 PLLCFG_N,
136 PLLCFG_P,
137 PLLCFG_Q,
138 PLLCFG_R,
139 PLLCFG_O,
140 PLLCFG_NB
141};
142
143enum stm32mp1_pllcsg {
144 PLLCSG_MOD_PER,
145 PLLCSG_INC_STEP,
146 PLLCSG_SSCG_MODE,
147 PLLCSG_NB
148};
149
150enum stm32mp1_plltype {
151 PLL_800,
152 PLL_1600,
153 PLL_TYPE_NB
154};
155
156struct stm32mp1_pll {
157 uint8_t refclk_min;
158 uint8_t refclk_max;
159 uint8_t divn_max;
160};
161
162struct stm32mp1_clk_gate {
163 uint16_t offset;
164 uint8_t bit;
165 uint8_t index;
166 uint8_t set_clr;
167 enum stm32mp1_parent_sel sel;
168 enum stm32mp1_parent_id fixed;
169 bool secure;
170};
171
172struct stm32mp1_clk_sel {
173 uint16_t offset;
174 uint8_t src;
175 uint8_t msk;
176 uint8_t nb_parent;
177 const uint8_t *parent;
178};
179
180#define REFCLK_SIZE 4
181struct stm32mp1_clk_pll {
182 enum stm32mp1_plltype plltype;
183 uint16_t rckxselr;
184 uint16_t pllxcfgr1;
185 uint16_t pllxcfgr2;
186 uint16_t pllxfracr;
187 uint16_t pllxcr;
188 uint16_t pllxcsgr;
189 enum stm32mp_osc_id refclk[REFCLK_SIZE];
190};
191
192struct stm32mp1_clk_data {
193 const struct stm32mp1_clk_gate *gate;
194 const struct stm32mp1_clk_sel *sel;
195 const struct stm32mp1_clk_pll *pll;
196 const int nb_gate;
197};
198
199struct stm32mp1_clk_priv {
200 uint32_t base;
201 const struct stm32mp1_clk_data *data;
202 unsigned long osc[NB_OSC];
203 uint32_t pkcs_usb_value;
204};
205
206#define STM32MP1_CLK(off, b, idx, s) \
207 { \
208 .offset = (off), \
209 .bit = (b), \
210 .index = (idx), \
211 .set_clr = 0, \
212 .sel = (s), \
213 .fixed = _UNKNOWN_ID, \
214 .secure = 0, \
215 }
216
217#define STM32MP1_CLK_F(off, b, idx, f) \
218 { \
219 .offset = (off), \
220 .bit = (b), \
221 .index = (idx), \
222 .set_clr = 0, \
223 .sel = _UNKNOWN_SEL, \
224 .fixed = (f), \
225 .secure = 0, \
226 }
227
228#define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
229 { \
230 .offset = (off), \
231 .bit = (b), \
232 .index = (idx), \
233 .set_clr = 1, \
234 .sel = (s), \
235 .fixed = _UNKNOWN_ID, \
236 .secure = 0, \
237 }
238
239#define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
240 { \
241 .offset = (off), \
242 .bit = (b), \
243 .index = (idx), \
244 .set_clr = 1, \
245 .sel = _UNKNOWN_SEL, \
246 .fixed = (f), \
247 .secure = 0, \
248 }
249
250#define STM32MP1_CLK_SEC_SET_CLR(off, b, idx, s) \
251 { \
252 .offset = (off), \
253 .bit = (b), \
254 .index = (idx), \
255 .set_clr = 1, \
256 .sel = (s), \
257 .fixed = _UNKNOWN_ID, \
258 .secure = 1, \
259 }
260
261#define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
262 [(idx)] = { \
263 .offset = (off), \
264 .src = (s), \
265 .msk = (m), \
266 .parent = (p), \
267 .nb_parent = ARRAY_SIZE((p)) \
268 }
269
270#define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, \
271 off4, off5, off6, \
272 p1, p2, p3, p4) \
273 [(idx)] = { \
274 .plltype = (type), \
275 .rckxselr = (off1), \
276 .pllxcfgr1 = (off2), \
277 .pllxcfgr2 = (off3), \
278 .pllxfracr = (off4), \
279 .pllxcr = (off5), \
280 .pllxcsgr = (off6), \
281 .refclk[0] = (p1), \
282 .refclk[1] = (p2), \
283 .refclk[2] = (p3), \
284 .refclk[3] = (p4), \
285 }
286
287static const uint8_t stm32mp1_clks[][2] = {
288 {CK_PER, _CK_PER},
289 {CK_MPU, _CK_MPU},
290 {CK_AXI, _ACLK},
291 {CK_HSE, _HSE},
292 {CK_CSI, _CSI},
293 {CK_LSI, _LSI},
294 {CK_LSE, _LSE},
295 {CK_HSI, _HSI},
296 {CK_HSE_DIV2, _HSE_KER_DIV2},
297};
298
299static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
300 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
301 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
302 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
303 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
304 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
305 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
306 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
307 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
308 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
309 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
310 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
311
312 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
313 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
314 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
315 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
316 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
317 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
318
319 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
320
321 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
322 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
323 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
324
325 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
326 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
327 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 11, TZC1, _UNKNOWN_SEL),
328 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 12, TZC2, _UNKNOWN_SEL),
329 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
330
331 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
332 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
333
334 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
335 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
336 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
337 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
338 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
339 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
340 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
341 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
342 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
343 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
344 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
345
346 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
347 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 5, HASH1, _UNKNOWN_SEL),
348 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _CSI_KER),
349 STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _UNKNOWN_SEL),
350
351 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
352 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
353 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
354 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
355 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
356
357 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
358};
359
360static const uint8_t i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
361static const uint8_t uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
362 _HSE_KER};
363static const uint8_t uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
364 _HSE_KER};
365static const uint8_t uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
366 _HSE_KER};
367static const uint8_t uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
368 _HSE_KER};
369static const uint8_t sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
370static const uint8_t sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
371static const uint8_t qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
372static const uint8_t fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
373static const uint8_t usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
374static const uint8_t usbo_parents[] = {_PLL4_R, _USB_PHY_48};
375static const uint8_t stgen_parents[] = {_HSI_KER, _HSE_KER};
376
377static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
378 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
379 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
380 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
381 uart24_parents),
382 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
383 uart35_parents),
384 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
385 uart78_parents),
386 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
387 sdmmc12_parents),
388 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
389 sdmmc3_parents),
390 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
391 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
392 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
393 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
394 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
395};
396
397/* Define characteristic of PLL according type */
398#define DIVN_MIN 24
399static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
400 [PLL_800] = {
401 .refclk_min = 4,
402 .refclk_max = 16,
403 .divn_max = 99,
404 },
405 [PLL_1600] = {
406 .refclk_min = 8,
407 .refclk_max = 16,
408 .divn_max = 199,
409 },
410};
411
412/* PLLNCFGR2 register divider by output */
413static const uint8_t pllncfgr2[_DIV_NB] = {
414 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
415 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
416 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT
417};
418
419static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
420 STM32MP1_CLK_PLL(_PLL1, PLL_1600,
421 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
422 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
423 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
424 STM32MP1_CLK_PLL(_PLL2, PLL_1600,
425 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
426 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
427 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
428 STM32MP1_CLK_PLL(_PLL3, PLL_800,
429 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
430 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
431 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID),
432 STM32MP1_CLK_PLL(_PLL4, PLL_800,
433 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
434 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
435 _HSI, _HSE, _CSI, _I2S_CKIN),
436};
437
438/* Prescaler table lookups for clock computation */
439
440/* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */
441#define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
442#define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
443static const uint8_t stm32mp1_mpu_apbx_div[8] = {
444 0, 1, 2, 3, 4, 4, 4, 4
445};
446
447/* div = /1 /2 /3 /4 */
448static const uint8_t stm32mp1_axi_div[8] = {
449 1, 2, 3, 4, 4, 4, 4, 4
450};
451
452static const struct stm32mp1_clk_data stm32mp1_data = {
453 .gate = stm32mp1_clk_gate,
454 .sel = stm32mp1_clk_sel,
455 .pll = stm32mp1_clk_pll,
456 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
457};
458
459static struct stm32mp1_clk_priv stm32mp1_clk_priv_data;
460
461static unsigned long stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv,
462 enum stm32mp_osc_id idx)
463{
464 if (idx >= NB_OSC) {
465 return 0;
466 }
467
468 return priv->osc[idx];
469}
470
471static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
472{
473 const struct stm32mp1_clk_gate *gate = priv->data->gate;
474 int i;
475 int nb_clks = priv->data->nb_gate;
476
477 for (i = 0; i < nb_clks; i++) {
478 if (gate[i].index == id) {
479 return i;
480 }
481 }
482
483 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id);
484
485 return -EINVAL;
486}
487
488static enum stm32mp1_parent_sel
489stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv, int i)
490{
491 const struct stm32mp1_clk_gate *gate = priv->data->gate;
492
493 return gate[i].sel;
494}
495
496static enum stm32mp1_parent_id
497stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv, int i)
498{
499 const struct stm32mp1_clk_gate *gate = priv->data->gate;
500
501 return gate[i].fixed;
502}
503
504static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
505 unsigned long id)
506{
507 const struct stm32mp1_clk_sel *sel = priv->data->sel;
508 uint32_t j, p_sel;
509 int i;
510 enum stm32mp1_parent_id p;
511 enum stm32mp1_parent_sel s;
512
513 for (j = 0; j < ARRAY_SIZE(stm32mp1_clks); j++) {
514 if (stm32mp1_clks[j][0] == id) {
515 return (int)stm32mp1_clks[j][1];
516 }
517 }
518
519 i = stm32mp1_clk_get_id(priv, id);
520 if (i < 0) {
521 return i;
522 }
523
524 p = stm32mp1_clk_get_fixed_parent(priv, i);
525 if (p < _PARENT_NB) {
526 return (int)p;
527 }
528
529 s = stm32mp1_clk_get_sel(priv, i);
530 if (s >= _PARENT_SEL_NB) {
531 return -EINVAL;
532 }
533
534 p_sel = (mmio_read_32(priv->base + sel[s].offset) >> sel[s].src) &
535 sel[s].msk;
536
537 if (p_sel < sel[s].nb_parent) {
538 return (int)sel[s].parent[p_sel];
539 }
540
541 ERROR("%s: no parents defined for clk id %ld\n", __func__, id);
542
543 return -EINVAL;
544}
545
546static unsigned long stm32mp1_pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
547 enum stm32mp1_pll_id pll_id)
548{
549 const struct stm32mp1_clk_pll *pll = priv->data->pll;
550 uint32_t selr, src;
551 unsigned long refclk;
552
553 selr = mmio_read_32(priv->base + pll[pll_id].rckxselr);
554 src = selr & RCC_SELR_REFCLK_SRC_MASK;
555
556 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
557
558 return refclk;
559}
560
561/*
562 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
563 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
564 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
565 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
566 */
567static unsigned long stm32mp1_pll_get_fvco(struct stm32mp1_clk_priv *priv,
568 enum stm32mp1_pll_id pll_id)
569{
570 const struct stm32mp1_clk_pll *pll = priv->data->pll;
571 unsigned long refclk, fvco;
572 uint32_t cfgr1, fracr, divm, divn;
573
574 cfgr1 = mmio_read_32(priv->base + pll[pll_id].pllxcfgr1);
575 fracr = mmio_read_32(priv->base + pll[pll_id].pllxfracr);
576
577 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
578 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
579
580 refclk = stm32mp1_pll_get_fref_ck(priv, pll_id);
581
582 /*
583 * With FRACV :
584 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
585 * Without FRACV
586 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
587 */
588 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) {
589 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
590 >> RCC_PLLNFRACR_FRACV_SHIFT;
591 unsigned long long numerator, denominator;
592
593 numerator = ((unsigned long long)divn + 1U) << 13;
594 numerator = (refclk * numerator) + fracv;
595 denominator = ((unsigned long long)divm + 1U) << 13;
596 fvco = (unsigned long)(numerator / denominator);
597 } else {
598 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U));
599 }
600
601 return fvco;
602}
603
604static unsigned long stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
605 enum stm32mp1_pll_id pll_id,
606 enum stm32mp1_div_id div_id)
607{
608 const struct stm32mp1_clk_pll *pll = priv->data->pll;
609 unsigned long dfout;
610 uint32_t cfgr2, divy;
611
612 if (div_id >= _DIV_NB) {
613 return 0;
614 }
615
616 cfgr2 = mmio_read_32(priv->base + pll[pll_id].pllxcfgr2);
617 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
618
619 dfout = stm32mp1_pll_get_fvco(priv, pll_id) / (divy + 1U);
620
621 return dfout;
622}
623
624static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
625{
626 uint32_t reg, clkdiv;
627 unsigned long clock = 0;
628
629 switch (p) {
630 case _CK_MPU:
631 /* MPU sub system */
632 reg = mmio_read_32(priv->base + RCC_MPCKSELR);
633 switch (reg & RCC_SELR_SRC_MASK) {
634 case RCC_MPCKSELR_HSI:
635 clock = stm32mp1_clk_get_fixed(priv, _HSI);
636 break;
637 case RCC_MPCKSELR_HSE:
638 clock = stm32mp1_clk_get_fixed(priv, _HSE);
639 break;
640 case RCC_MPCKSELR_PLL:
641 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
642 break;
643 case RCC_MPCKSELR_PLL_MPUDIV:
644 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
645
646 reg = mmio_read_32(priv->base + RCC_MPCKDIVR);
647 clkdiv = reg & RCC_MPUDIV_MASK;
648 if (clkdiv != 0U) {
649 clock /= stm32mp1_mpu_div[clkdiv];
650 }
651
652 break;
653 default:
654 break;
655 }
656 break;
657 /* AXI sub system */
658 case _ACLK:
659 case _HCLK2:
660 case _HCLK6:
661 case _PCLK4:
662 case _PCLK5:
663 reg = mmio_read_32(priv->base + RCC_ASSCKSELR);
664 switch (reg & RCC_SELR_SRC_MASK) {
665 case RCC_ASSCKSELR_HSI:
666 clock = stm32mp1_clk_get_fixed(priv, _HSI);
667 break;
668 case RCC_ASSCKSELR_HSE:
669 clock = stm32mp1_clk_get_fixed(priv, _HSE);
670 break;
671 case RCC_ASSCKSELR_PLL:
672 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
673 break;
674 default:
675 break;
676 }
677
678 /* System clock divider */
679 reg = mmio_read_32(priv->base + RCC_AXIDIVR);
680 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
681
682 switch (p) {
683 case _PCLK4:
684 reg = mmio_read_32(priv->base + RCC_APB4DIVR);
685 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
686 break;
687 case _PCLK5:
688 reg = mmio_read_32(priv->base + RCC_APB5DIVR);
689 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
690 break;
691 default:
692 break;
693 }
694 break;
695 case _CK_PER:
696 reg = mmio_read_32(priv->base + RCC_CPERCKSELR);
697 switch (reg & RCC_SELR_SRC_MASK) {
698 case RCC_CPERCKSELR_HSI:
699 clock = stm32mp1_clk_get_fixed(priv, _HSI);
700 break;
701 case RCC_CPERCKSELR_HSE:
702 clock = stm32mp1_clk_get_fixed(priv, _HSE);
703 break;
704 case RCC_CPERCKSELR_CSI:
705 clock = stm32mp1_clk_get_fixed(priv, _CSI);
706 break;
707 default:
708 break;
709 }
710 break;
711 case _HSI:
712 case _HSI_KER:
713 clock = stm32mp1_clk_get_fixed(priv, _HSI);
714 break;
715 case _CSI:
716 case _CSI_KER:
717 clock = stm32mp1_clk_get_fixed(priv, _CSI);
718 break;
719 case _HSE:
720 case _HSE_KER:
721 clock = stm32mp1_clk_get_fixed(priv, _HSE);
722 break;
723 case _HSE_KER_DIV2:
724 clock = stm32mp1_clk_get_fixed(priv, _HSE) >> 1;
725 break;
726 case _LSI:
727 clock = stm32mp1_clk_get_fixed(priv, _LSI);
728 break;
729 case _LSE:
730 clock = stm32mp1_clk_get_fixed(priv, _LSE);
731 break;
732 /* PLL */
733 case _PLL1_P:
734 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
735 break;
736 case _PLL1_Q:
737 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_Q);
738 break;
739 case _PLL1_R:
740 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_R);
741 break;
742 case _PLL2_P:
743 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
744 break;
745 case _PLL2_Q:
746 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_Q);
747 break;
748 case _PLL2_R:
749 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_R);
750 break;
751 case _PLL3_P:
752 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
753 break;
754 case _PLL3_Q:
755 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_Q);
756 break;
757 case _PLL3_R:
758 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_R);
759 break;
760 case _PLL4_P:
761 clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_P);
762 break;
763 case _PLL4_Q:
764 clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_Q);
765 break;
766 case _PLL4_R:
767 clock = stm32mp1_read_pll_freq(priv, _PLL4, _DIV_R);
768 break;
769 /* Other */
770 case _USB_PHY_48:
771 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
772 break;
773 default:
774 break;
775 }
776
777 return clock;
778}
779
780bool stm32mp1_clk_is_enabled(unsigned long id)
781{
782 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data;
783 const struct stm32mp1_clk_gate *gate = priv->data->gate;
784 int i = stm32mp1_clk_get_id(priv, id);
785
786 if (i < 0) {
787 return false;
788 }
789
790 return ((mmio_read_32(priv->base + gate[i].offset) &
791 BIT(gate[i].bit)) != 0U);
792}
793
794int stm32mp1_clk_enable(unsigned long id)
795{
796 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data;
797 const struct stm32mp1_clk_gate *gate = priv->data->gate;
798 int i = stm32mp1_clk_get_id(priv, id);
799
800 if (i < 0) {
801 return i;
802 }
803
804 if (gate[i].set_clr != 0U) {
805 mmio_write_32(priv->base + gate[i].offset, BIT(gate[i].bit));
806 } else {
807 mmio_setbits_32(priv->base + gate[i].offset, BIT(gate[i].bit));
808 }
809
810 return 0;
811}
812
813int stm32mp1_clk_disable(unsigned long id)
814{
815 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data;
816 const struct stm32mp1_clk_gate *gate = priv->data->gate;
817 int i = stm32mp1_clk_get_id(priv, id);
818
819 if (i < 0) {
820 return i;
821 }
822
823 if (gate[i].set_clr != 0U) {
824 mmio_write_32(priv->base + gate[i].offset
825 + RCC_MP_ENCLRR_OFFSET,
826 BIT(gate[i].bit));
827 } else {
828 mmio_clrbits_32(priv->base + gate[i].offset, BIT(gate[i].bit));
829 }
830
831 return 0;
832}
833
834unsigned long stm32mp1_clk_get_rate(unsigned long id)
835{
836 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data;
837 int p = stm32mp1_clk_get_parent(priv, id);
838 unsigned long rate;
839
840 if (p < 0) {
841 return 0;
842 }
843
844 rate = stm32mp1_clk_get(priv, p);
845
846 return rate;
847}
848
849static void stm32mp1_ls_osc_set(int enable, uint32_t rcc, uint32_t offset,
850 uint32_t mask_on)
851{
852 uint32_t address = rcc + offset;
853
854 if (enable != 0) {
855 mmio_setbits_32(address, mask_on);
856 } else {
857 mmio_clrbits_32(address, mask_on);
858 }
859}
860
861static void stm32mp1_hs_ocs_set(int enable, uint32_t rcc, uint32_t mask_on)
862{
863 if (enable != 0) {
864 mmio_setbits_32(rcc + RCC_OCENSETR, mask_on);
865 } else {
866 mmio_setbits_32(rcc + RCC_OCENCLRR, mask_on);
867 }
868}
869
870static int stm32mp1_osc_wait(int enable, uint32_t rcc, uint32_t offset,
871 uint32_t mask_rdy)
872{
873 unsigned long start;
874 uint32_t mask_test;
875 uint32_t address = rcc + offset;
876
877 if (enable != 0) {
878 mask_test = mask_rdy;
879 } else {
880 mask_test = 0;
881 }
882
883 start = get_timer(0);
884 while ((mmio_read_32(address) & mask_rdy) != mask_test) {
885 if (get_timer(start) > OSCRDY_TIMEOUT) {
886 ERROR("OSC %x @ %x timeout for enable=%d : 0x%x\n",
887 mask_rdy, address, enable, mmio_read_32(address));
888 return -ETIMEDOUT;
889 }
890 }
891
892 return 0;
893}
894
895static void stm32mp1_lse_enable(uint32_t rcc, bool bypass, uint32_t lsedrv)
896{
897 uint32_t value;
898
899 if (bypass) {
900 mmio_setbits_32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
901 }
902
903 /*
904 * Warning: not recommended to switch directly from "high drive"
905 * to "medium low drive", and vice-versa.
906 */
907 value = (mmio_read_32(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >>
908 RCC_BDCR_LSEDRV_SHIFT;
909
910 while (value != lsedrv) {
911 if (value > lsedrv) {
912 value--;
913 } else {
914 value++;
915 }
916
917 mmio_clrsetbits_32(rcc + RCC_BDCR,
918 RCC_BDCR_LSEDRV_MASK,
919 value << RCC_BDCR_LSEDRV_SHIFT);
920 }
921
922 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
923}
924
925static void stm32mp1_lse_wait(uint32_t rcc)
926{
927 if (stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY) != 0) {
928 VERBOSE("%s: failed\n", __func__);
929 }
930}
931
932static void stm32mp1_lsi_set(uint32_t rcc, int enable)
933{
934 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
935 if (stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) !=
936 0) {
937 VERBOSE("%s: failed\n", __func__);
938 }
939}
940
941static void stm32mp1_hse_enable(uint32_t rcc, bool bypass, bool css)
942{
943 if (bypass) {
944 mmio_setbits_32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
945 }
946
947 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
948 if (stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY) !=
949 0) {
950 VERBOSE("%s: failed\n", __func__);
951 }
952
953 if (css) {
954 mmio_setbits_32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
955 }
956}
957
958static void stm32mp1_csi_set(uint32_t rcc, int enable)
959{
960 stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
961 if (stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) !=
962 0) {
963 VERBOSE("%s: failed\n", __func__);
964 }
965}
966
967static void stm32mp1_hsi_set(uint32_t rcc, int enable)
968{
969 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
970 if (stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) !=
971 0) {
972 VERBOSE("%s: failed\n", __func__);
973 }
974}
975
976static int stm32mp1_set_hsidiv(uint32_t rcc, uint8_t hsidiv)
977{
978 unsigned long start;
979 uint32_t address = rcc + RCC_OCRDYR;
980
981 mmio_clrsetbits_32(rcc + RCC_HSICFGR,
982 RCC_HSICFGR_HSIDIV_MASK,
983 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv);
984
985 start = get_timer(0);
986 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) {
987 if (get_timer(start) > HSIDIV_TIMEOUT) {
988 ERROR("HSIDIV failed @ 0x%x: 0x%x\n",
989 address, mmio_read_32(address));
990 return -ETIMEDOUT;
991 }
992 }
993
994 return 0;
995}
996
997static int stm32mp1_hsidiv(uint32_t rcc, unsigned long hsifreq)
998{
999 uint8_t hsidiv;
1000 uint32_t hsidivfreq = MAX_HSI_HZ;
1001
1002 for (hsidiv = 0; hsidiv < 4U; hsidiv++) {
1003 if (hsidivfreq == hsifreq) {
1004 break;
1005 }
1006
1007 hsidivfreq /= 2U;
1008 }
1009
1010 if (hsidiv == 4U) {
1011 ERROR("Invalid clk-hsi frequency\n");
1012 return -1;
1013 }
1014
1015 if (hsidiv != 0U) {
1016 return stm32mp1_set_hsidiv(rcc, hsidiv);
1017 }
1018
1019 return 0;
1020}
1021
1022static void stm32mp1_pll_start(struct stm32mp1_clk_priv *priv,
1023 enum stm32mp1_pll_id pll_id)
1024{
1025 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1026
1027 mmio_write_32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_PLLON);
1028}
1029
1030static int stm32mp1_pll_output(struct stm32mp1_clk_priv *priv,
1031 enum stm32mp1_pll_id pll_id, uint32_t output)
1032{
1033 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1034 uint32_t pllxcr = priv->base + pll[pll_id].pllxcr;
1035 unsigned long start;
1036
1037 start = get_timer(0);
1038 /* Wait PLL lock */
1039 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) {
1040 if (get_timer(start) > PLLRDY_TIMEOUT) {
1041 ERROR("PLL%d start failed @ 0x%x: 0x%x\n",
1042 pll_id, pllxcr, mmio_read_32(pllxcr));
1043 return -ETIMEDOUT;
1044 }
1045 }
1046
1047 /* Start the requested output */
1048 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1049
1050 return 0;
1051}
1052
1053static int stm32mp1_pll_stop(struct stm32mp1_clk_priv *priv,
1054 enum stm32mp1_pll_id pll_id)
1055{
1056 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1057 uint32_t pllxcr = priv->base + pll[pll_id].pllxcr;
1058 unsigned long start;
1059
1060 /* Stop all output */
1061 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1062 RCC_PLLNCR_DIVREN);
1063
1064 /* Stop PLL */
1065 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON);
1066
1067 start = get_timer(0);
1068 /* Wait PLL stopped */
1069 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) {
1070 if (get_timer(start) > PLLRDY_TIMEOUT) {
1071 ERROR("PLL%d stop failed @ 0x%x: 0x%x\n",
1072 pll_id, pllxcr, mmio_read_32(pllxcr));
1073 return -ETIMEDOUT;
1074 }
1075 }
1076
1077 return 0;
1078}
1079
1080static void stm32mp1_pll_config_output(struct stm32mp1_clk_priv *priv,
1081 enum stm32mp1_pll_id pll_id,
1082 uint32_t *pllcfg)
1083{
1084 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1085 uint32_t rcc = priv->base;
1086 uint32_t value;
1087
1088 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1089 RCC_PLLNCFGR2_DIVP_MASK;
1090 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1091 RCC_PLLNCFGR2_DIVQ_MASK;
1092 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1093 RCC_PLLNCFGR2_DIVR_MASK;
1094 mmio_write_32(rcc + pll[pll_id].pllxcfgr2, value);
1095}
1096
1097static int stm32mp1_pll_config(struct stm32mp1_clk_priv *priv,
1098 enum stm32mp1_pll_id pll_id,
1099 uint32_t *pllcfg, uint32_t fracv)
1100{
1101 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1102 uint32_t rcc = priv->base;
1103 enum stm32mp1_plltype type = pll[pll_id].plltype;
1104 unsigned long refclk;
1105 uint32_t ifrge = 0;
1106 uint32_t src, value;
1107
1108 src = mmio_read_32(priv->base + pll[pll_id].rckxselr) &
1109 RCC_SELR_REFCLK_SRC_MASK;
1110
1111 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1112 (pllcfg[PLLCFG_M] + 1U);
1113
1114 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
1115 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
1116 return -EINVAL;
1117 }
1118
1119 if ((type == PLL_800) && (refclk >= 8000000U)) {
1120 ifrge = 1U;
1121 }
1122
1123 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1124 RCC_PLLNCFGR1_DIVN_MASK;
1125 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1126 RCC_PLLNCFGR1_DIVM_MASK;
1127 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
1128 RCC_PLLNCFGR1_IFRGE_MASK;
1129 mmio_write_32(rcc + pll[pll_id].pllxcfgr1, value);
1130
1131 /* Fractional configuration */
1132 value = 0;
1133 mmio_write_32(rcc + pll[pll_id].pllxfracr, value);
1134
1135 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
1136 mmio_write_32(rcc + pll[pll_id].pllxfracr, value);
1137
1138 value |= RCC_PLLNFRACR_FRACLE;
1139 mmio_write_32(rcc + pll[pll_id].pllxfracr, value);
1140
1141 stm32mp1_pll_config_output(priv, pll_id, pllcfg);
1142
1143 return 0;
1144}
1145
1146static void stm32mp1_pll_csg(struct stm32mp1_clk_priv *priv,
1147 enum stm32mp1_pll_id pll_id,
1148 uint32_t *csg)
1149{
1150 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1151 uint32_t pllxcsg = 0;
1152
1153 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1154 RCC_PLLNCSGR_MOD_PER_MASK;
1155
1156 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1157 RCC_PLLNCSGR_INC_STEP_MASK;
1158
1159 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1160 RCC_PLLNCSGR_SSCG_MODE_MASK;
1161
1162 mmio_write_32(priv->base + pll[pll_id].pllxcsgr, pllxcsg);
1163}
1164
1165static int stm32mp1_set_clksrc(struct stm32mp1_clk_priv *priv,
1166 unsigned int clksrc)
1167{
1168 uint32_t address = priv->base + (clksrc >> 4);
1169 unsigned long start;
1170
1171 mmio_clrsetbits_32(address, RCC_SELR_SRC_MASK,
1172 clksrc & RCC_SELR_SRC_MASK);
1173
1174 start = get_timer(0);
1175 while ((mmio_read_32(address) & RCC_SELR_SRCRDY) == 0U) {
1176 if (get_timer(start) > CLKSRC_TIMEOUT) {
1177 ERROR("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1178 clksrc, address, mmio_read_32(address));
1179 return -ETIMEDOUT;
1180 }
1181 }
1182
1183 return 0;
1184}
1185
1186static int stm32mp1_set_clkdiv(unsigned int clkdiv, uint32_t address)
1187{
1188 unsigned long start;
1189
1190 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK,
1191 clkdiv & RCC_DIVR_DIV_MASK);
1192
1193 start = get_timer(0);
1194 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) {
1195 if (get_timer(start) > CLKDIV_TIMEOUT) {
1196 ERROR("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1197 clkdiv, address, mmio_read_32(address));
1198 return -ETIMEDOUT;
1199 }
1200 }
1201
1202 return 0;
1203}
1204
1205static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1206 uint32_t clksrc, uint32_t clkdiv)
1207{
1208 uint32_t address = priv->base + (clksrc >> 4);
1209
1210 /*
1211 * Binding clksrc :
1212 * bit15-4 offset
1213 * bit3: disable
1214 * bit2-0: MCOSEL[2:0]
1215 */
1216 if ((clksrc & 0x8U) != 0U) {
1217 mmio_clrbits_32(address, RCC_MCOCFG_MCOON);
1218 } else {
1219 mmio_clrsetbits_32(address,
1220 RCC_MCOCFG_MCOSRC_MASK,
1221 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1222 mmio_clrsetbits_32(address,
1223 RCC_MCOCFG_MCODIV_MASK,
1224 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1225 mmio_setbits_32(address, RCC_MCOCFG_MCOON);
1226 }
1227}
1228
1229static void stm32mp1_set_rtcsrc(struct stm32mp1_clk_priv *priv,
1230 unsigned int clksrc, bool lse_css)
1231{
1232 uint32_t address = priv->base + RCC_BDCR;
1233
1234 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) ||
1235 (clksrc != (uint32_t)CLK_RTC_DISABLED)) {
1236 mmio_clrsetbits_32(address,
1237 RCC_BDCR_RTCSRC_MASK,
1238 clksrc << RCC_BDCR_RTCSRC_SHIFT);
1239
1240 mmio_setbits_32(address, RCC_BDCR_RTCCKEN);
1241 }
1242
1243 if (lse_css) {
1244 mmio_setbits_32(address, RCC_BDCR_LSECSSON);
1245 }
1246}
1247
1248#define CNTCVL_OFF 0x008
1249#define CNTCVU_OFF 0x00C
1250
1251static void stm32mp1_stgen_config(struct stm32mp1_clk_priv *priv)
1252{
1253 uintptr_t stgen;
1254 int p;
1255 uint32_t cntfid0;
1256 unsigned long rate;
1257
1258 stgen = fdt_get_stgen_base();
1259
1260 cntfid0 = mmio_read_32(stgen + CNTFID_OFF);
1261 p = stm32mp1_clk_get_parent(priv, STGEN_K);
1262 rate = stm32mp1_clk_get(priv, p);
1263
1264 if (cntfid0 != rate) {
1265 unsigned long long counter;
1266
1267 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
1268 counter = (unsigned long long)
1269 mmio_read_32(stgen + CNTCVL_OFF);
1270 counter |= ((unsigned long long)
1271 (mmio_read_32(stgen + CNTCVU_OFF))) << 32;
1272 counter = (counter * rate / cntfid0);
1273 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter);
1274 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32));
1275 mmio_write_32(stgen + CNTFID_OFF, rate);
1276 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
1277
1278 write_cntfrq((u_register_t)rate);
1279
1280 /* Need to update timer with new frequency */
1281 generic_delay_timer_init();
1282 }
1283}
1284
1285void stm32mp1_stgen_increment(unsigned long long offset_in_ms)
1286{
1287 uintptr_t stgen;
1288 unsigned long long cnt;
1289
1290 stgen = fdt_get_stgen_base();
1291
1292 cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) |
1293 mmio_read_32(stgen + CNTCVL_OFF);
1294
1295 cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U;
1296
1297 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
1298 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt);
1299 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32));
1300 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
1301}
1302
1303static void stm32mp1_pkcs_config(struct stm32mp1_clk_priv *priv, uint32_t pkcs)
1304{
1305 uint32_t address = priv->base + ((pkcs >> 4) & 0xFFFU);
1306 uint32_t value = pkcs & 0xFU;
1307 uint32_t mask = 0xFU;
1308
1309 if ((pkcs & BIT(31)) != 0U) {
1310 mask <<= 4;
1311 value <<= 4;
1312 }
1313
1314 mmio_clrsetbits_32(address, mask, value);
1315}
1316
1317int stm32mp1_clk_init(void)
1318{
1319 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data;
1320 uint32_t rcc = priv->base;
1321 unsigned int clksrc[CLKSRC_NB];
1322 unsigned int clkdiv[CLKDIV_NB];
1323 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1324 int plloff[_PLL_NB];
1325 int ret, len;
1326 enum stm32mp1_pll_id i;
1327 bool lse_css = false;
Yann Gautierf9af3bc2018-11-09 15:57:18 +01001328 const fdt32_t *pkcs_cell;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001329
1330 /* Check status field to disable security */
1331 if (!fdt_get_rcc_secure_status()) {
1332 mmio_write_32(rcc + RCC_TZCR, 0);
1333 }
1334
1335 ret = fdt_rcc_read_uint32_array("st,clksrc", clksrc,
1336 (uint32_t)CLKSRC_NB);
1337 if (ret < 0) {
1338 return -FDT_ERR_NOTFOUND;
1339 }
1340
1341 ret = fdt_rcc_read_uint32_array("st,clkdiv", clkdiv,
1342 (uint32_t)CLKDIV_NB);
1343 if (ret < 0) {
1344 return -FDT_ERR_NOTFOUND;
1345 }
1346
1347 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1348 char name[12];
1349
Antonio Nino Diaz00086e32018-08-16 16:46:06 +01001350 snprintf(name, sizeof(name), "st,pll@%d", i);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001351 plloff[i] = fdt_rcc_subnode_offset(name);
1352
1353 if (!fdt_check_node(plloff[i])) {
1354 continue;
1355 }
1356
1357 ret = fdt_read_uint32_array(plloff[i], "cfg",
1358 pllcfg[i], (int)PLLCFG_NB);
1359 if (ret < 0) {
1360 return -FDT_ERR_NOTFOUND;
1361 }
1362 }
1363
1364 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1365 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1366
1367 /*
1368 * Switch ON oscillator found in device-tree.
1369 * Note: HSI already ON after BootROM stage.
1370 */
1371 if (priv->osc[_LSI] != 0U) {
1372 stm32mp1_lsi_set(rcc, 1);
1373 }
1374 if (priv->osc[_LSE] != 0U) {
1375 bool bypass;
1376 uint32_t lsedrv;
1377
1378 bypass = fdt_osc_read_bool(_LSE, "st,bypass");
1379 lse_css = fdt_osc_read_bool(_LSE, "st,css");
1380 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive",
1381 LSEDRV_MEDIUM_HIGH);
1382 stm32mp1_lse_enable(rcc, bypass, lsedrv);
1383 }
1384 if (priv->osc[_HSE] != 0U) {
1385 bool bypass, css;
1386
1387 bypass = fdt_osc_read_bool(_LSE, "st,bypass");
1388 css = fdt_osc_read_bool(_LSE, "st,css");
1389 stm32mp1_hse_enable(rcc, bypass, css);
1390 }
1391 /*
1392 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1393 * => switch on CSI even if node is not present in device tree
1394 */
1395 stm32mp1_csi_set(rcc, 1);
1396
1397 /* Come back to HSI */
1398 ret = stm32mp1_set_clksrc(priv, CLK_MPU_HSI);
1399 if (ret != 0) {
1400 return ret;
1401 }
1402 ret = stm32mp1_set_clksrc(priv, CLK_AXI_HSI);
1403 if (ret != 0) {
1404 return ret;
1405 }
1406
1407 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1408 if (i == _PLL4)
1409 continue;
1410 ret = stm32mp1_pll_stop(priv, i);
1411 if (ret != 0) {
1412 return ret;
1413 }
1414 }
1415
1416 /* Configure HSIDIV */
1417 if (priv->osc[_HSI] != 0U) {
1418 ret = stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1419 if (ret != 0) {
1420 return ret;
1421 }
1422 stm32mp1_stgen_config(priv);
1423 }
1424
1425 /* Select DIV */
1426 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1427 mmio_write_32(rcc + RCC_MPCKDIVR,
1428 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK);
1429 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1430 if (ret != 0) {
1431 return ret;
1432 }
1433 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1434 if (ret != 0) {
1435 return ret;
1436 }
1437 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1438 if (ret != 0) {
1439 return ret;
1440 }
1441 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1442 if (ret != 0) {
1443 return ret;
1444 }
1445 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1446 if (ret != 0) {
1447 return ret;
1448 }
1449 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1450 if (ret != 0) {
1451 return ret;
1452 }
1453
1454 /* No ready bit for RTC */
1455 mmio_write_32(rcc + RCC_RTCDIVR,
1456 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK);
1457
1458 /* Configure PLLs source */
1459 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1460 if (ret != 0) {
1461 return ret;
1462 }
1463 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1464 if (ret != 0) {
1465 return ret;
1466 }
1467
1468 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1469 if (ret != 0) {
1470 return ret;
1471 }
1472
1473 /* Configure and start PLLs */
1474 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1475 uint32_t fracv;
1476 uint32_t csg[PLLCSG_NB];
1477
1478 if (!fdt_check_node(plloff[i])) {
1479 continue;
1480 }
1481
1482 fracv = fdt_read_uint32_default(plloff[i], "frac", 0);
1483
1484 ret = stm32mp1_pll_config(priv, i, pllcfg[i], fracv);
1485 if (ret != 0) {
1486 return ret;
1487 }
1488 ret = fdt_read_uint32_array(plloff[i], "csg", csg,
1489 (uint32_t)PLLCSG_NB);
1490 if (ret == 0) {
1491 stm32mp1_pll_csg(priv, i, csg);
1492 } else if (ret != -FDT_ERR_NOTFOUND) {
1493 return ret;
1494 }
1495
1496 stm32mp1_pll_start(priv, i);
1497 }
1498 /* Wait and start PLLs ouptut when ready */
1499 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1500 if (!fdt_check_node(plloff[i])) {
1501 continue;
1502 }
1503
1504 ret = stm32mp1_pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1505 if (ret != 0) {
1506 return ret;
1507 }
1508 }
1509 /* Wait LSE ready before to use it */
1510 if (priv->osc[_LSE] != 0U) {
1511 stm32mp1_lse_wait(rcc);
1512 }
1513
1514 /* Configure with expected clock source */
1515 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_MPU]);
1516 if (ret != 0) {
1517 return ret;
1518 }
1519 ret = stm32mp1_set_clksrc(priv, clksrc[CLKSRC_AXI]);
1520 if (ret != 0) {
1521 return ret;
1522 }
1523 stm32mp1_set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1524
1525 /* Configure PKCK */
1526 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len);
1527 if (pkcs_cell != NULL) {
1528 bool ckper_disabled = false;
1529 uint32_t j;
1530
1531 priv->pkcs_usb_value = 0;
1532
1533 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) {
Yann Gautierf9af3bc2018-11-09 15:57:18 +01001534 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001535
1536 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) {
1537 ckper_disabled = true;
1538 continue;
1539 }
1540 stm32mp1_pkcs_config(priv, pkcs);
1541 }
1542
1543 /*
1544 * CKPER is source for some peripheral clocks
1545 * (FMC-NAND / QPSI-NOR) and switching source is allowed
1546 * only if previous clock is still ON
1547 * => deactivated CKPER only after switching clock
1548 */
1549 if (ckper_disabled) {
1550 stm32mp1_pkcs_config(priv, CLK_CKPER_DISABLED);
1551 }
1552 }
1553
1554 /* Switch OFF HSI if not found in device-tree */
1555 if (priv->osc[_HSI] == 0U) {
1556 stm32mp1_hsi_set(rcc, 0);
1557 }
1558 stm32mp1_stgen_config(priv);
1559
1560 /* Software Self-Refresh mode (SSR) during DDR initilialization */
1561 mmio_clrsetbits_32(priv->base + RCC_DDRITFCR,
1562 RCC_DDRITFCR_DDRCKMOD_MASK,
1563 RCC_DDRITFCR_DDRCKMOD_SSR <<
1564 RCC_DDRITFCR_DDRCKMOD_SHIFT);
1565
1566 return 0;
1567}
1568
1569static void stm32mp1_osc_clk_init(const char *name,
1570 struct stm32mp1_clk_priv *priv,
1571 enum stm32mp_osc_id index)
1572{
1573 uint32_t frequency;
1574
1575 priv->osc[index] = 0;
1576
1577 if (fdt_osc_read_freq(name, &frequency) != 0) {
1578 ERROR("%s frequency request failed\n", name);
1579 panic();
1580 } else {
1581 priv->osc[index] = frequency;
1582 }
1583}
1584
1585static void stm32mp1_osc_init(void)
1586{
1587 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data;
1588 enum stm32mp_osc_id i;
1589
1590 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) {
1591 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], priv, i);
1592 }
1593}
1594
1595int stm32mp1_clk_probe(void)
1596{
1597 struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data;
1598
1599 priv->base = fdt_rcc_read_addr();
1600 if (priv->base == 0U) {
1601 return -EINVAL;
1602 }
1603
1604 priv->data = &stm32mp1_data;
1605
1606 if ((priv->data->gate == NULL) || (priv->data->sel == NULL) ||
1607 (priv->data->pll == NULL)) {
1608 return -EINVAL;
1609 }
1610
1611 stm32mp1_osc_init();
1612
1613 return 0;
1614}