| commit | 40c28e8b03ca0ef3a2069e1a47005c100c2f2146 | [log] [tgz] |
|---|---|---|
| author | Etienne Carriere <etienne.carriere@st.com> | Thu Dec 19 10:03:23 2019 +0100 |
| committer | Yann Gautier <yann.gautier@st.com> | Wed Oct 06 10:53:33 2021 +0200 |
| tree | 20b562c0f3c49bf439e3cee9aa838c899cd8d581 | |
| parent | eaab37dfb031896bca7a840f887d1ba79aab707a [diff] |
fix(stm32mp1_clk): fix MCU/AXI parent clock Correct MCU clock parent selector: MCU subsystem clock is derived from clock PLL3_P, not PLL3. Correct AXI clock parent selector: AXI subsystem clock is derived from clock PLL2_P, not PLL2. This change also renames MCU clock and AXI clock resources to prevent confusion. Change-Id: If55618d180e7dce8e4f0977b0e586a6fa8ef28d1 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>