tree 20b562c0f3c49bf439e3cee9aa838c899cd8d581
parent eaab37dfb031896bca7a840f887d1ba79aab707a
author Etienne Carriere <etienne.carriere@st.com> 1576746203 +0100
committer Yann Gautier <yann.gautier@st.com> 1633510413 +0200

fix(stm32mp1_clk): fix MCU/AXI parent clock

Correct MCU clock parent selector: MCU subsystem clock is derived
from clock  PLL3_P, not PLL3.

Correct AXI clock parent selector: AXI subsystem clock is derived
from clock  PLL2_P, not PLL2.

This change also renames MCU clock and AXI clock resources to
prevent confusion.

Change-Id: If55618d180e7dce8e4f0977b0e586a6fa8ef28d1
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>