Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 1 | /* |
Louis Mayencourt | 8a06127 | 2019-04-05 16:25:25 +0100 | [diff] [blame] | 2 | * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <common/bl_common.h> |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 10 | #include <cortex_a35.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* --------------------------------------------- |
| 15 | * Disable L1 data cache and unified L2 cache |
| 16 | * --------------------------------------------- |
| 17 | */ |
| 18 | func cortex_a35_disable_dcache |
| 19 | mrs x1, sctlr_el3 |
| 20 | bic x1, x1, #SCTLR_C_BIT |
| 21 | msr sctlr_el3, x1 |
| 22 | isb |
| 23 | ret |
| 24 | endfunc cortex_a35_disable_dcache |
| 25 | |
| 26 | /* --------------------------------------------- |
| 27 | * Disable intra-cluster coherency |
| 28 | * --------------------------------------------- |
| 29 | */ |
| 30 | func cortex_a35_disable_smp |
| 31 | mrs x0, CORTEX_A35_CPUECTLR_EL1 |
| 32 | bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT |
| 33 | msr CORTEX_A35_CPUECTLR_EL1, x0 |
| 34 | isb |
| 35 | dsb sy |
| 36 | ret |
| 37 | endfunc cortex_a35_disable_smp |
| 38 | |
Louis Mayencourt | 8a06127 | 2019-04-05 16:25:25 +0100 | [diff] [blame] | 39 | /* --------------------------------------------------- |
| 40 | * Errata Workaround for Cortex A35 Errata #855472. |
| 41 | * This applies to revisions r0p0 of Cortex A35. |
| 42 | * Inputs: |
| 43 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 44 | * Shall clobber: x0-x17 |
| 45 | * --------------------------------------------------- |
| 46 | */ |
| 47 | func errata_a35_855472_wa |
| 48 | /* |
| 49 | * Compare x0 against revision r0p0 |
| 50 | */ |
| 51 | mov x17, x30 |
| 52 | bl check_errata_855472 |
| 53 | cbz x0, 1f |
| 54 | mrs x1, CORTEX_A35_CPUACTLR_EL1 |
| 55 | orr x1, x1, #CORTEX_A35_CPUACTLR_EL1_ENDCCASCI |
| 56 | msr CORTEX_A35_CPUACTLR_EL1, x1 |
| 57 | isb |
| 58 | 1: |
| 59 | ret x17 |
| 60 | endfunc errata_a35_855472_wa |
| 61 | |
| 62 | func check_errata_855472 |
| 63 | mov x1, #0x00 |
| 64 | b cpu_rev_var_ls |
| 65 | endfunc check_errata_855472 |
| 66 | |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 67 | /* ------------------------------------------------- |
| 68 | * The CPU Ops reset function for Cortex-A35. |
| 69 | * Clobbers: x0 |
| 70 | * ------------------------------------------------- |
| 71 | */ |
| 72 | func cortex_a35_reset_func |
Louis Mayencourt | 8a06127 | 2019-04-05 16:25:25 +0100 | [diff] [blame] | 73 | mov x19, x30 |
| 74 | bl cpu_get_rev_var |
| 75 | |
| 76 | #if ERRATA_A35_855472 |
| 77 | bl errata_a35_855472_wa |
| 78 | #endif |
| 79 | |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 80 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 81 | * Enable the SMP bit. |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 82 | * --------------------------------------------- |
| 83 | */ |
| 84 | mrs x0, CORTEX_A35_CPUECTLR_EL1 |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 85 | orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT |
| 86 | msr CORTEX_A35_CPUECTLR_EL1, x0 |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 87 | isb |
Louis Mayencourt | 8a06127 | 2019-04-05 16:25:25 +0100 | [diff] [blame] | 88 | ret x19 |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 89 | endfunc cortex_a35_reset_func |
| 90 | |
| 91 | func cortex_a35_core_pwr_dwn |
| 92 | mov x18, x30 |
| 93 | |
| 94 | /* --------------------------------------------- |
| 95 | * Turn off caches. |
| 96 | * --------------------------------------------- |
| 97 | */ |
| 98 | bl cortex_a35_disable_dcache |
| 99 | |
| 100 | /* --------------------------------------------- |
| 101 | * Flush L1 caches. |
| 102 | * --------------------------------------------- |
| 103 | */ |
| 104 | mov x0, #DCCISW |
| 105 | bl dcsw_op_level1 |
| 106 | |
| 107 | /* --------------------------------------------- |
| 108 | * Come out of intra cluster coherency |
| 109 | * --------------------------------------------- |
| 110 | */ |
| 111 | mov x30, x18 |
| 112 | b cortex_a35_disable_smp |
| 113 | endfunc cortex_a35_core_pwr_dwn |
| 114 | |
| 115 | func cortex_a35_cluster_pwr_dwn |
| 116 | mov x18, x30 |
| 117 | |
| 118 | /* --------------------------------------------- |
| 119 | * Turn off caches. |
| 120 | * --------------------------------------------- |
| 121 | */ |
| 122 | bl cortex_a35_disable_dcache |
| 123 | |
| 124 | /* --------------------------------------------- |
| 125 | * Flush L1 caches. |
| 126 | * --------------------------------------------- |
| 127 | */ |
| 128 | mov x0, #DCCISW |
| 129 | bl dcsw_op_level1 |
| 130 | |
| 131 | /* --------------------------------------------- |
| 132 | * Disable the optional ACP. |
| 133 | * --------------------------------------------- |
| 134 | */ |
| 135 | bl plat_disable_acp |
| 136 | |
| 137 | /* --------------------------------------------- |
| 138 | * Flush L2 caches. |
| 139 | * --------------------------------------------- |
| 140 | */ |
| 141 | mov x0, #DCCISW |
| 142 | bl dcsw_op_level2 |
| 143 | |
| 144 | /* --------------------------------------------- |
| 145 | * Come out of intra cluster coherency |
| 146 | * --------------------------------------------- |
| 147 | */ |
| 148 | mov x30, x18 |
| 149 | b cortex_a35_disable_smp |
| 150 | endfunc cortex_a35_cluster_pwr_dwn |
| 151 | |
Soby Mathew | 0980dce | 2018-09-17 04:34:35 +0100 | [diff] [blame] | 152 | #if REPORT_ERRATA |
| 153 | /* |
| 154 | * Errata printing function for Cortex A35. Must follow AAPCS. |
| 155 | */ |
| 156 | func cortex_a35_errata_report |
Louis Mayencourt | 8a06127 | 2019-04-05 16:25:25 +0100 | [diff] [blame] | 157 | stp x8, x30, [sp, #-16]! |
| 158 | |
| 159 | bl cpu_get_rev_var |
| 160 | mov x8, x0 |
| 161 | |
| 162 | /* |
| 163 | * Report all errata. The revision-variant information is passed to |
| 164 | * checking functions of each errata. |
| 165 | */ |
| 166 | report_errata ERRATA_A35_855472, cortex_a35, 855472 |
| 167 | |
| 168 | ldp x8, x30, [sp], #16 |
Soby Mathew | 0980dce | 2018-09-17 04:34:35 +0100 | [diff] [blame] | 169 | ret |
| 170 | endfunc cortex_a35_errata_report |
| 171 | #endif |
| 172 | |
| 173 | |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 174 | /* --------------------------------------------- |
| 175 | * This function provides cortex_a35 specific |
| 176 | * register information for crash reporting. |
| 177 | * It needs to return with x6 pointing to |
| 178 | * a list of register names in ascii and |
| 179 | * x8 - x15 having values of registers to be |
| 180 | * reported. |
| 181 | * --------------------------------------------- |
| 182 | */ |
| 183 | .section .rodata.cortex_a35_regs, "aS" |
| 184 | cortex_a35_regs: /* The ascii list of register names to be reported */ |
| 185 | .asciz "cpuectlr_el1", "" |
| 186 | |
| 187 | func cortex_a35_cpu_reg_dump |
| 188 | adr x6, cortex_a35_regs |
| 189 | mrs x8, CORTEX_A35_CPUECTLR_EL1 |
| 190 | ret |
| 191 | endfunc cortex_a35_cpu_reg_dump |
| 192 | |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 193 | declare_cpu_ops cortex_a35, CORTEX_A35_MIDR, \ |
| 194 | cortex_a35_reset_func, \ |
| 195 | cortex_a35_core_pwr_dwn, \ |
| 196 | cortex_a35_cluster_pwr_dwn |