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Yann Gautier9d135e42018-07-16 19:36:06 +02001/*
Yann Gautier2bbf1712019-08-06 17:28:23 +02002 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
Yann Gautier9d135e42018-07-16 19:36:06 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Yann Gautier9d135e42018-07-16 19:36:06 +02007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <arch_helpers.h>
Yann Gautier2bbf1712019-08-06 17:28:23 +020011#include <bl32/sp_min/platform_sp_min.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <common/bl_common.h>
13#include <common/debug.h>
Yann Gautier9d135e42018-07-16 19:36:06 +020014#include <context.h>
Yann Gautierf9d40d52019-01-17 14:41:46 +010015#include <drivers/arm/gicv2.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <drivers/arm/tzc400.h>
17#include <drivers/generic_delay_timer.h>
Yann Gautier52448ab2019-01-17 14:53:24 +010018#include <drivers/st/bsec.h>
Etienne Carrieree96162e2020-04-10 11:32:54 +020019#include <drivers/st/etzpc.h>
Yann Gautier14d769c2019-01-18 11:13:15 +010020#include <drivers/st/stm32_gpio.h>
Yann Gautier091eab52019-06-04 18:06:34 +020021#include <drivers/st/stm32_iwdg.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <drivers/st/stm32mp1_clk.h>
Yann Gautier9d135e42018-07-16 19:36:06 +020023#include <dt-bindings/clock/stm32mp1-clks.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024#include <lib/el3_runtime/context_mgmt.h>
25#include <lib/mmio.h>
26#include <lib/xlat_tables/xlat_tables_v2.h>
27#include <plat/common/platform.h>
28
Yann Gautier2bbf1712019-08-06 17:28:23 +020029#include <platform_def.h>
Yann Gautier9d135e42018-07-16 19:36:06 +020030
31/******************************************************************************
32 * Placeholder variables for copying the arguments that have been passed to
33 * BL32 from BL2.
34 ******************************************************************************/
35static entry_point_info_t bl33_image_ep_info;
36
37/*******************************************************************************
38 * Interrupt handler for FIQ (secure IRQ)
39 ******************************************************************************/
40void sp_min_plat_fiq_handler(uint32_t id)
41{
Yann Gautierb55a6242022-03-07 16:09:23 +010042 (void)plat_crash_console_init();
43
Yann Gautierf9d40d52019-01-17 14:41:46 +010044 switch (id & INT_ID_MASK) {
Yann Gautier9d135e42018-07-16 19:36:06 +020045 case STM32MP1_IRQ_TZC400:
Yann Gautier658775c2021-07-06 10:00:44 +020046 tzc400_init(STM32MP1_TZC_BASE);
Yann Gautierd7820562019-04-25 13:29:12 +020047 (void)tzc400_it_handler();
Yann Gautier9d135e42018-07-16 19:36:06 +020048 panic();
49 break;
50 case STM32MP1_IRQ_AXIERRIRQ:
51 ERROR("STM32MP1_IRQ_AXIERRIRQ generated\n");
52 panic();
53 break;
54 default:
Yann Gautierb55a6242022-03-07 16:09:23 +010055 ERROR("SECURE IT handler not define for it : %u\n", id);
Yann Gautier9d135e42018-07-16 19:36:06 +020056 break;
57 }
58}
59
60/*******************************************************************************
61 * Return a pointer to the 'entry_point_info' structure of the next image for
62 * the security state specified. BL33 corresponds to the non-secure image type
63 * while BL32 corresponds to the secure image type. A NULL pointer is returned
64 * if the image does not exist.
65 ******************************************************************************/
66entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
67{
68 entry_point_info_t *next_image_info;
69
70 next_image_info = &bl33_image_ep_info;
71
72 if (next_image_info->pc == 0U) {
73 return NULL;
74 }
75
76 return next_image_info;
77}
78
Etienne Carriere72369b12019-12-08 08:17:56 +010079CASSERT((STM32MP_SEC_SYSRAM_BASE == STM32MP_SYSRAM_BASE) &&
80 ((STM32MP_SEC_SYSRAM_BASE + STM32MP_SEC_SYSRAM_SIZE) <=
81 (STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE)),
82 assert_secure_sysram_fits_at_begining_of_sysram);
83
84#ifdef STM32MP_NS_SYSRAM_BASE
85CASSERT((STM32MP_NS_SYSRAM_BASE >= STM32MP_SEC_SYSRAM_BASE) &&
86 ((STM32MP_NS_SYSRAM_BASE + STM32MP_NS_SYSRAM_SIZE) ==
87 (STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE)),
88 assert_non_secure_sysram_fits_at_end_of_sysram);
89
90CASSERT((STM32MP_NS_SYSRAM_BASE & (PAGE_SIZE_4KB - U(1))) == 0U,
91 assert_non_secure_sysram_base_is_4kbyte_aligned);
92
93#define TZMA1_SECURE_RANGE \
94 (((STM32MP_NS_SYSRAM_BASE - STM32MP_SYSRAM_BASE) >> FOUR_KB_SHIFT) - 1U)
95#else
Etienne Carrieree96162e2020-04-10 11:32:54 +020096#define TZMA1_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE
Etienne Carriere72369b12019-12-08 08:17:56 +010097#endif /* STM32MP_NS_SYSRAM_BASE */
Etienne Carrieree96162e2020-04-10 11:32:54 +020098#define TZMA0_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE
99
100static void stm32mp1_etzpc_early_setup(void)
101{
Etienne Carrieree96162e2020-04-10 11:32:54 +0200102 if (etzpc_init() != 0) {
103 panic();
104 }
105
106 etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_ROM, TZMA0_SECURE_RANGE);
107 etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_SYSRAM, TZMA1_SECURE_RANGE);
Etienne Carrieree96162e2020-04-10 11:32:54 +0200108}
109
Yann Gautier9d135e42018-07-16 19:36:06 +0200110/*******************************************************************************
111 * Perform any BL32 specific platform actions.
112 ******************************************************************************/
113void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
114 u_register_t arg2, u_register_t arg3)
115{
Yann Gautier9d135e42018-07-16 19:36:06 +0200116 bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
Yann Gautier658775c2021-07-06 10:00:44 +0200117 uintptr_t dt_addr = arg1;
Yann Gautier9d135e42018-07-16 19:36:06 +0200118
Yann Gautier65662112021-10-15 16:49:07 +0200119 stm32mp_setup_early_console();
120
Yann Gautier9d135e42018-07-16 19:36:06 +0200121 /* Imprecise aborts can be masked in NonSecure */
122 write_scr(read_scr() | SCR_AW_BIT);
123
Yann Gautier7ffe84b2019-07-11 10:45:09 +0200124 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
125 BL_CODE_END - BL_CODE_BASE,
126 MT_CODE | MT_SECURE);
127
128 configure_mmu();
129
Yann Gautier9d135e42018-07-16 19:36:06 +0200130 assert(params_from_bl2 != NULL);
131 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
132 assert(params_from_bl2->h.version >= VERSION_2);
133
134 bl_params_node_t *bl_params = params_from_bl2->head;
135
136 /*
137 * Copy BL33 entry point information.
138 * They are stored in Secure RAM, in BL2's address space.
139 */
140 while (bl_params != NULL) {
141 if (bl_params->image_id == BL33_IMAGE_ID) {
142 bl33_image_ep_info = *bl_params->ep_info;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200143 /*
144 * Check if hw_configuration is given to BL32 and
145 * share it to BL33.
146 */
147 if (arg2 != 0U) {
148 bl33_image_ep_info.args.arg0 = 0U;
149 bl33_image_ep_info.args.arg1 = 0U;
150 bl33_image_ep_info.args.arg2 = arg2;
151 }
152
Yann Gautier9d135e42018-07-16 19:36:06 +0200153 break;
154 }
155
156 bl_params = bl_params->next_params_info;
157 }
158
Yann Gautier658775c2021-07-06 10:00:44 +0200159 if (dt_open_and_check(dt_addr) < 0) {
Yann Gautier9d135e42018-07-16 19:36:06 +0200160 panic();
161 }
162
Yann Gautier52448ab2019-01-17 14:53:24 +0100163 if (bsec_probe() != 0) {
164 panic();
165 }
166
Yann Gautier9d135e42018-07-16 19:36:06 +0200167 if (stm32mp1_clk_probe() < 0) {
168 panic();
169 }
170
Yann Gautier414f17c2021-10-18 15:50:05 +0200171 (void)stm32mp_uart_console_setup();
Etienne Carrieree96162e2020-04-10 11:32:54 +0200172
173 stm32mp1_etzpc_early_setup();
Yann Gautier9d135e42018-07-16 19:36:06 +0200174}
175
176/*******************************************************************************
177 * Initialize the MMU, security and the GIC.
178 ******************************************************************************/
179void sp_min_platform_setup(void)
180{
Yann Gautier9d135e42018-07-16 19:36:06 +0200181 generic_delay_timer_init();
182
Yann Gautier2bbf1712019-08-06 17:28:23 +0200183 stm32mp_gic_init();
Yann Gautier14d769c2019-01-18 11:13:15 +0100184
Yann Gautier091eab52019-06-04 18:06:34 +0200185 if (stm32_iwdg_init() < 0) {
186 panic();
187 }
Etienne Carriere7a4a34f2020-05-13 10:07:45 +0200188
189 stm32mp_lock_periph_registering();
Etienne Carriere34f0e932020-07-16 17:36:18 +0200190
191 stm32mp1_init_scmi_server();
Yann Gautier9d135e42018-07-16 19:36:06 +0200192}
193
194void sp_min_plat_arch_setup(void)
195{
196}