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Jeenu Viswambharan615ff392016-10-24 14:31:51 +01001#
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05002# Copyright (c) 2016-2021, ARM Limited. All rights reserved.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01005#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010013# Use T32 by default
14AARCH32_INSTRUCTION_SET := T32
15
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010016# The AArch32 Secure Payload to be built as BL32 image
17AARCH32_SP := none
18
19# The Target build architecture. Supported values are: aarch64, aarch32.
20ARCH := aarch64
21
Alexei Fedorov132e6652020-12-07 16:38:53 +000022# ARM Architecture feature modifiers: none by default
23ARM_ARCH_FEATURE := none
24
Jeenu Viswambharanfca76802017-01-16 16:52:35 +000025# ARM Architecture major and minor versions: 8.0 by default.
26ARM_ARCH_MAJOR := 8
27ARM_ARCH_MINOR := 0
28
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010029# Base commit to perform code check on
30BASE_COMMIT := origin/master
31
Roberto Vargase0e99462017-10-30 14:43:43 +000032# Execute BL2 at EL3
33BL2_AT_EL3 := 0
34
Jiafei Pan43a7bf42018-03-21 07:20:09 +000035# BL2 image is stored in XIP memory, for now, this option is only supported
36# when BL2_AT_EL3 is 1.
37BL2_IN_XIP_MEM := 0
38
Hadi Asyrafi461f8f42019-08-20 15:33:27 +080039# Do dcache invalidate upon BL2 entry at EL3
40BL2_INV_DCACHE := 1
41
Alexei Fedorov90f2e882019-05-24 12:17:09 +010042# Select the branch protection features to use.
43BRANCH_PROTECTION := 0
44
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010045# By default, consider that the platform may release several CPUs out of reset.
46# The platform Makefile is free to override this value.
47COLD_BOOT_SINGLE_CPU := 0
48
Julius Wernerb624ae02017-06-09 15:17:15 -070049# Flag to compile in coreboot support code. Exclude by default. The coreboot
50# Makefile system will set this when compiling TF as part of a coreboot image.
51COREBOOT := 0
52
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010053# For Chain of Trust
54CREATE_KEYS := 1
55
56# Build flag to include AArch32 registers in cpu context save and restore during
57# world switch. This flag must be set to 0 for AArch64-only platforms.
58CTX_INCLUDE_AARCH32_REGS := 1
59
60# Include FP registers in cpu context
61CTX_INCLUDE_FPREGS := 0
62
Antonio Nino Diaz594811b2019-01-31 11:58:00 +000063# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
64# must be set to 1 if the platform wants to use this feature in the Secure
65# world. It is not needed to use it in the Non-secure world.
66CTX_INCLUDE_PAUTH_REGS := 0
67
Arunachalam Ganapathydd3ec7e2020-05-28 11:57:09 +010068# Include Nested virtualization control (Armv8.4-NV) registers in cpu context.
69# This must be set to 1 if architecture implements Nested Virtualization
70# Extension and platform wants to use this feature in the Secure world
71CTX_INCLUDE_NEVE_REGS := 0
72
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010073# Debug build
74DEBUG := 0
75
Sumit Garg392e4df2019-11-15 10:43:00 +053076# By default disable authenticated decryption support.
77DECRYPTION_SUPPORT := none
78
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010079# Build platform
80DEFAULT_PLAT := fvp
81
Christoph Müllner4f088e42019-04-24 09:45:30 +020082# Disable the generation of the binary image (ELF only).
83DISABLE_BIN_GENERATION := 0
84
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +000085# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards
86# compatibility.
87DISABLE_MTPMU := 0
88
Soby Mathew9fe88042018-03-26 12:43:37 +010089# Enable capability to disable authentication dynamically. Only meant for
90# development platforms.
91DYN_DISABLE_AUTH := 0
92
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +010093# Build option to enable MPAM for lower ELs
94ENABLE_MPAM_FOR_LOWER_ELS := 0
95
Soby Mathew078f1a42018-08-28 11:13:55 +010096# Flag to Enable Position Independant support (PIE)
97ENABLE_PIE := 0
98
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010099# Flag to enable Performance Measurement Framework
100ENABLE_PMF := 0
101
102# Flag to enable PSCI STATs functionality
103ENABLE_PSCI_STAT := 0
104
105# Flag to enable runtime instrumentation using PMF
106ENABLE_RUNTIME_INSTRUMENTATION := 0
107
Douglas Raillard306593d2017-02-24 18:14:15 +0000108# Flag to enable stack corruption protection
109ENABLE_STACK_PROTECTOR := 0
110
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100111# Flag to enable exception handling in EL3
112EL3_EXCEPTION_HANDLING := 0
113
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100114# Flag to enable Branch Target Identification.
115# Internal flag not meant for direct setting.
116# Use BRANCH_PROTECTION to enable BTI.
117ENABLE_BTI := 0
118
119# Flag to enable Pointer Authentication.
120# Internal flag not meant for direct setting.
121# Use BRANCH_PROTECTION to enable PAUTH.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000122ENABLE_PAUTH := 0
123
Sumit Gargeec52442019-11-14 16:33:45 +0530124# By default BL31 encryption disabled
125ENCRYPT_BL31 := 0
126
127# By default BL32 encryption disabled
128ENCRYPT_BL32 := 0
129
130# Default dummy firmware encryption key
131ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef
132
133# Default dummy nonce for firmware encryption
134ENC_NONCE := 1234567890abcdef12345678
135
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100136# Build flag to treat usage of deprecated platform and framework APIs as error.
137ERROR_DEPRECATED := 0
138
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000139# Fault injection support
140FAULT_INJECTION_SUPPORT := 0
141
Masahiro Yamada4d87eb42016-12-25 13:52:22 +0900142# Byte alignment that each component in FIP is aligned to
143FIP_ALIGN := 0
144
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100145# Default FIP file name
146FIP_NAME := fip.bin
147
148# Default FWU_FIP file name
149FWU_FIP_NAME := fwu_fip.bin
150
Sumit Gargeec52442019-11-14 16:33:45 +0530151# By default firmware encryption with SSK
152FW_ENC_STATUS := 0
153
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100154# For Chain of Trust
155GENERATE_COT := 0
156
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100157# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
158# default, they are for Secure EL1.
159GICV2_G0_FOR_EL3 := 0
160
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000161# Route External Aborts to EL3. Disabled by default; External Aborts are handled
162# by lower ELs.
163HANDLE_EA_EL3_FIRST := 0
164
Alexei Fedorovf11aeb72020-10-06 15:54:12 +0100165# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512.
166# The default value is sha256.
167HASH_ALG := sha256
168
Jeenu Viswambharana10d64e2017-01-04 13:51:42 +0000169# Whether system coherency is managed in hardware, without explicit software
170# operations.
171HW_ASSISTED_COHERENCY := 0
172
Soby Mathew13b16052017-08-31 11:49:32 +0100173# Set the default algorithm for the generation of Trusted Board Boot keys
174KEY_ALG := rsa
175
Leonardo Sandoval849f7af2020-06-18 17:32:55 -0500176# Set the default key size in case KEY_ALG is rsa
177ifeq ($(KEY_ALG),rsa)
178KEY_SIZE := 2048
179endif
180
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000181# Option to build TF with Measured Boot support
182MEASURED_BOOT := 0
183
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100184# NS timer register save and restore
185NS_TIMER_SWITCH := 0
186
Varun Wadekar3f9002c2019-01-31 09:22:30 -0800187# Include lib/libc in the final image
188OVERRIDE_LIBC := 0
189
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100190# Build PL011 UART driver in minimal generic UART mode
191PL011_GENERIC_UART := 0
192
193# By default, consider that the platform's reset address is not programmable.
194# The platform Makefile is free to override this value.
195PROGRAMMABLE_RESET_ADDRESS := 0
196
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000197# Flag used to choose the power state format: Extended State-ID or Original
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100198PSCI_EXTENDED_STATE_ID := 0
199
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100200# Enable RAS support
201RAS_EXTENSION := 0
202
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100203# By default, BL1 acts as the reset handler, not BL31
204RESET_TO_BL31 := 0
205
206# For Chain of Trust
207SAVE_KEYS := 0
208
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100209# Software Delegated Exception support
210SDEI_SUPPORT := 0
211
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -0500212# True Random Number firmware Interface
213TRNG_SUPPORT := 0
214
Jeremy Linton90cbf522020-11-18 10:12:41 -0600215# SMCCC PCI support
216SMC_PCI_SUPPORT := 0
217
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100218# Whether code and read-only data should be put on separate memory pages. The
219# platform Makefile is free to override this value.
220SEPARATE_CODE_AND_RODATA := 0
221
Samuel Holland31a14e12018-10-17 21:40:18 -0500222# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a
223# separate memory region, which may be discontiguous from the rest of BL31.
224SEPARATE_NOBITS_REGION := 0
225
Daniel Boulby468f0d72018-09-18 11:45:51 +0100226# If the BL31 image initialisation code is recalimed after use for the secondary
227# cores stack
228RECLAIM_INIT_CODE := 0
229
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100230# SPD choice
231SPD := none
232
Paul Beesleyfe975b42019-09-16 11:29:03 +0000233# Enable the Management Mode (MM)-based Secure Partition Manager implementation
234SPM_MM := 0
Antonio Nino Diaz8cd7ea32018-10-30 11:08:08 +0000235
Max Shvetsove7fd80e2020-02-25 13:55:00 +0000236# Use SPM at S-EL2 as a default config for SPMD
237SPMD_SPM_AT_SEL2 := 1
238
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100239# Flag to introduce an infinite loop in BL1 just before it exits into the next
240# image. This is meant to help debugging the post-BL2 phase.
241SPIN_ON_BL1_EXIT := 0
242
243# Flags to build TF with Trusted Boot support
244TRUSTED_BOARD_BOOT := 0
245
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100246# Build option to choose whether Trusted Firmware uses Coherent memory or not.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100247USE_COHERENT_MEM := 1
248
Olivier Deprezcb4c5622019-09-19 17:46:46 +0200249# Build option to add debugfs support
250USE_DEBUGFS := 0
251
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100252# Build option to fconf based io
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100253ARM_IO_IN_DTB := 0
254
255# Build option to support SDEI through fconf
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500256SDEI_IN_FCONF := 0
257
258# Build option to support Secure Interrupt descriptors through fconf
259SEC_INT_DESC_IN_FCONF := 0
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100260
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100261# Build option to choose whether Trusted Firmware uses library at ROM
262USE_ROMLIB := 0
Roberto Vargase92111a2018-05-22 16:05:42 +0100263
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000264# Build option to choose whether the xlat tables of BL images can be read-only.
265# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES,
266# which is the per BL-image option that actually enables the read-only tables
267# API. The reason for having this additional option is to have a common high
268# level makefile where we can check for incompatible features/build options.
269ALLOW_RO_XLAT_TABLES := 0
270
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100271# Chain of trust.
272COT := tbbr
273
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900274# Use tbbr_oid.h instead of platform_oid.h
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100275USE_TBBR_DEFS := 1
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900276
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100277# Build verbosity
278V := 0
Soby Mathew043fe9c2017-04-10 22:35:42 +0100279
280# Whether to enable D-Cache early during warm boot. This is usually
281# applicable for platforms wherein interconnect programming is not
282# required to enable cache coherency after warm reset (eg: single cluster
283# platforms).
284WARMBOOT_ENABLE_DCACHE_EARLY := 0
dp-armee3457b2017-05-23 09:32:49 +0100285
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100286# Build option to enable/disable the Statistical Profiling Extensions
dp-armee3457b2017-05-23 09:32:49 +0100287ENABLE_SPE_FOR_LOWER_ELS := 1
288
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100289# SPE is only supported on AArch64 so disable it on AArch32.
dp-armee3457b2017-05-23 09:32:49 +0100290ifeq (${ARCH},aarch32)
291 override ENABLE_SPE_FOR_LOWER_ELS := 0
dp-armee3457b2017-05-23 09:32:49 +0100292endif
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100293
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100294# Include Memory Tagging Extension registers in cpu context. This must be set
295# to 1 if the platform wants to use this feature in the Secure world and MTE is
296# enabled at ELX.
johpow01fa59c6f2020-10-02 13:41:11 -0500297CTX_INCLUDE_MTE_REGS := 0
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100298
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100299ENABLE_AMU := 0
johpow01fa59c6f2020-10-02 13:41:11 -0500300AMU_RESTRICT_COUNTERS := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100301
Max Shvetsovc4502772021-03-22 11:59:37 +0000302# By default, enable Scalable Vector Extension if implemented only for Non-secure
David Cunadoce88eee2017-10-20 11:30:57 +0100303# lower ELs
304# Note SVE is only supported on AArch64 - therefore do not enable in AArch32
305ifneq (${ARCH},aarch32)
306 ENABLE_SVE_FOR_NS := 1
Max Shvetsovc4502772021-03-22 11:59:37 +0000307 ENABLE_SVE_FOR_SWD := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100308else
309 override ENABLE_SVE_FOR_NS := 0
Max Shvetsovc4502772021-03-22 11:59:37 +0000310 override ENABLE_SVE_FOR_SWD := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100311endif
Justin Chadwell83e04882019-08-20 11:01:52 +0100312
313SANITIZE_UB := off
Soby Mathewad042012019-09-25 14:03:41 +0100314
315# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock
316# implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
317# Default: disabled
318USE_SPINLOCK_CAS := 0
zelalem-aweked5f45272019-11-12 16:20:17 -0600319
320# Enable Link Time Optimization
321ENABLE_LTO := 0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000322
323# Build flag to include EL2 registers in cpu context save and restore during
324# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option.
325# Default is 0.
326CTX_INCLUDE_EL2_REGS := 0
Manish V Badarkhe75c972a2020-03-22 05:06:38 +0000327
328# Enable Memory tag extension which is supported for architecture greater
329# than Armv8.5-A
330# By default it is set to "no"
331SUPPORT_STACK_MEMTAG := no
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100332
333# Select workaround for AT speculative behaviour.
334ERRATA_SPECULATIVE_AT := 0
Varun Wadekar92234852020-06-12 10:11:28 -0700335
336# Trap RAS error record access from lower EL
337RAS_TRAP_LOWER_EL_ERR_ACCESS := 0
Manish V Badarkhead339892020-06-29 10:32:53 +0100338
339# Build option to create cot descriptors using fconf
340COT_DESC_IN_DTB := 0
Manish V Badarkhe3589b702020-07-29 10:58:44 +0100341
342# Build option to provide openssl directory path
343OPENSSL_DIR := /usr
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500344
345# Build option to use the SP804 timer instead of the generic one
346USE_SP804_TIMER := 0