Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | 84a775e | 2019-01-03 10:12:55 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 7cf57d7 | 2018-05-17 09:36:38 -0700 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 8 | #include <arch_helpers.h> |
kalyanic | 0a2cc61 | 2019-09-13 14:49:39 -0700 | [diff] [blame] | 9 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <common/bl_common.h> |
Varun Wadekar | 9d15f7e | 2019-08-21 14:01:31 -0700 | [diff] [blame] | 11 | #include <drivers/console.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | #include <lib/xlat_tables/xlat_tables_v2.h> |
Varun Wadekar | a125180 | 2019-08-22 11:52:36 -0700 | [diff] [blame] | 13 | #include <memctrl.h> |
Ambroise Vincent | ffbf32a | 2019-03-28 09:01:18 +0000 | [diff] [blame] | 14 | #include <plat/common/platform.h> |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 15 | #include <tegra_def.h> |
Varun Wadekar | 9d15f7e | 2019-08-21 14:01:31 -0700 | [diff] [blame] | 16 | #include <tegra_platform.h> |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 17 | #include <tegra_private.h> |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 18 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 19 | /* sets of MMIO ranges setup */ |
| 20 | #define MMIO_RANGE_0_ADDR 0x50000000 |
| 21 | #define MMIO_RANGE_1_ADDR 0x60000000 |
| 22 | #define MMIO_RANGE_2_ADDR 0x70000000 |
| 23 | #define MMIO_RANGE_SIZE 0x200000 |
| 24 | |
| 25 | /* |
| 26 | * Table of regions to map using the MMU. |
| 27 | */ |
| 28 | static const mmap_region_t tegra_mmap[] = { |
| 29 | MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, |
| 30 | MT_DEVICE | MT_RW | MT_SECURE), |
| 31 | MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, |
| 32 | MT_DEVICE | MT_RW | MT_SECURE), |
| 33 | MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, |
| 34 | MT_DEVICE | MT_RW | MT_SECURE), |
| 35 | {0} |
| 36 | }; |
| 37 | |
| 38 | /******************************************************************************* |
| 39 | * Set up the pagetables as per the platform memory map & initialize the MMU |
| 40 | ******************************************************************************/ |
| 41 | const mmap_region_t *plat_get_mmio_map(void) |
| 42 | { |
| 43 | /* MMIO space */ |
| 44 | return tegra_mmap; |
| 45 | } |
| 46 | |
Varun Wadekar | e34bc3d | 2017-04-28 08:43:33 -0700 | [diff] [blame] | 47 | /******************************************************************************* |
| 48 | * The Tegra power domain tree has a single system level power domain i.e. a |
| 49 | * single root node. The first entry in the power domain descriptor specifies |
| 50 | * the number of power domains at the highest power level. |
| 51 | ******************************************************************************* |
| 52 | */ |
| 53 | const unsigned char tegra_power_domain_tree_desc[] = { |
| 54 | /* No of root nodes */ |
| 55 | 1, |
| 56 | /* No of clusters */ |
| 57 | PLATFORM_CLUSTER_COUNT, |
| 58 | /* No of CPU cores */ |
| 59 | PLATFORM_CORE_COUNT, |
| 60 | }; |
| 61 | |
| 62 | /******************************************************************************* |
| 63 | * This function returns the Tegra default topology tree information. |
| 64 | ******************************************************************************/ |
| 65 | const unsigned char *plat_get_power_domain_tree_desc(void) |
| 66 | { |
| 67 | return tegra_power_domain_tree_desc; |
| 68 | } |
| 69 | |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 70 | unsigned int plat_get_syscnt_freq2(void) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 71 | { |
| 72 | return 12000000; |
| 73 | } |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 74 | |
| 75 | /******************************************************************************* |
| 76 | * Maximum supported UART controllers |
| 77 | ******************************************************************************/ |
| 78 | #define TEGRA132_MAX_UART_PORTS 5 |
| 79 | |
| 80 | /******************************************************************************* |
| 81 | * This variable holds the UART port base addresses |
| 82 | ******************************************************************************/ |
| 83 | static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = { |
| 84 | 0, /* undefined - treated as an error case */ |
| 85 | TEGRA_UARTA_BASE, |
| 86 | TEGRA_UARTB_BASE, |
| 87 | TEGRA_UARTC_BASE, |
| 88 | TEGRA_UARTD_BASE, |
| 89 | TEGRA_UARTE_BASE, |
| 90 | }; |
| 91 | |
| 92 | /******************************************************************************* |
Varun Wadekar | 9d15f7e | 2019-08-21 14:01:31 -0700 | [diff] [blame] | 93 | * Enable console corresponding to the console ID |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 94 | ******************************************************************************/ |
Varun Wadekar | 9d15f7e | 2019-08-21 14:01:31 -0700 | [diff] [blame] | 95 | void plat_enable_console(int32_t id) |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 96 | { |
Andre Przywara | 98b5a11 | 2020-01-25 00:58:35 +0000 | [diff] [blame] | 97 | static console_t uart_console; |
Varun Wadekar | 9d15f7e | 2019-08-21 14:01:31 -0700 | [diff] [blame] | 98 | uint32_t console_clock; |
| 99 | |
| 100 | if ((id > 0) && (id < TEGRA132_MAX_UART_PORTS)) { |
| 101 | /* |
| 102 | * Reference clock used by the FPGAs is a lot slower. |
| 103 | */ |
| 104 | if (tegra_platform_is_fpga()) { |
| 105 | console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; |
| 106 | } else { |
| 107 | console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; |
| 108 | } |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 109 | |
Varun Wadekar | 9d15f7e | 2019-08-21 14:01:31 -0700 | [diff] [blame] | 110 | (void)console_16550_register(tegra132_uart_addresses[id], |
| 111 | console_clock, |
| 112 | TEGRA_CONSOLE_BAUDRATE, |
| 113 | &uart_console); |
Andre Przywara | 98b5a11 | 2020-01-25 00:58:35 +0000 | [diff] [blame] | 114 | console_set_scope(&uart_console, CONSOLE_FLAG_BOOT | |
Varun Wadekar | 9d15f7e | 2019-08-21 14:01:31 -0700 | [diff] [blame] | 115 | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); |
| 116 | } |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 117 | } |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 118 | |
| 119 | /******************************************************************************* |
| 120 | * Initialize the GIC and SGIs |
| 121 | ******************************************************************************/ |
| 122 | void plat_gic_setup(void) |
| 123 | { |
| 124 | tegra_gic_setup(NULL, 0); |
Varun Wadekar | 84a775e | 2019-01-03 10:12:55 -0800 | [diff] [blame] | 125 | tegra_gic_init(); |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 126 | } |
Varun Wadekar | 7cf57d7 | 2018-05-17 09:36:38 -0700 | [diff] [blame] | 127 | |
| 128 | /******************************************************************************* |
| 129 | * Return pointer to the BL31 params from previous bootloader |
| 130 | ******************************************************************************/ |
| 131 | struct tegra_bl31_params *plat_get_bl31_params(void) |
| 132 | { |
| 133 | return NULL; |
| 134 | } |
| 135 | |
| 136 | /******************************************************************************* |
| 137 | * Return pointer to the BL31 platform params from previous bootloader |
| 138 | ******************************************************************************/ |
| 139 | plat_params_from_bl2_t *plat_get_bl31_plat_params(void) |
| 140 | { |
| 141 | return NULL; |
| 142 | } |
| 143 | |
| 144 | /******************************************************************************* |
| 145 | * Handler for early platform setup |
| 146 | ******************************************************************************/ |
| 147 | void plat_early_platform_setup(void) |
| 148 | { |
Varun Wadekar | a125180 | 2019-08-22 11:52:36 -0700 | [diff] [blame] | 149 | plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); |
| 150 | |
kalyanic | 0a2cc61 | 2019-09-13 14:49:39 -0700 | [diff] [blame] | 151 | /* Verify chip id is t132 */ |
| 152 | assert(tegra_chipid_is_t132()); |
Varun Wadekar | a125180 | 2019-08-22 11:52:36 -0700 | [diff] [blame] | 153 | |
| 154 | /* |
| 155 | * Do initial security configuration to allow DRAM/device access. |
| 156 | */ |
| 157 | tegra_memctrl_tzdram_setup(plat_params->tzdram_base, |
| 158 | (uint32_t)plat_params->tzdram_size); |
Varun Wadekar | 7cf57d7 | 2018-05-17 09:36:38 -0700 | [diff] [blame] | 159 | } |
| 160 | |
| 161 | /******************************************************************************* |
| 162 | * Handler for late platform setup |
| 163 | ******************************************************************************/ |
| 164 | void plat_late_platform_setup(void) |
| 165 | { |
| 166 | ; /* do nothing */ |
| 167 | } |
Varun Wadekar | 8d7a02b | 2018-06-26 16:07:50 -0700 | [diff] [blame] | 168 | |
| 169 | /******************************************************************************* |
| 170 | * Handler to indicate support for System Suspend |
| 171 | ******************************************************************************/ |
| 172 | bool plat_supports_system_suspend(void) |
| 173 | { |
| 174 | return true; |
| 175 | } |
Kalyani Chidambaram Vaidyanathan | e755856 | 2020-06-15 16:48:53 -0700 | [diff] [blame^] | 176 | |
| 177 | /******************************************************************************* |
| 178 | * Platform specific runtime setup. |
| 179 | ******************************************************************************/ |
| 180 | void plat_runtime_setup(void) |
| 181 | { |
| 182 | /* |
| 183 | * During cold boot, it is observed that the arbitration |
| 184 | * bit is set in the Memory controller leading to false |
| 185 | * error interrupts in the non-secure world. To avoid |
| 186 | * this, clean the interrupt status register before |
| 187 | * booting into the non-secure world |
| 188 | */ |
| 189 | tegra_memctrl_clear_pending_interrupts(); |
| 190 | |
| 191 | /* |
| 192 | * During boot, USB3 and flash media (SDMMC/SATA) devices need |
| 193 | * access to IRAM. Because these clients connect to the MC and |
| 194 | * do not have a direct path to the IRAM, the MC implements AHB |
| 195 | * redirection during boot to allow path to IRAM. In this mode |
| 196 | * accesses to a programmed memory address aperture are directed |
| 197 | * to the AHB bus, allowing access to the IRAM. This mode must be |
| 198 | * disabled before we jump to the non-secure world. |
| 199 | */ |
| 200 | tegra_memctrl_disable_ahb_redirection(); |
| 201 | } |