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Varun Wadekar0f3baa02015-07-16 11:36:33 +05301/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <xlat_tables.h>
32#include <tegra_def.h>
33
Varun Wadekara78bb1b2015-08-07 10:03:00 +053034/*******************************************************************************
35 * The Tegra power domain tree has a single system level power domain i.e. a
36 * single root node. The first entry in the power domain descriptor specifies
37 * the number of power domains at the highest power level.
38 *******************************************************************************
39 */
40const unsigned char tegra_power_domain_tree_desc[] = {
41 /* No of root nodes */
42 1,
43 /* No of clusters */
44 PLATFORM_CLUSTER_COUNT,
45 /* No of CPU cores */
46 PLATFORM_CORE_COUNT,
47};
48
Varun Wadekar0f3baa02015-07-16 11:36:33 +053049/* sets of MMIO ranges setup */
50#define MMIO_RANGE_0_ADDR 0x50000000
51#define MMIO_RANGE_1_ADDR 0x60000000
52#define MMIO_RANGE_2_ADDR 0x70000000
53#define MMIO_RANGE_SIZE 0x200000
54
55/*
56 * Table of regions to map using the MMU.
57 */
58static const mmap_region_t tegra_mmap[] = {
59 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
60 MT_DEVICE | MT_RW | MT_SECURE),
61 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
62 MT_DEVICE | MT_RW | MT_SECURE),
63 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
64 MT_DEVICE | MT_RW | MT_SECURE),
65 {0}
66};
67
68/*******************************************************************************
69 * Set up the pagetables as per the platform memory map & initialize the MMU
70 ******************************************************************************/
71const mmap_region_t *plat_get_mmio_map(void)
72{
73 /* MMIO space */
74 return tegra_mmap;
75}
76
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010077unsigned int plat_get_syscnt_freq2(void)
Varun Wadekar0f3baa02015-07-16 11:36:33 +053078{
79 return 12000000;
80}