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Varun Wadekar0f3baa02015-07-16 11:36:33 +05301/*
Varun Wadekar84a775e2019-01-03 10:12:55 -08002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekar7cf57d72018-05-17 09:36:38 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar0f3baa02015-07-16 11:36:33 +05304 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar0f3baa02015-07-16 11:36:33 +05306 */
7
Varun Wadekarb7b45752015-12-28 14:55:41 -08008#include <arch_helpers.h>
kalyanic0a2cc612019-09-13 14:49:39 -07009#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/bl_common.h>
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070011#include <drivers/console.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <lib/xlat_tables/xlat_tables_v2.h>
Varun Wadekara1251802019-08-22 11:52:36 -070013#include <memctrl.h>
Ambroise Vincentffbf32a2019-03-28 09:01:18 +000014#include <plat/common/platform.h>
Varun Wadekar0f3baa02015-07-16 11:36:33 +053015#include <tegra_def.h>
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070016#include <tegra_platform.h>
Varun Wadekarb7b45752015-12-28 14:55:41 -080017#include <tegra_private.h>
Varun Wadekar0f3baa02015-07-16 11:36:33 +053018
Varun Wadekar0f3baa02015-07-16 11:36:33 +053019/* sets of MMIO ranges setup */
20#define MMIO_RANGE_0_ADDR 0x50000000
21#define MMIO_RANGE_1_ADDR 0x60000000
22#define MMIO_RANGE_2_ADDR 0x70000000
23#define MMIO_RANGE_SIZE 0x200000
24
25/*
26 * Table of regions to map using the MMU.
27 */
28static const mmap_region_t tegra_mmap[] = {
29 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
30 MT_DEVICE | MT_RW | MT_SECURE),
31 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
32 MT_DEVICE | MT_RW | MT_SECURE),
33 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
34 MT_DEVICE | MT_RW | MT_SECURE),
35 {0}
36};
37
38/*******************************************************************************
39 * Set up the pagetables as per the platform memory map & initialize the MMU
40 ******************************************************************************/
41const mmap_region_t *plat_get_mmio_map(void)
42{
43 /* MMIO space */
44 return tegra_mmap;
45}
46
Varun Wadekare34bc3d2017-04-28 08:43:33 -070047/*******************************************************************************
48 * The Tegra power domain tree has a single system level power domain i.e. a
49 * single root node. The first entry in the power domain descriptor specifies
50 * the number of power domains at the highest power level.
51 *******************************************************************************
52 */
53const unsigned char tegra_power_domain_tree_desc[] = {
54 /* No of root nodes */
55 1,
56 /* No of clusters */
57 PLATFORM_CLUSTER_COUNT,
58 /* No of CPU cores */
59 PLATFORM_CORE_COUNT,
60};
61
62/*******************************************************************************
63 * This function returns the Tegra default topology tree information.
64 ******************************************************************************/
65const unsigned char *plat_get_power_domain_tree_desc(void)
66{
67 return tegra_power_domain_tree_desc;
68}
69
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010070unsigned int plat_get_syscnt_freq2(void)
Varun Wadekar0f3baa02015-07-16 11:36:33 +053071{
72 return 12000000;
73}
Varun Wadekard2014c62015-10-29 10:37:28 +053074
75/*******************************************************************************
76 * Maximum supported UART controllers
77 ******************************************************************************/
78#define TEGRA132_MAX_UART_PORTS 5
79
80/*******************************************************************************
81 * This variable holds the UART port base addresses
82 ******************************************************************************/
83static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = {
84 0, /* undefined - treated as an error case */
85 TEGRA_UARTA_BASE,
86 TEGRA_UARTB_BASE,
87 TEGRA_UARTC_BASE,
88 TEGRA_UARTD_BASE,
89 TEGRA_UARTE_BASE,
90};
91
92/*******************************************************************************
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070093 * Enable console corresponding to the console ID
Varun Wadekard2014c62015-10-29 10:37:28 +053094 ******************************************************************************/
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070095void plat_enable_console(int32_t id)
Varun Wadekard2014c62015-10-29 10:37:28 +053096{
Andre Przywara98b5a112020-01-25 00:58:35 +000097 static console_t uart_console;
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070098 uint32_t console_clock;
99
100 if ((id > 0) && (id < TEGRA132_MAX_UART_PORTS)) {
101 /*
102 * Reference clock used by the FPGAs is a lot slower.
103 */
104 if (tegra_platform_is_fpga()) {
105 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
106 } else {
107 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
108 }
Varun Wadekard2014c62015-10-29 10:37:28 +0530109
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700110 (void)console_16550_register(tegra132_uart_addresses[id],
111 console_clock,
112 TEGRA_CONSOLE_BAUDRATE,
113 &uart_console);
Andre Przywara98b5a112020-01-25 00:58:35 +0000114 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700115 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
116 }
Varun Wadekard2014c62015-10-29 10:37:28 +0530117}
Varun Wadekarb7b45752015-12-28 14:55:41 -0800118
119/*******************************************************************************
120 * Initialize the GIC and SGIs
121 ******************************************************************************/
122void plat_gic_setup(void)
123{
124 tegra_gic_setup(NULL, 0);
Varun Wadekar84a775e2019-01-03 10:12:55 -0800125 tegra_gic_init();
Varun Wadekarb7b45752015-12-28 14:55:41 -0800126}
Varun Wadekar7cf57d72018-05-17 09:36:38 -0700127
128/*******************************************************************************
129 * Return pointer to the BL31 params from previous bootloader
130 ******************************************************************************/
131struct tegra_bl31_params *plat_get_bl31_params(void)
132{
133 return NULL;
134}
135
136/*******************************************************************************
137 * Return pointer to the BL31 platform params from previous bootloader
138 ******************************************************************************/
139plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
140{
141 return NULL;
142}
143
144/*******************************************************************************
145 * Handler for early platform setup
146 ******************************************************************************/
147void plat_early_platform_setup(void)
148{
Varun Wadekara1251802019-08-22 11:52:36 -0700149 plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
150
kalyanic0a2cc612019-09-13 14:49:39 -0700151 /* Verify chip id is t132 */
152 assert(tegra_chipid_is_t132());
Varun Wadekara1251802019-08-22 11:52:36 -0700153
154 /*
155 * Do initial security configuration to allow DRAM/device access.
156 */
157 tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
158 (uint32_t)plat_params->tzdram_size);
Varun Wadekar7cf57d72018-05-17 09:36:38 -0700159}
160
161/*******************************************************************************
162 * Handler for late platform setup
163 ******************************************************************************/
164void plat_late_platform_setup(void)
165{
166 ; /* do nothing */
167}
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700168
169/*******************************************************************************
170 * Handler to indicate support for System Suspend
171 ******************************************************************************/
172bool plat_supports_system_suspend(void)
173{
174 return true;
175}