Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 1 | /* |
Michal Simek | 2a47faa | 2023-04-14 08:43:51 +0200 | [diff] [blame] | 2 | * Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved. |
Akshay Belsare | ec0afc8 | 2023-02-27 12:04:26 +0530 | [diff] [blame] | 3 | * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. |
| 4 | * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 5 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 6 | * SPDX-License-Identifier: BSD-3-Clause |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 7 | */ |
| 8 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 9 | #ifndef PLATFORM_DEF_H |
| 10 | #define PLATFORM_DEF_H |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 11 | |
| 12 | #include <arch.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 13 | #include <common/interrupt_props.h> |
| 14 | #include <drivers/arm/gic_common.h> |
| 15 | #include <lib/utils_def.h> |
| 16 | |
Jolly Shah | 16fe5ab | 2019-01-08 11:16:16 -0800 | [diff] [blame] | 17 | #include "zynqmp_def.h" |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 18 | |
| 19 | /******************************************************************************* |
| 20 | * Generic platform constants |
| 21 | ******************************************************************************/ |
| 22 | |
| 23 | /* Size of cacheable stacks */ |
Akshay Belsare | 32d5c90 | 2023-04-06 16:21:06 +0530 | [diff] [blame] | 24 | #ifndef PLATFORM_STACK_SIZE |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 25 | #define PLATFORM_STACK_SIZE 0x440 |
Akshay Belsare | 32d5c90 | 2023-04-06 16:21:06 +0530 | [diff] [blame] | 26 | #endif |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 27 | |
Deepika Bhavnani | b16bada | 2019-12-13 10:53:56 -0600 | [diff] [blame] | 28 | #define PLATFORM_CORE_COUNT U(4) |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 29 | #define PLAT_MAX_PWR_LVL U(1) |
| 30 | #define PLAT_MAX_RET_STATE U(1) |
| 31 | #define PLAT_MAX_OFF_STATE U(2) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 32 | |
| 33 | /******************************************************************************* |
| 34 | * BL31 specific defines. |
| 35 | ******************************************************************************/ |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 36 | /* |
| 37 | * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if |
| 38 | * present). BL31_BASE is calculated using the current BL31 debug size plus a |
| 39 | * little space for growth. |
| 40 | */ |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 41 | #ifndef ZYNQMP_ATF_MEM_BASE |
Jan Kiszka | e1407fc | 2020-07-14 22:36:59 +0200 | [diff] [blame] | 42 | #if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 43 | # define BL31_BASE U(0xfffea000) |
| 44 | # define BL31_LIMIT U(0x100000000) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 45 | #else |
Akshay Belsare | 69c6a59 | 2023-02-15 10:49:52 +0530 | [diff] [blame] | 46 | # define BL31_BASE U(0x1000) |
Ilias Apalodimas | bd54123 | 2023-05-18 12:05:43 +0300 | [diff] [blame] | 47 | # define BL31_LIMIT U(0x80000) |
Jolly Shah | 8f5ddb3 | 2018-01-30 11:31:53 -0800 | [diff] [blame] | 48 | #endif |
| 49 | #else |
Akshay Belsare | e748f9f | 2023-06-08 11:19:54 +0530 | [diff] [blame^] | 50 | # define BL31_BASE U(ZYNQMP_ATF_MEM_BASE) |
| 51 | # define BL31_LIMIT (UL(ZYNQMP_ATF_MEM_BASE) + U(ZYNQMP_ATF_MEM_SIZE)) |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 52 | # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE |
Akshay Belsare | e748f9f | 2023-06-08 11:19:54 +0530 | [diff] [blame^] | 53 | # define BL31_PROGBITS_LIMIT (UL(ZYNQMP_ATF_MEM_BASE) + U(ZYNQMP_ATF_MEM_PROGBITS_SIZE)) |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 54 | # endif |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 55 | #endif |
| 56 | |
| 57 | /******************************************************************************* |
| 58 | * BL32 specific defines. |
| 59 | ******************************************************************************/ |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 60 | #ifndef ZYNQMP_BL32_MEM_BASE |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 61 | # define BL32_BASE U(0x60000000) |
Ilias Apalodimas | bd54123 | 2023-05-18 12:05:43 +0300 | [diff] [blame] | 62 | # define BL32_LIMIT U(0x80000000) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 63 | #else |
Akshay Belsare | e748f9f | 2023-06-08 11:19:54 +0530 | [diff] [blame^] | 64 | # define BL32_BASE U(ZYNQMP_BL32_MEM_BASE) |
| 65 | # define BL32_LIMIT (UL(ZYNQMP_BL32_MEM_BASE) + U(ZYNQMP_BL32_MEM_SIZE)) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 66 | #endif |
| 67 | |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 68 | /******************************************************************************* |
| 69 | * BL33 specific defines. |
| 70 | ******************************************************************************/ |
| 71 | #ifndef PRELOADED_BL33_BASE |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 72 | # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 73 | #else |
Akshay Belsare | e748f9f | 2023-06-08 11:19:54 +0530 | [diff] [blame^] | 74 | # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 75 | #endif |
| 76 | |
| 77 | /******************************************************************************* |
| 78 | * TSP specific defines. |
| 79 | ******************************************************************************/ |
| 80 | #define TSP_SEC_MEM_BASE BL32_BASE |
Ilias Apalodimas | bd54123 | 2023-05-18 12:05:43 +0300 | [diff] [blame] | 81 | #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 82 | |
| 83 | /* ID of the secure physical generic timer interrupt used by the TSP */ |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 84 | #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER |
| 85 | |
| 86 | /******************************************************************************* |
| 87 | * Platform specific page table and MMU setup constants |
| 88 | ******************************************************************************/ |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 89 | #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) |
| 90 | #define PLAT_DDR_LOWMEM_MAX U(0x80000000) |
Akshay Belsare | ec0afc8 | 2023-02-27 12:04:26 +0530 | [diff] [blame] | 91 | #define PLAT_OCM_BASE U(0xFFFC0000) |
| 92 | #define PLAT_OCM_LIMIT U(0xFFFFFFFF) |
| 93 | |
| 94 | #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) |
Michal Simek | 53865b0 | 2021-05-27 09:42:37 +0200 | [diff] [blame] | 95 | |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 96 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 97 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
Amit Nagal | 71e1ffc | 2023-02-23 21:37:23 +0530 | [diff] [blame] | 98 | |
| 99 | #ifndef MAX_MMAP_REGIONS |
Akshay Belsare | ec0afc8 | 2023-02-27 12:04:26 +0530 | [diff] [blame] | 100 | #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) |
Michal Simek | 53865b0 | 2021-05-27 09:42:37 +0200 | [diff] [blame] | 101 | #define MAX_MMAP_REGIONS 8 |
| 102 | #else |
Soren Brinkmann | 6d1ba58 | 2016-07-08 14:45:14 -0700 | [diff] [blame] | 103 | #define MAX_MMAP_REGIONS 7 |
Amit Nagal | 71e1ffc | 2023-02-23 21:37:23 +0530 | [diff] [blame] | 104 | #endif |
| 105 | #endif |
| 106 | |
| 107 | #ifndef MAX_XLAT_TABLES |
Akshay Belsare | ec0afc8 | 2023-02-27 12:04:26 +0530 | [diff] [blame] | 108 | #if !IS_TFA_IN_OCM(BL31_BASE) |
Amit Nagal | 71e1ffc | 2023-02-23 21:37:23 +0530 | [diff] [blame] | 109 | #define MAX_XLAT_TABLES 8 |
| 110 | #else |
Soren Brinkmann | 7ac746c | 2016-07-25 10:33:53 -0700 | [diff] [blame] | 111 | #define MAX_XLAT_TABLES 5 |
Venkatesh Yadav Abbarapu | 586e192 | 2022-03-01 22:10:05 -0700 | [diff] [blame] | 112 | #endif |
Amit Nagal | 71e1ffc | 2023-02-23 21:37:23 +0530 | [diff] [blame] | 113 | #endif |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 114 | |
| 115 | #define CACHE_WRITEBACK_SHIFT 6 |
| 116 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 117 | |
Jan Kiszka | e1407fc | 2020-07-14 22:36:59 +0200 | [diff] [blame] | 118 | #define ZYNQMP_SDEI_SGI_PRIVATE U(8) |
| 119 | |
| 120 | /* Platform macros to support exception handling framework */ |
| 121 | #define PLAT_PRI_BITS U(3) |
| 122 | #define PLAT_SDEI_CRITICAL_PRI 0x10 |
| 123 | #define PLAT_SDEI_NORMAL_PRI 0x20 |
| 124 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 125 | #define PLAT_ARM_GICD_BASE BASE_GICD_BASE |
| 126 | #define PLAT_ARM_GICC_BASE BASE_GICC_BASE |
| 127 | /* |
Jeenu Viswambharan | 9bde130 | 2017-09-29 11:15:18 +0100 | [diff] [blame] | 128 | * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 129 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 130 | * as Group 0 interrupts. |
| 131 | */ |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 132 | #if !ZYNQMP_WDT_RESTART |
Jeenu Viswambharan | 9bde130 | 2017-09-29 11:15:18 +0100 | [diff] [blame] | 133 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 134 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 135 | GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 9bde130 | 2017-09-29 11:15:18 +0100 | [diff] [blame] | 136 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 137 | GIC_INTR_CFG_EDGE), \ |
| 138 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 139 | GIC_INTR_CFG_EDGE), \ |
| 140 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 141 | GIC_INTR_CFG_EDGE), \ |
| 142 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 143 | GIC_INTR_CFG_EDGE), \ |
| 144 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 145 | GIC_INTR_CFG_EDGE), \ |
| 146 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 147 | GIC_INTR_CFG_EDGE), \ |
| 148 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 149 | GIC_INTR_CFG_EDGE) |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 150 | #else |
| 151 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 152 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 153 | GIC_INTR_CFG_LEVEL), \ |
| 154 | INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 155 | GIC_INTR_CFG_EDGE), \ |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 156 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 157 | GIC_INTR_CFG_EDGE), \ |
| 158 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 159 | GIC_INTR_CFG_EDGE), \ |
| 160 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 161 | GIC_INTR_CFG_EDGE), \ |
| 162 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 163 | GIC_INTR_CFG_EDGE), \ |
| 164 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 165 | GIC_INTR_CFG_EDGE), \ |
| 166 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 167 | GIC_INTR_CFG_EDGE), \ |
| 168 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 169 | GIC_INTR_CFG_EDGE) |
| 170 | #endif |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 171 | |
Jan Kiszka | e1407fc | 2020-07-14 22:36:59 +0200 | [diff] [blame] | 172 | #define PLAT_ARM_G0_IRQ_PROPS(grp) \ |
| 173 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \ |
| 174 | GIC_INTR_CFG_EDGE) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 175 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 176 | #endif /* PLATFORM_DEF_H */ |