commit 586e192bbc044cce8df91997069cd750b2cd0816
author Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Tue Mar 01 22:10:05 2022 -0700
committer Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Wed Mar 02 02:25:14 2022 -0700
tree 077647d99ab77ed557a026b51ea4e9feb0274fbb
parent 5f404854358cf4bddab3590f4e7d3b2705dbc4c8

feat(zynqmp): increase the max xlat tables when debug build is enabled

Update the MAX_XLAT_TABLES as the memory map has been
added for the dtb to accomodate in DDR address.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I46225673f40f123cdab38efefb038604da119b58

plat/xilinx/zynqmp/include/platform_def.h

diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h
index 0c5f621..1c4daa1 100644
--- a/plat/xilinx/zynqmp/include/platform_def.h
+++ b/plat/xilinx/zynqmp/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -91,10 +91,11 @@
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
 #if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
 #define MAX_MMAP_REGIONS		8
+#define MAX_XLAT_TABLES			6
 #else
 #define MAX_MMAP_REGIONS		7
-#endif
 #define MAX_XLAT_TABLES			5
+#endif
 
 #define CACHE_WRITEBACK_SHIFT   6
 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)