Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 1 | /* |
Michal Simek | 2a47faa | 2023-04-14 08:43:51 +0200 | [diff] [blame^] | 2 | * Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved. |
Akshay Belsare | ec0afc8 | 2023-02-27 12:04:26 +0530 | [diff] [blame] | 3 | * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. |
| 4 | * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 5 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 6 | * SPDX-License-Identifier: BSD-3-Clause |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 7 | */ |
| 8 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 9 | #ifndef PLATFORM_DEF_H |
| 10 | #define PLATFORM_DEF_H |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 11 | |
| 12 | #include <arch.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 13 | #include <common/interrupt_props.h> |
| 14 | #include <drivers/arm/gic_common.h> |
| 15 | #include <lib/utils_def.h> |
| 16 | |
Jolly Shah | 16fe5ab | 2019-01-08 11:16:16 -0800 | [diff] [blame] | 17 | #include "zynqmp_def.h" |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 18 | |
| 19 | /******************************************************************************* |
| 20 | * Generic platform constants |
| 21 | ******************************************************************************/ |
| 22 | |
| 23 | /* Size of cacheable stacks */ |
Akshay Belsare | 32d5c90 | 2023-04-06 16:21:06 +0530 | [diff] [blame] | 24 | #ifndef PLATFORM_STACK_SIZE |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 25 | #define PLATFORM_STACK_SIZE 0x440 |
Akshay Belsare | 32d5c90 | 2023-04-06 16:21:06 +0530 | [diff] [blame] | 26 | #endif |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 27 | |
Deepika Bhavnani | b16bada | 2019-12-13 10:53:56 -0600 | [diff] [blame] | 28 | #define PLATFORM_CORE_COUNT U(4) |
| 29 | #define PLAT_NUM_POWER_DOMAINS U(5) |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 30 | #define PLAT_MAX_PWR_LVL U(1) |
| 31 | #define PLAT_MAX_RET_STATE U(1) |
| 32 | #define PLAT_MAX_OFF_STATE U(2) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 33 | |
| 34 | /******************************************************************************* |
| 35 | * BL31 specific defines. |
| 36 | ******************************************************************************/ |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 37 | /* |
| 38 | * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if |
| 39 | * present). BL31_BASE is calculated using the current BL31 debug size plus a |
| 40 | * little space for growth. |
| 41 | */ |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 42 | #ifndef ZYNQMP_ATF_MEM_BASE |
Jan Kiszka | e1407fc | 2020-07-14 22:36:59 +0200 | [diff] [blame] | 43 | #if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 44 | # define BL31_BASE U(0xfffea000) |
| 45 | # define BL31_LIMIT U(0x100000000) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 46 | #else |
Akshay Belsare | 69c6a59 | 2023-02-15 10:49:52 +0530 | [diff] [blame] | 47 | # define BL31_BASE U(0x1000) |
| 48 | # define BL31_LIMIT U(0x7ffff) |
Jolly Shah | 8f5ddb3 | 2018-01-30 11:31:53 -0800 | [diff] [blame] | 49 | #endif |
| 50 | #else |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 51 | # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) |
| 52 | # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1) |
| 53 | # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE |
| 54 | # define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1) |
| 55 | # endif |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 56 | #endif |
| 57 | |
| 58 | /******************************************************************************* |
| 59 | * BL32 specific defines. |
| 60 | ******************************************************************************/ |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 61 | #ifndef ZYNQMP_BL32_MEM_BASE |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 62 | # define BL32_BASE U(0x60000000) |
| 63 | # define BL32_LIMIT U(0x7fffffff) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 64 | #else |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 65 | # define BL32_BASE (ZYNQMP_BL32_MEM_BASE) |
| 66 | # define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 67 | #endif |
| 68 | |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 69 | /******************************************************************************* |
| 70 | * BL33 specific defines. |
| 71 | ******************************************************************************/ |
| 72 | #ifndef PRELOADED_BL33_BASE |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 73 | # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 74 | #else |
Sandrine Bailleux | afa91db | 2019-01-31 15:01:32 +0100 | [diff] [blame] | 75 | # define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE |
Soren Brinkmann | 4a9ca04 | 2016-04-14 10:27:00 -0700 | [diff] [blame] | 76 | #endif |
| 77 | |
| 78 | /******************************************************************************* |
| 79 | * TSP specific defines. |
| 80 | ******************************************************************************/ |
| 81 | #define TSP_SEC_MEM_BASE BL32_BASE |
| 82 | #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) |
| 83 | |
| 84 | /* ID of the secure physical generic timer interrupt used by the TSP */ |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 85 | #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER |
| 86 | |
| 87 | /******************************************************************************* |
| 88 | * Platform specific page table and MMU setup constants |
| 89 | ******************************************************************************/ |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 90 | #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) |
| 91 | #define PLAT_DDR_LOWMEM_MAX U(0x80000000) |
Akshay Belsare | ec0afc8 | 2023-02-27 12:04:26 +0530 | [diff] [blame] | 92 | #define PLAT_OCM_BASE U(0xFFFC0000) |
| 93 | #define PLAT_OCM_LIMIT U(0xFFFFFFFF) |
| 94 | |
| 95 | #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) |
Michal Simek | 53865b0 | 2021-05-27 09:42:37 +0200 | [diff] [blame] | 96 | |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 97 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 98 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
Amit Nagal | 71e1ffc | 2023-02-23 21:37:23 +0530 | [diff] [blame] | 99 | |
| 100 | #ifndef MAX_MMAP_REGIONS |
Akshay Belsare | ec0afc8 | 2023-02-27 12:04:26 +0530 | [diff] [blame] | 101 | #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) |
Michal Simek | 53865b0 | 2021-05-27 09:42:37 +0200 | [diff] [blame] | 102 | #define MAX_MMAP_REGIONS 8 |
| 103 | #else |
Soren Brinkmann | 6d1ba58 | 2016-07-08 14:45:14 -0700 | [diff] [blame] | 104 | #define MAX_MMAP_REGIONS 7 |
Amit Nagal | 71e1ffc | 2023-02-23 21:37:23 +0530 | [diff] [blame] | 105 | #endif |
| 106 | #endif |
| 107 | |
| 108 | #ifndef MAX_XLAT_TABLES |
Akshay Belsare | ec0afc8 | 2023-02-27 12:04:26 +0530 | [diff] [blame] | 109 | #if !IS_TFA_IN_OCM(BL31_BASE) |
Amit Nagal | 71e1ffc | 2023-02-23 21:37:23 +0530 | [diff] [blame] | 110 | #define MAX_XLAT_TABLES 8 |
| 111 | #else |
Soren Brinkmann | 7ac746c | 2016-07-25 10:33:53 -0700 | [diff] [blame] | 112 | #define MAX_XLAT_TABLES 5 |
Venkatesh Yadav Abbarapu | 586e192 | 2022-03-01 22:10:05 -0700 | [diff] [blame] | 113 | #endif |
Amit Nagal | 71e1ffc | 2023-02-23 21:37:23 +0530 | [diff] [blame] | 114 | #endif |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 115 | |
| 116 | #define CACHE_WRITEBACK_SHIFT 6 |
| 117 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 118 | |
Jan Kiszka | e1407fc | 2020-07-14 22:36:59 +0200 | [diff] [blame] | 119 | #define ZYNQMP_SDEI_SGI_PRIVATE U(8) |
| 120 | |
| 121 | /* Platform macros to support exception handling framework */ |
| 122 | #define PLAT_PRI_BITS U(3) |
| 123 | #define PLAT_SDEI_CRITICAL_PRI 0x10 |
| 124 | #define PLAT_SDEI_NORMAL_PRI 0x20 |
| 125 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 126 | #define PLAT_ARM_GICD_BASE BASE_GICD_BASE |
| 127 | #define PLAT_ARM_GICC_BASE BASE_GICC_BASE |
| 128 | /* |
Jeenu Viswambharan | 9bde130 | 2017-09-29 11:15:18 +0100 | [diff] [blame] | 129 | * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 130 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 131 | * as Group 0 interrupts. |
| 132 | */ |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 133 | #if !ZYNQMP_WDT_RESTART |
Jeenu Viswambharan | 9bde130 | 2017-09-29 11:15:18 +0100 | [diff] [blame] | 134 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 135 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 136 | GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 9bde130 | 2017-09-29 11:15:18 +0100 | [diff] [blame] | 137 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 138 | GIC_INTR_CFG_EDGE), \ |
| 139 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 140 | GIC_INTR_CFG_EDGE), \ |
| 141 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 142 | GIC_INTR_CFG_EDGE), \ |
| 143 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 144 | GIC_INTR_CFG_EDGE), \ |
| 145 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 146 | GIC_INTR_CFG_EDGE), \ |
| 147 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 148 | GIC_INTR_CFG_EDGE), \ |
| 149 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 150 | GIC_INTR_CFG_EDGE) |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 151 | #else |
| 152 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 153 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 154 | GIC_INTR_CFG_LEVEL), \ |
| 155 | INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 156 | GIC_INTR_CFG_EDGE), \ |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 157 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 158 | GIC_INTR_CFG_EDGE), \ |
| 159 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 160 | GIC_INTR_CFG_EDGE), \ |
| 161 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 162 | GIC_INTR_CFG_EDGE), \ |
| 163 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 164 | GIC_INTR_CFG_EDGE), \ |
| 165 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 166 | GIC_INTR_CFG_EDGE), \ |
| 167 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 168 | GIC_INTR_CFG_EDGE), \ |
| 169 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 170 | GIC_INTR_CFG_EDGE) |
| 171 | #endif |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 172 | |
Jan Kiszka | e1407fc | 2020-07-14 22:36:59 +0200 | [diff] [blame] | 173 | #define PLAT_ARM_G0_IRQ_PROPS(grp) \ |
| 174 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \ |
| 175 | GIC_INTR_CFG_EDGE) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 176 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 177 | #endif /* PLATFORM_DEF_H */ |