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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.
Akshay Belsareec0afc82023-02-27 12:04:26 +05303 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08005 *
dp-armfa3cf0b2017-05-03 09:38:09 +01006 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08007 */
8
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01009#ifndef PLATFORM_DEF_H
10#define PLATFORM_DEF_H
Soren Brinkmann76fcae32016-03-06 20:16:27 -080011
12#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <common/interrupt_props.h>
14#include <drivers/arm/gic_common.h>
15#include <lib/utils_def.h>
16
Jolly Shah16fe5ab2019-01-08 11:16:16 -080017#include "zynqmp_def.h"
Soren Brinkmann76fcae32016-03-06 20:16:27 -080018
19/*******************************************************************************
20 * Generic platform constants
21 ******************************************************************************/
22
23/* Size of cacheable stacks */
Akshay Belsare32d5c902023-04-06 16:21:06 +053024#ifndef PLATFORM_STACK_SIZE
Soren Brinkmann76fcae32016-03-06 20:16:27 -080025#define PLATFORM_STACK_SIZE 0x440
Akshay Belsare32d5c902023-04-06 16:21:06 +053026#endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -080027
Deepika Bhavnanib16bada2019-12-13 10:53:56 -060028#define PLATFORM_CORE_COUNT U(4)
29#define PLAT_NUM_POWER_DOMAINS U(5)
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010030#define PLAT_MAX_PWR_LVL U(1)
31#define PLAT_MAX_RET_STATE U(1)
32#define PLAT_MAX_OFF_STATE U(2)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080033
34/*******************************************************************************
35 * BL31 specific defines.
36 ******************************************************************************/
Soren Brinkmann76fcae32016-03-06 20:16:27 -080037/*
38 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
39 * present). BL31_BASE is calculated using the current BL31 debug size plus a
40 * little space for growth.
41 */
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070042#ifndef ZYNQMP_ATF_MEM_BASE
Jan Kiszkae1407fc2020-07-14 22:36:59 +020043#if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT
Venkatesh Yadav Abbarapued4f1e82022-04-29 09:58:30 +053044# define BL31_BASE U(0xfffea000)
45# define BL31_LIMIT U(0x100000000)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080046#else
Akshay Belsare69c6a592023-02-15 10:49:52 +053047# define BL31_BASE U(0x1000)
48# define BL31_LIMIT U(0x7ffff)
Jolly Shah8f5ddb32018-01-30 11:31:53 -080049#endif
50#else
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070051# define BL31_BASE (ZYNQMP_ATF_MEM_BASE)
52# define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1)
53# ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
54# define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1)
55# endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -080056#endif
57
58/*******************************************************************************
59 * BL32 specific defines.
60 ******************************************************************************/
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070061#ifndef ZYNQMP_BL32_MEM_BASE
Venkatesh Yadav Abbarapued4f1e82022-04-29 09:58:30 +053062# define BL32_BASE U(0x60000000)
63# define BL32_LIMIT U(0x7fffffff)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080064#else
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070065# define BL32_BASE (ZYNQMP_BL32_MEM_BASE)
66# define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080067#endif
68
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070069/*******************************************************************************
70 * BL33 specific defines.
71 ******************************************************************************/
72#ifndef PRELOADED_BL33_BASE
Venkatesh Yadav Abbarapued4f1e82022-04-29 09:58:30 +053073# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000)
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070074#else
Sandrine Bailleuxafa91db2019-01-31 15:01:32 +010075# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070076#endif
77
78/*******************************************************************************
79 * TSP specific defines.
80 ******************************************************************************/
81#define TSP_SEC_MEM_BASE BL32_BASE
82#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
83
84/* ID of the secure physical generic timer interrupt used by the TSP */
Soren Brinkmann76fcae32016-03-06 20:16:27 -080085#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
86
87/*******************************************************************************
88 * Platform specific page table and MMU setup constants
89 ******************************************************************************/
Venkatesh Yadav Abbarapued4f1e82022-04-29 09:58:30 +053090#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000)
91#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
Akshay Belsareec0afc82023-02-27 12:04:26 +053092#define PLAT_OCM_BASE U(0xFFFC0000)
93#define PLAT_OCM_LIMIT U(0xFFFFFFFF)
94
95#define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT))
Michal Simek53865b02021-05-27 09:42:37 +020096
David Cunadoc1503122018-02-16 21:12:58 +000097#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
98#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
Amit Nagal71e1ffc2023-02-23 21:37:23 +053099
100#ifndef MAX_MMAP_REGIONS
Akshay Belsareec0afc82023-02-27 12:04:26 +0530101#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
Michal Simek53865b02021-05-27 09:42:37 +0200102#define MAX_MMAP_REGIONS 8
103#else
Soren Brinkmann6d1ba582016-07-08 14:45:14 -0700104#define MAX_MMAP_REGIONS 7
Amit Nagal71e1ffc2023-02-23 21:37:23 +0530105#endif
106#endif
107
108#ifndef MAX_XLAT_TABLES
Akshay Belsareec0afc82023-02-27 12:04:26 +0530109#if !IS_TFA_IN_OCM(BL31_BASE)
Amit Nagal71e1ffc2023-02-23 21:37:23 +0530110#define MAX_XLAT_TABLES 8
111#else
Soren Brinkmann7ac746c2016-07-25 10:33:53 -0700112#define MAX_XLAT_TABLES 5
Venkatesh Yadav Abbarapu586e1922022-03-01 22:10:05 -0700113#endif
Amit Nagal71e1ffc2023-02-23 21:37:23 +0530114#endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800115
116#define CACHE_WRITEBACK_SHIFT 6
117#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
118
Jan Kiszkae1407fc2020-07-14 22:36:59 +0200119#define ZYNQMP_SDEI_SGI_PRIVATE U(8)
120
121/* Platform macros to support exception handling framework */
122#define PLAT_PRI_BITS U(3)
123#define PLAT_SDEI_CRITICAL_PRI 0x10
124#define PLAT_SDEI_NORMAL_PRI 0x20
125
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800126#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
127#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
128/*
Jeenu Viswambharan9bde1302017-09-29 11:15:18 +0100129 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800130 * terminology. On a GICv2 system or mode, the lists will be merged and treated
131 * as Group 0 interrupts.
132 */
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530133#if !ZYNQMP_WDT_RESTART
Jeenu Viswambharan9bde1302017-09-29 11:15:18 +0100134#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
135 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
136 GIC_INTR_CFG_LEVEL), \
Jeenu Viswambharan9bde1302017-09-29 11:15:18 +0100137 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
138 GIC_INTR_CFG_EDGE), \
139 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
140 GIC_INTR_CFG_EDGE), \
141 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
142 GIC_INTR_CFG_EDGE), \
143 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
144 GIC_INTR_CFG_EDGE), \
145 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
146 GIC_INTR_CFG_EDGE), \
147 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
148 GIC_INTR_CFG_EDGE), \
149 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
150 GIC_INTR_CFG_EDGE)
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530151#else
152#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
153 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
154 GIC_INTR_CFG_LEVEL), \
155 INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
156 GIC_INTR_CFG_EDGE), \
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530157 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
158 GIC_INTR_CFG_EDGE), \
159 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
160 GIC_INTR_CFG_EDGE), \
161 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
162 GIC_INTR_CFG_EDGE), \
163 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
164 GIC_INTR_CFG_EDGE), \
165 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
166 GIC_INTR_CFG_EDGE), \
167 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
168 GIC_INTR_CFG_EDGE), \
169 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
170 GIC_INTR_CFG_EDGE)
171#endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800172
Jan Kiszkae1407fc2020-07-14 22:36:59 +0200173#define PLAT_ARM_G0_IRQ_PROPS(grp) \
174 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \
175 GIC_INTR_CFG_EDGE)
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800176
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100177#endif /* PLATFORM_DEF_H */