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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01002 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08005 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Soren Brinkmann76fcae32016-03-06 20:16:27 -08009
10#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/interrupt_props.h>
12#include <drivers/arm/gic_common.h>
13#include <lib/utils_def.h>
14
Jolly Shah16fe5ab2019-01-08 11:16:16 -080015#include "zynqmp_def.h"
Soren Brinkmann76fcae32016-03-06 20:16:27 -080016
17/*******************************************************************************
18 * Generic platform constants
19 ******************************************************************************/
20
21/* Size of cacheable stacks */
22#define PLATFORM_STACK_SIZE 0x440
23
24#define PLATFORM_CORE_COUNT 4
25#define PLAT_NUM_POWER_DOMAINS 5
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010026#define PLAT_MAX_PWR_LVL U(1)
27#define PLAT_MAX_RET_STATE U(1)
28#define PLAT_MAX_OFF_STATE U(2)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080029
30/*******************************************************************************
31 * BL31 specific defines.
32 ******************************************************************************/
Soren Brinkmann76fcae32016-03-06 20:16:27 -080033/*
34 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
35 * present). BL31_BASE is calculated using the current BL31 debug size plus a
36 * little space for growth.
37 */
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070038#ifndef ZYNQMP_ATF_MEM_BASE
Siva Durga Prasad Paladuguee1a1142018-06-20 17:01:13 +053039#if !DEBUG && defined(SPD_none)
Soren Brinkmann802ba1d2016-07-15 06:23:37 -070040# define BL31_BASE 0xfffea000
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070041# define BL31_LIMIT 0xffffffff
Soren Brinkmann76fcae32016-03-06 20:16:27 -080042#else
Jolly Shah8f5ddb32018-01-30 11:31:53 -080043# define BL31_BASE 0x1000
44# define BL31_LIMIT 0x7ffff
45#endif
46#else
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070047# define BL31_BASE (ZYNQMP_ATF_MEM_BASE)
48# define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1)
49# ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
50# define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1)
51# endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -080052#endif
53
54/*******************************************************************************
55 * BL32 specific defines.
56 ******************************************************************************/
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070057#ifndef ZYNQMP_BL32_MEM_BASE
58# define BL32_BASE 0x60000000
59# define BL32_LIMIT 0x7fffffff
Soren Brinkmann76fcae32016-03-06 20:16:27 -080060#else
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070061# define BL32_BASE (ZYNQMP_BL32_MEM_BASE)
62# define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080063#endif
64
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070065/*******************************************************************************
66 * BL33 specific defines.
67 ******************************************************************************/
68#ifndef PRELOADED_BL33_BASE
Sandrine Bailleuxafa91db2019-01-31 15:01:32 +010069# define PLAT_ARM_NS_IMAGE_BASE 0x8000000
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070070#else
Sandrine Bailleuxafa91db2019-01-31 15:01:32 +010071# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070072#endif
73
74/*******************************************************************************
75 * TSP specific defines.
76 ******************************************************************************/
77#define TSP_SEC_MEM_BASE BL32_BASE
78#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
79
80/* ID of the secure physical generic timer interrupt used by the TSP */
Soren Brinkmann76fcae32016-03-06 20:16:27 -080081#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
82
83/*******************************************************************************
84 * Platform specific page table and MMU setup constants
85 ******************************************************************************/
David Cunadoc1503122018-02-16 21:12:58 +000086#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
87#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
Soren Brinkmann6d1ba582016-07-08 14:45:14 -070088#define MAX_MMAP_REGIONS 7
Soren Brinkmann7ac746c2016-07-25 10:33:53 -070089#define MAX_XLAT_TABLES 5
Soren Brinkmann76fcae32016-03-06 20:16:27 -080090
91#define CACHE_WRITEBACK_SHIFT 6
92#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
93
94#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
95#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
96/*
Jeenu Viswambharan9bde1302017-09-29 11:15:18 +010097 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
Soren Brinkmann76fcae32016-03-06 20:16:27 -080098 * terminology. On a GICv2 system or mode, the lists will be merged and treated
99 * as Group 0 interrupts.
100 */
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530101#if !ZYNQMP_WDT_RESTART
Jeenu Viswambharan9bde1302017-09-29 11:15:18 +0100102#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
103 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
104 GIC_INTR_CFG_LEVEL), \
105 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
106 GIC_INTR_CFG_EDGE), \
107 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
108 GIC_INTR_CFG_EDGE), \
109 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
110 GIC_INTR_CFG_EDGE), \
111 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
112 GIC_INTR_CFG_EDGE), \
113 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
114 GIC_INTR_CFG_EDGE), \
115 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
116 GIC_INTR_CFG_EDGE), \
117 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
118 GIC_INTR_CFG_EDGE), \
119 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
120 GIC_INTR_CFG_EDGE)
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530121#else
122#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
123 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
124 GIC_INTR_CFG_LEVEL), \
125 INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
126 GIC_INTR_CFG_EDGE), \
127 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
128 GIC_INTR_CFG_EDGE), \
129 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
130 GIC_INTR_CFG_EDGE), \
131 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
132 GIC_INTR_CFG_EDGE), \
133 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
134 GIC_INTR_CFG_EDGE), \
135 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
136 GIC_INTR_CFG_EDGE), \
137 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
138 GIC_INTR_CFG_EDGE), \
139 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
140 GIC_INTR_CFG_EDGE), \
141 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
142 GIC_INTR_CFG_EDGE)
143#endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800144
Jeenu Viswambharan9bde1302017-09-29 11:15:18 +0100145#define PLAT_ARM_G0_IRQ_PROPS(grp)
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800146
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100147#endif /* PLATFORM_DEF_H */