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Nishanth Menon0192f892016-10-14 01:13:34 +00001#
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +00002# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
Nishanth Menon0192f892016-10-14 01:13:34 +00003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7# We don't use BL1 or BL2, so BL31 is the first image to execute
8RESET_TO_BL31 := 1
9# Only one core starts up at first
10COLD_BOOT_SINGLE_CPU := 1
11# We can choose where a core starts executing
12PROGRAMMABLE_RESET_ADDRESS:= 1
13
14# System coherency is managed in hardware
Andrew F. Davisf86a5de2019-04-25 14:02:33 -040015WARMBOOT_ENABLE_DCACHE_EARLY := 1
16USE_COHERENT_MEM := 1
Nishanth Menon0192f892016-10-14 01:13:34 +000017
Nishanth Menon0192f892016-10-14 01:13:34 +000018# A53 erratum for SoC. (enable them all)
19ERRATA_A53_826319 := 1
20ERRATA_A53_835769 := 1
21ERRATA_A53_836870 := 1
22ERRATA_A53_843419 := 1
23ERRATA_A53_855873 := 1
24
Nishanth Menon4f9ef162018-06-22 06:36:29 -050025# A72 Erratum for SoC
26ERRATA_A72_859971 := 1
27
Andrew F. Davis8d19f1c2019-05-14 15:38:11 -050028CRASH_REPORTING := 1
29HANDLE_EA_EL3_FIRST := 1
30
Andrew F. Davis26e89122019-01-22 14:16:03 -060031# Split out RO data into a non-executable section
32SEPARATE_CODE_AND_RODATA := 1
33
Andrew F. Davis4ab7e012019-01-04 16:04:01 -060034# Generate a Position Independent Executable
35ENABLE_PIE := 1
36
Nishanth Menonce976042016-10-14 01:13:44 +000037TI_16550_MDR_QUIRK := 1
38$(eval $(call add_define,TI_16550_MDR_QUIRK))
39
Jan Kiszkab99c0782020-05-20 07:35:48 +020040K3_USART := 0
41$(eval $(call add_define,K3_USART))
42
Andreas Dannenberg5e6d1402019-01-14 13:20:15 -060043# Allow customizing the UART baud rate
44K3_USART_BAUD := 115200
45$(eval $(call add_define,K3_USART_BAUD))
46
Nishanth Menon3ed1b282016-10-14 01:13:45 +000047# Libraries
48include lib/xlat_tables_v2/xlat_tables.mk
49
Nishanth Menon0192f892016-10-14 01:13:34 +000050PLAT_INCLUDES += \
51 -I${PLAT_PATH}/include \
Andrew F. Davis537d3ff2018-05-04 19:06:08 +000052 -I${PLAT_PATH}/common/drivers/sec_proxy \
Andrew F. Davisa513b2a2018-05-04 19:06:09 +000053 -I${PLAT_PATH}/common/drivers/ti_sci \
Nishanth Menon0192f892016-10-14 01:13:34 +000054
Nishanth Menonce976042016-10-14 01:13:44 +000055K3_CONSOLE_SOURCES += \
Nishanth Menonce976042016-10-14 01:13:44 +000056 drivers/ti/uart/aarch64/16550_console.S \
57 ${PLAT_PATH}/common/k3_console.c \
58
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +000059# Include GICv3 driver files
60include drivers/arm/gic/v3/gicv3.mk
61
Nishanth Menonf97ad372016-10-14 01:13:49 +000062K3_GIC_SOURCES += \
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +000063 ${GICV3_SOURCES} \
Nishanth Menonf97ad372016-10-14 01:13:49 +000064 plat/common/plat_gicv3.c \
65 ${PLAT_PATH}/common/k3_gicv3.c \
66
Benjamin Faira42b61b2016-10-14 01:13:46 +000067K3_PSCI_SOURCES += \
68 plat/common/plat_psci_common.c \
69 ${PLAT_PATH}/common/k3_psci.c \
70
Andrew F. Davis537d3ff2018-05-04 19:06:08 +000071K3_SEC_PROXY_SOURCES += \
72 ${PLAT_PATH}/common/drivers/sec_proxy/sec_proxy.c \
73
Andrew F. Davisa513b2a2018-05-04 19:06:09 +000074K3_TI_SCI_SOURCES += \
75 ${PLAT_PATH}/common/drivers/ti_sci/ti_sci.c \
76
Nishanth Menon0192f892016-10-14 01:13:34 +000077PLAT_BL_COMMON_SOURCES += \
78 lib/cpus/aarch64/cortex_a53.S \
Nishanth Menon4f9ef162018-06-22 06:36:29 -050079 lib/cpus/aarch64/cortex_a72.S \
Nishanth Menon3ed1b282016-10-14 01:13:45 +000080 ${XLAT_TABLES_LIB_SRCS} \
Nishanth Menonce976042016-10-14 01:13:44 +000081 ${K3_CONSOLE_SOURCES} \
Nishanth Menon0192f892016-10-14 01:13:34 +000082
83BL31_SOURCES += \
84 ${PLAT_PATH}/common/k3_bl31_setup.c \
Benjamin Fairf807a342016-10-18 14:32:06 -050085 ${PLAT_PATH}/common/k3_helpers.S \
Benjamin Fair42eea872016-10-14 01:13:47 +000086 ${PLAT_PATH}/common/k3_topology.c \
Nishanth Menonf97ad372016-10-14 01:13:49 +000087 ${K3_GIC_SOURCES} \
Benjamin Faira42b61b2016-10-14 01:13:46 +000088 ${K3_PSCI_SOURCES} \
Andrew F. Davis537d3ff2018-05-04 19:06:08 +000089 ${K3_SEC_PROXY_SOURCES} \
Andrew F. Davisa513b2a2018-05-04 19:06:09 +000090 ${K3_TI_SCI_SOURCES} \