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Ghennadi Procopciucf648e5d2024-06-12 09:07:16 +03001/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#include <drivers/clk.h>
7#include <s32cc-clk-drv.h>
8#include <s32cc-clk-ids.h>
9#include <s32cc-clk-utils.h>
10
11#define S32CC_FXOSC_FREQ (40U * MHZ)
Ghennadi Procopciuce18cf332024-06-12 11:55:32 +030012#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
Ghennadi Procopciuc907f6542024-06-12 12:00:15 +030013#define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ)
Ghennadi Procopciucf648e5d2024-06-12 09:07:16 +030014
15int s32cc_init_early_clks(void)
16{
17 int ret;
18
19 s32cc_clk_register_drv();
20
Ghennadi Procopciuc4e4786d2024-06-12 11:17:37 +030021 ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC);
22 if (ret != 0) {
23 return ret;
24 }
25
26 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0);
27 if (ret != 0) {
28 return ret;
29 }
30
Ghennadi Procopciucf648e5d2024-06-12 09:07:16 +030031 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL);
32 if (ret != 0) {
33 return ret;
34 }
35
Ghennadi Procopciuce18cf332024-06-12 11:55:32 +030036 ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL);
37 if (ret != 0) {
38 return ret;
39 }
40
Ghennadi Procopciuc907f6542024-06-12 12:00:15 +030041 ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL);
42 if (ret != 0) {
43 return ret;
44 }
45
Ghennadi Procopciuc9dee8e42024-06-12 09:25:17 +030046 ret = clk_enable(S32CC_CLK_FXOSC);
47 if (ret != 0) {
48 return ret;
49 }
50
Ghennadi Procopciucf648e5d2024-06-12 09:07:16 +030051 return ret;
52}