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git01.mediatek.com / filogic / atf / e4f708ddf4c3ab61f92bdae8d43cf69e316d2749 / drivers / nxp / clk / s32cc / s32cc_early_clks.c
  1. 907f654 feat(nxp-clk): set rate for PLL divider objects by Ghennadi Procopciuc · Wed Jun 12 12:00:15 2024 +0300
  2. e18cf33 feat(nxp-clk): set rate for PLL objects by Ghennadi Procopciuc · Wed Jun 12 11:55:32 2024 +0300
  3. 4e4786d feat(nxp-clk): set parent for ARM PLL and MC_CGM muxes by Ghennadi Procopciuc · Wed Jun 12 11:17:37 2024 +0300
  4. 9dee8e4 feat(nxp-clk): add FXOSC clock enablement by Ghennadi Procopciuc · Wed Jun 12 09:25:17 2024 +0300
  5. f648e5d feat(s32g274a): enable BL2 early clocks by Ghennadi Procopciuc · Wed Jun 12 09:07:16 2024 +0300