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Hadi Asyrafi616da772019-06-27 11:34:03 +08001/*
Jit Loon Lim86f6fb32023-05-17 12:26:11 +08002 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
Jit Loon Limb24dddf2023-05-17 12:26:11 +08003 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
Hadi Asyrafi616da772019-06-27 11:34:03 +08004 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include <arch_helpers.h>
9#include <common/debug.h>
Jit Loon Limb24dddf2023-05-17 12:26:11 +080010
11#ifndef GICV3_SUPPORT_GIC600
Hadi Asyrafi616da772019-06-27 11:34:03 +080012#include <drivers/arm/gicv2.h>
Jit Loon Lim86f6fb32023-05-17 12:26:11 +080013#else
14#include <drivers/arm/gicv3.h>
15#endif
Hadi Asyrafi616da772019-06-27 11:34:03 +080016#include <lib/mmio.h>
17#include <lib/psci/psci.h>
18#include <plat/common/platform.h>
Hadi Asyrafi6f8a2b22019-10-23 18:34:14 +080019#include "socfpga_mailbox.h"
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +080020#include "socfpga_plat_def.h"
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +080021#include "socfpga_reset_manager.h"
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +080022#include "socfpga_sip_svc.h"
Jit Loon Lim86f6fb32023-05-17 12:26:11 +080023#include "socfpga_system_manager.h"
Hadi Asyrafi616da772019-06-27 11:34:03 +080024
Jit Loon Limb24dddf2023-05-17 12:26:11 +080025#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
26void socfpga_wakeup_secondary_cpu(unsigned int cpu_id);
27extern void plat_secondary_cold_boot_setup(void);
28#endif
Hadi Asyrafi616da772019-06-27 11:34:03 +080029
Hadi Asyrafi616da772019-06-27 11:34:03 +080030/*******************************************************************************
31 * plat handler called when a CPU is about to enter standby.
32 ******************************************************************************/
33void socfpga_cpu_standby(plat_local_state_t cpu_state)
34{
35 /*
36 * Enter standby state
37 * dsb is good practice before using wfi to enter low power states
38 */
39 VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state);
40 dsb();
41 wfi();
42}
43
44/*******************************************************************************
45 * plat handler called when a power domain is about to be turned on. The
46 * mpidr determines the CPU to be turned on.
47 ******************************************************************************/
48int socfpga_pwr_domain_on(u_register_t mpidr)
49{
50 unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
Jit Loon Limb24dddf2023-05-17 12:26:11 +080051#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
52 /* TODO: Add in CPU FUSE from SDM */
53#else
Jit Loon Lim44c61fc2023-03-02 13:38:53 +080054 uint32_t psci_boot = 0x00;
Hadi Asyrafi616da772019-06-27 11:34:03 +080055
56 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
Jit Loon Limb24dddf2023-05-17 12:26:11 +080057#endif
Hadi Asyrafi616da772019-06-27 11:34:03 +080058
59 if (cpu_id == -1)
60 return PSCI_E_INTERN_FAIL;
61
Jit Loon Limb24dddf2023-05-17 12:26:11 +080062#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
Jit Loon Lim44c61fc2023-03-02 13:38:53 +080063 if (cpu_id == 0x00) {
64 psci_boot = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8));
65 psci_boot |= 0x20000; /* bit 17 */
66 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8), psci_boot);
67 }
68
Hadi Asyrafia2edf0e2019-10-22 13:39:14 +080069 mmio_write_64(PLAT_CPUID_RELEASE, cpu_id);
Jit Loon Limb24dddf2023-05-17 12:26:11 +080070#endif
Hadi Asyrafi616da772019-06-27 11:34:03 +080071
72 /* release core reset */
Jit Loon Limb24dddf2023-05-17 12:26:11 +080073#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
74 bl31_plat_set_secondary_cpu_entrypoint(cpu_id);
75#else
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +080076 mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
Jit Loon Limb24dddf2023-05-17 12:26:11 +080077 mmio_write_64(PLAT_CPUID_RELEASE, cpu_id);
78#endif
79
Hadi Asyrafi616da772019-06-27 11:34:03 +080080 return PSCI_E_SUCCESS;
81}
82
83/*******************************************************************************
84 * plat handler called when a power domain is about to be turned off. The
85 * target_state encodes the power state that each level should transition to.
86 ******************************************************************************/
87void socfpga_pwr_domain_off(const psci_power_state_t *target_state)
88{
Hadi Asyrafi616da772019-06-27 11:34:03 +080089 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
90 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
91 __func__, i, target_state->pwr_domain_state[i]);
92
Hadi Asyrafi91071fc2019-09-12 15:14:01 +080093 /* Prevent interrupts from spuriously waking up this cpu */
Jit Loon Limb24dddf2023-05-17 12:26:11 +080094#ifdef GICV3_SUPPORT_GIC600
95 gicv3_cpuif_disable(plat_my_core_pos());
96#else
Hadi Asyrafi91071fc2019-09-12 15:14:01 +080097 gicv2_cpuif_disable();
Jit Loon Limb24dddf2023-05-17 12:26:11 +080098#endif
99
Hadi Asyrafi616da772019-06-27 11:34:03 +0800100}
101
102/*******************************************************************************
103 * plat handler called when a power domain is about to be suspended. The
104 * target_state encodes the power state that each level should transition to.
105 ******************************************************************************/
106void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state)
107{
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800108#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
Hadi Asyrafi616da772019-06-27 11:34:03 +0800109 unsigned int cpu_id = plat_my_core_pos();
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800110#endif
Hadi Asyrafi616da772019-06-27 11:34:03 +0800111
112 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
113 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
114 __func__, i, target_state->pwr_domain_state[i]);
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800115
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800116#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
Hadi Asyrafi616da772019-06-27 11:34:03 +0800117 /* assert core reset */
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +0800118 mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800119#endif
Hadi Asyrafi616da772019-06-27 11:34:03 +0800120}
121
122/*******************************************************************************
123 * plat handler called when a power domain has just been powered on after
124 * being turned off earlier. The target_state encodes the low power state that
125 * each level has woken up from.
126 ******************************************************************************/
127void socfpga_pwr_domain_on_finish(const psci_power_state_t *target_state)
128{
129 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
130 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
131 __func__, i, target_state->pwr_domain_state[i]);
132
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800133 /* Enable the gic cpu interface */
134#ifdef GICV3_SUPPORT_GIC600
135 gicv3_rdistif_init(plat_my_core_pos());
136 gicv3_cpuif_enable(plat_my_core_pos());
137#else
Hadi Asyrafi616da772019-06-27 11:34:03 +0800138 /* Program the gic per-cpu distributor or re-distributor interface */
139 gicv2_pcpu_distif_init();
140 gicv2_set_pe_target_mask(plat_my_core_pos());
141
142 /* Enable the gic cpu interface */
143 gicv2_cpuif_enable();
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800144#endif
Hadi Asyrafi616da772019-06-27 11:34:03 +0800145}
146
147/*******************************************************************************
148 * plat handler called when a power domain has just been powered on after
149 * having been suspended earlier. The target_state encodes the low power state
150 * that each level has woken up from.
151 * TODO: At the moment we reuse the on finisher and reinitialize the secure
152 * context. Need to implement a separate suspend finisher.
153 ******************************************************************************/
154void socfpga_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
155{
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800156#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
Hadi Asyrafi616da772019-06-27 11:34:03 +0800157 unsigned int cpu_id = plat_my_core_pos();
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800158#endif
Hadi Asyrafi616da772019-06-27 11:34:03 +0800159
160 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
161 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
162 __func__, i, target_state->pwr_domain_state[i]);
163
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800164#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
Hadi Asyrafi616da772019-06-27 11:34:03 +0800165 /* release core reset */
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +0800166 mmio_clrbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800167#endif
Hadi Asyrafi616da772019-06-27 11:34:03 +0800168}
169
170/*******************************************************************************
171 * plat handlers to shutdown/reboot the system
172 ******************************************************************************/
173static void __dead2 socfpga_system_off(void)
174{
175 wfi();
176 ERROR("System Off: operation not handled.\n");
177 panic();
178}
179
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800180extern uint64_t intel_rsu_update_address;
181
Hadi Asyrafi616da772019-06-27 11:34:03 +0800182static void __dead2 socfpga_system_reset(void)
183{
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +0800184 uint32_t addr_buf[2];
185
186 memcpy(addr_buf, &intel_rsu_update_address,
187 sizeof(intel_rsu_update_address));
Jit Loon Lim86f6fb32023-05-17 12:26:11 +0800188 if (intel_rsu_update_address) {
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +0800189 mailbox_rsu_update(addr_buf);
Jit Loon Lim86f6fb32023-05-17 12:26:11 +0800190 } else {
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800191 mailbox_reset_cold();
Jit Loon Lim86f6fb32023-05-17 12:26:11 +0800192 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800193
194 while (1)
195 wfi();
196}
197
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800198static int socfpga_system_reset2(int is_vendor, int reset_type,
199 u_register_t cookie)
200{
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800201#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
202 mailbox_reset_warm(reset_type);
203#else
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800204 if (cold_reset_for_ecc_dbe()) {
205 mailbox_reset_cold();
206 }
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800207#endif
208
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800209 /* disable cpuif */
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800210#ifdef GICV3_SUPPORT_GIC600
211 gicv3_cpuif_disable(plat_my_core_pos());
212#else
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800213 gicv2_cpuif_disable();
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800214#endif
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800215
216 /* Store magic number */
217 mmio_write_32(L2_RESET_DONE_REG, L2_RESET_DONE_STATUS);
218
219 /* Increase timeout */
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +0800220 mmio_write_32(SOCFPGA_RSTMGR(HDSKTIMEOUT), 0xffffff);
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800221
222 /* Enable handshakes */
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +0800223 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_SET);
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800224
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800225#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800226 /* Reset L2 module */
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +0800227 mmio_setbits_32(SOCFPGA_RSTMGR(COLDMODRST), 0x100);
Jit Loon Limb24dddf2023-05-17 12:26:11 +0800228#endif
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800229
230 while (1)
231 wfi();
232
233 /* Should not reach here */
234 return 0;
235}
236
Hadi Asyrafi616da772019-06-27 11:34:03 +0800237int socfpga_validate_power_state(unsigned int power_state,
238 psci_power_state_t *req_state)
239{
240 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
241
242 return PSCI_E_SUCCESS;
243}
244
245int socfpga_validate_ns_entrypoint(unsigned long ns_entrypoint)
246{
247 VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint);
248 return PSCI_E_SUCCESS;
249}
250
251void socfpga_get_sys_suspend_power_state(psci_power_state_t *req_state)
252{
253 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
254 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
255}
256
257/*******************************************************************************
258 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
259 * platform layer will take care of registering the handlers with PSCI.
260 ******************************************************************************/
261const plat_psci_ops_t socfpga_psci_pm_ops = {
262 .cpu_standby = socfpga_cpu_standby,
263 .pwr_domain_on = socfpga_pwr_domain_on,
264 .pwr_domain_off = socfpga_pwr_domain_off,
265 .pwr_domain_suspend = socfpga_pwr_domain_suspend,
266 .pwr_domain_on_finish = socfpga_pwr_domain_on_finish,
267 .pwr_domain_suspend_finish = socfpga_pwr_domain_suspend_finish,
268 .system_off = socfpga_system_off,
269 .system_reset = socfpga_system_reset,
Hadi Asyrafi5fae68f2019-10-22 14:23:57 +0800270 .system_reset2 = socfpga_system_reset2,
Hadi Asyrafi616da772019-06-27 11:34:03 +0800271 .validate_power_state = socfpga_validate_power_state,
272 .validate_ns_entrypoint = socfpga_validate_ns_entrypoint,
273 .get_sys_suspend_power_state = socfpga_get_sys_suspend_power_state
274};
275
276/*******************************************************************************
277 * Export the platform specific power ops.
278 ******************************************************************************/
279int plat_setup_psci_ops(uintptr_t sec_entrypoint,
280 const struct plat_psci_ops **psci_ops)
281{
282 /* Save warm boot entrypoint.*/
Hadi Asyrafia2edf0e2019-10-22 13:39:14 +0800283 mmio_write_64(PLAT_SEC_ENTRY, sec_entrypoint);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800284 *psci_ops = &socfpga_psci_pm_ops;
Hadi Asyrafia2edf0e2019-10-22 13:39:14 +0800285
Hadi Asyrafi616da772019-06-27 11:34:03 +0800286 return 0;
287}