intel: Refactor reset manager driver
Refactor reset manager into intel common platform directory as it can be
shared by both Stratix 10 and Agilex. Register address and field is now
referred through macros.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a
diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c
index 1ba48ea..d8a6c19 100644
--- a/plat/intel/soc/common/socfpga_psci.c
+++ b/plat/intel/soc/common/socfpga_psci.c
@@ -47,7 +47,7 @@
mmio_write_64(PLAT_CPUID_RELEASE, cpu_id);
/* release core reset */
- mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
+ mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
return PSCI_E_SUCCESS;
}
@@ -78,7 +78,7 @@
__func__, i, target_state->pwr_domain_state[i]);
/* assert core reset */
- mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
+ mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
}
@@ -117,7 +117,7 @@
__func__, i, target_state->pwr_domain_state[i]);
/* release core reset */
- mmio_clrbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
+ mmio_clrbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
}
/*******************************************************************************
@@ -148,13 +148,13 @@
mmio_write_32(L2_RESET_DONE_REG, L2_RESET_DONE_STATUS);
/* Increase timeout */
- mmio_write_32(SOCFPGA_RSTMGR_HDSKTIMEOUT, 0xffffff);
+ mmio_write_32(SOCFPGA_RSTMGR(HDSKTIMEOUT), 0xffffff);
/* Enable handshakes */
- mmio_setbits_32(SOCFPGA_RSTMGR_HDSKEN, SOCFPGA_RSTMGR_HDSKEN_SET);
+ mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_SET);
/* Reset L2 module */
- mmio_setbits_32(SOCFPGA_RSTMGR_COLDMODRST, 0x100);
+ mmio_setbits_32(SOCFPGA_RSTMGR(COLDMODRST), 0x100);
while (1)
wfi();