blob: 84e6b38de523735bc6b7ae24141804603d536365 [file] [log] [blame]
Soby Mathewfeac8fc2015-09-29 15:47:16 +01001/*
Pranav Madhue3173282022-07-27 12:49:24 +05302 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
Soby Mathewfeac8fc2015-09-29 15:47:16 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewfeac8fc2015-09-29 15:47:16 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef CSS_PM_H
8#define CSS_PM_H
Soby Mathewfeac8fc2015-09-29 15:47:16 +01009
10#include <cdefs.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010011#include <stdint.h>
Soby Mathewfeac8fc2015-09-29 15:47:16 +010012
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <lib/psci/psci.h>
14
Pranav Madhue3173282022-07-27 12:49:24 +053015/* SGI used to trigger per-core power down request */
16#define CSS_CPU_PWR_DOWN_REQ_INTR ARM_IRQ_SEC_SGI_7
17
Soby Mathew200fffd2016-10-21 11:34:59 +010018/* Macros to read the CSS power domain state */
19#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0]
20#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1]
Nariman Poushincd956262018-05-01 09:28:40 +010021
22static inline unsigned int css_system_pwr_state(const psci_power_state_t *state)
23{
24#if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL)
25 return state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL];
26#else
27 return 0;
28#endif
29}
Soby Mathew200fffd2016-10-21 11:34:59 +010030
Soby Mathewfeac8fc2015-09-29 15:47:16 +010031int css_pwr_domain_on(u_register_t mpidr);
32void css_pwr_domain_on_finish(const psci_power_state_t *target_state);
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -050033void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state);
Soby Mathewfeac8fc2015-09-29 15:47:16 +010034void css_pwr_domain_off(const psci_power_state_t *target_state);
35void css_pwr_domain_suspend(const psci_power_state_t *target_state);
36void css_pwr_domain_suspend_finish(
37 const psci_power_state_t *target_state);
38void __dead2 css_system_off(void);
39void __dead2 css_system_reset(void);
40void css_cpu_standby(plat_local_state_t cpu_state);
Soby Mathew61e8d0b2015-10-12 17:32:29 +010041void css_get_sys_suspend_power_state(psci_power_state_t *req_state);
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +010042int css_node_hw_state(u_register_t mpidr, unsigned int power_level);
Pranav Madhue3173282022-07-27 12:49:24 +053043void css_setup_cpu_pwr_down_intr(void);
Pranav Madhu9ad55b02022-07-27 13:12:27 +053044int css_reboot_interrupt_handler(uint32_t intr_raw, uint32_t flags,
45 void *handle, void *cookie);
Soby Mathewfeac8fc2015-09-29 15:47:16 +010046
Roberto Vargas2b36b152018-02-12 12:36:17 +000047/*
48 * This mapping array has to be exported by the platform. Each element at
49 * a given index maps that core to an SCMI power domain.
50 */
51extern const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[];
52
Aditya Angadi7f8837b2019-12-31 14:23:53 +053053#define SCMI_DOMAIN_ID_MASK U(0xFFFF)
54#define SCMI_CHANNEL_ID_MASK U(0xFFFF)
55#define SCMI_CHANNEL_ID_SHIFT U(16)
56
57#define SET_SCMI_CHANNEL_ID(n) (((n) & SCMI_CHANNEL_ID_MASK) << \
58 SCMI_CHANNEL_ID_SHIFT)
59#define SET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK)
60#define GET_SCMI_CHANNEL_ID(n) (((n) >> SCMI_CHANNEL_ID_SHIFT) & \
61 SCMI_CHANNEL_ID_MASK)
62#define GET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK)
63
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000064#endif /* CSS_PM_H */