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git01.mediatek.com / filogic / atf / dcf9d92f383f011aa388858a26713ae0d5dd538f / . / plat / arm / board / common / board_css_common.c
blob: 159bf86f41065e29c99136ceb69b2922731a55a8 [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]1/*
Summer Qin9db8f2e2017-04-24 16:49:28 +0100[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]5 */
6#include <arm_def.h>
7#include <plat_arm.h>
8
9/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100[diff] [blame]10 * Table of memory regions for different BL stages to map using the MMU.
11 * This doesn't include Trusted SRAM as arm_setup_page_tables() already
12 * takes care of mapping it.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]13 */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]14#ifdef IMAGE_BL1
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]15const mmap_region_t plat_arm_mmap[] = {
16 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +0100[diff] [blame]17 V2M_MAP_FLASH0_RO,
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]18 V2M_MAP_IOFPGA,
19 CSS_MAP_DEVICE,
20 SOC_CSS_MAP_DEVICE,
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100[diff] [blame]21#if TRUSTED_BOARD_BOOT
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +0100[diff] [blame]22 /* Map DRAM to authenticate NS_BL2U image. */
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100[diff] [blame]23 ARM_MAP_NS_DRAM1,
24#endif
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]25 {0}
26};
27#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]28#ifdef IMAGE_BL2
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]29const mmap_region_t plat_arm_mmap[] = {
30 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +0100[diff] [blame]31 V2M_MAP_FLASH0_RO,
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]32 V2M_MAP_IOFPGA,
33 CSS_MAP_DEVICE,
34 SOC_CSS_MAP_DEVICE,
35 ARM_MAP_NS_DRAM1,
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +0100[diff] [blame]36#ifdef SPD_tspd
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]37 ARM_MAP_TSP_SEC_MEM,
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +0100[diff] [blame]38#endif
Summer Qin9db8f2e2017-04-24 16:49:28 +0100[diff] [blame]39#ifdef SPD_opteed
Soby Mathew874fc9e2017-09-01 13:43:50 +0100[diff] [blame]40 ARM_MAP_OPTEE_CORE_MEM,
Summer Qin9db8f2e2017-04-24 16:49:28 +0100[diff] [blame]41 ARM_OPTEE_PAGEABLE_LOAD_MEM,
42#endif
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]43 {0}
44};
45#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]46#ifdef IMAGE_BL2U
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100[diff] [blame]47const mmap_region_t plat_arm_mmap[] = {
48 ARM_MAP_SHARED_RAM,
49 CSS_MAP_DEVICE,
50 SOC_CSS_MAP_DEVICE,
51 {0}
52};
53#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]54#ifdef IMAGE_BL31
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]55const mmap_region_t plat_arm_mmap[] = {
56 ARM_MAP_SHARED_RAM,
57 V2M_MAP_IOFPGA,
58 CSS_MAP_DEVICE,
59 SOC_CSS_MAP_DEVICE,
60 {0}
61};
62#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]63#ifdef IMAGE_BL32
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]64const mmap_region_t plat_arm_mmap[] = {
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000[diff] [blame]65#ifdef AARCH32
66 ARM_MAP_SHARED_RAM,
67#endif
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]68 V2M_MAP_IOFPGA,
69 CSS_MAP_DEVICE,
70 SOC_CSS_MAP_DEVICE,
71 {0}
72};
73#endif
74
75ARM_CASSERT_MMAP