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Paul Beesleyf3653a62019-05-22 11:22:44 +01001Xilinx Zynq UltraScale+ MPSoC
2=============================
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Dan Handley610e7e12018-03-01 18:44:00 +00004Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Xilinx Zynq
Douglas Raillardd7c21b72017-06-28 15:23:03 +01005UltraScale + MPSoC.
Dan Handley610e7e12018-03-01 18:44:00 +00006The platform only uses the runtime part of TF-A as ZynqMP already has a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01007BootROM (BL1) and FSBL (BL2).
8
Dan Handley610e7e12018-03-01 18:44:00 +00009BL31 is TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010010BL32 is an optional Secure Payload.
11BL33 is the non-secure world software (U-Boot, Linux etc).
12
13To build:
14
15.. code:: bash
16
Venkatesh Yadav Abbarapu476336b2022-04-11 09:13:17 +053017 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31
Douglas Raillardd7c21b72017-06-28 15:23:03 +010018
19To build bl32 TSP you have to rebuild bl31 too:
20
21.. code:: bash
22
Venkatesh Yadav Abbarapu476336b2022-04-11 09:13:17 +053023 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd RESET_TO_BL31=1 bl31 bl32
Douglas Raillardd7c21b72017-06-28 15:23:03 +010024
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -070025To build TF-A for JTAG DCC console:
26
27.. code:: bash
28
29 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 ZYNQMP_CONSOLE=dcc
30
Douglas Raillardd7c21b72017-06-28 15:23:03 +010031ZynqMP platform specific build options
Paul Beesleyf3653a62019-05-22 11:22:44 +010032--------------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010033
Akshay Belsareec0afc82023-02-27 12:04:26 +053034- ``XILINX_OF_BOARD_DTB_ADDR`` : Specifies the base address of Device tree.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010035- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary.
36- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary.
37- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary.
38- ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary.
39
40- ``ZYNQMP_CONSOLE``: Select the console driver. Options:
41
42 - ``cadence``, ``cadence0``: Cadence UART 0
43 - ``cadence1`` : Cadence UART 1
44
Akshay Belsare69c6a592023-02-15 10:49:52 +053045ZynqMP Debug behavior
46---------------------
47
48With DEBUG=1, TF-A for ZynqMP uses DDR memory range instead of OCM memory range
49due to size constraints.
50For DEBUG=1 configuration for ZynqMP the BL31_BASE is set to the DDR location
Akshay Belsareec0afc82023-02-27 12:04:26 +053051of 0x1000 and BL31_LIMIT is set to DDR location of 0x7FFFF. By default the
52above memory range will NOT be reserved in device tree.
53
54To reserve the above memory range in device tree, the device tree base address
55must be provided during build as,
56
57make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \
58 XILINX_OF_BOARD_DTB_ADDR=<DTB address> bl31
59
60The default DTB base address for ZynqMP platform is 0x100000. This default value
61is not set in the code and to use this default address, user still needs to
62provide it through the build command as above.
Akshay Belsare69c6a592023-02-15 10:49:52 +053063
64If the user wants to move the bl31 to a different DDR location, user can provide
Akshay Belsareec0afc82023-02-27 12:04:26 +053065the DDR address location using the build time parameters ZYNQMP_ATF_MEM_BASE and
66ZYNQMP_ATF_MEM_SIZE.
67
68The DDR address must be reserved in the DTB by the user, either by manually
69adding the reserved memory node, in the device tree, with the required address
70range OR let TF-A modify the device tree on the run.
71
72To let TF-A access and modify the device tree, the DTB address must be provided
73to the build command as follows,
Akshay Belsare69c6a592023-02-15 10:49:52 +053074
75make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \
Akshay Belsareec0afc82023-02-27 12:04:26 +053076 ZYNQMP_ATF_MEM_BASE=<DDR address> ZYNQMP_ATF_MEM_SIZE=<size> \
77 XILINX_OF_BOARD_DTB_ADDR=<DTB address> bl31
Akshay Belsare69c6a592023-02-15 10:49:52 +053078
Belsare, Akshay03f37112023-03-06 15:08:54 +053079DDR Address Range Usage
80-----------------------
81
82When FSBL runs on RPU and TF-A is to be placed in DDR address range,
83then the user needs to make sure that the DDR address is beyond 256KB.
84In the RPU view, the first 256 KB is TCM memory.
85
86For this use case, with the minimum base address in DDR for TF-A,
87the build command example is;
88
89make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \
90 ZYNQMP_ATF_MEM_BASE=0x40000 ZYNQMP_ATF_MEM_SIZE=<size>
Akshay Belsare69c6a592023-02-15 10:49:52 +053091
Akshay Belsare32d5c902023-04-06 16:21:06 +053092Configurable Stack Size
93-----------------------
94
95The stack size in TF-A for ZynqMP platform is configurable.
96The custom package can define the desired stack size as per the requirement in
97the make file as follows,
98
99PLATFORM_STACK_SIZE := <value>
100$(eval $(call add_define,PLATFORM_STACK_SIZE))
101
Dan Handley610e7e12018-03-01 18:44:00 +0000102FSBL->TF-A Parameter Passing
Paul Beesleyf3653a62019-05-22 11:22:44 +0100103----------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100104
Dan Handley610e7e12018-03-01 18:44:00 +0000105The FSBL populates a data structure with image information for TF-A. TF-A uses
106that data to hand off to the loaded images. The address of the handoff data
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100107structure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The
Dan Handley610e7e12018-03-01 18:44:00 +0000108register is free to be used by other software once TF-A has brought up
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100109further firmware images.
110
111Power Domain Tree
Paul Beesleyf3653a62019-05-22 11:22:44 +0100112-----------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100113
Dan Handley610e7e12018-03-01 18:44:00 +0000114The following power domain tree represents the power domain model used by TF-A
115for ZynqMP:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100116
117::
118
119 +-+
120 |0|
121 +-+
122 +-------+---+---+-------+
123 | | | |
124 | | | |
125 v v v v
126 +-+ +-+ +-+ +-+
127 |0| |1| |2| |3|
128 +-+ +-+ +-+ +-+
129
130The 4 leaf power domains represent the individual A53 cores, while resources
131common to the cluster are grouped in the power domain on the top.
Amit Nagalf7ecba32023-02-15 18:43:55 +0530132
133CUSTOM SIP service support
134--------------------------
135
136- Dedicated SMC FID ZYNQMP_SIP_SVC_CUSTOM(0x82002000)(32-bit)/
137 (0xC2002000)(64-bit) to be used by a custom package for
138 providing CUSTOM SIP service.
139
140- by default platform provides bare minimum definition for
141 custom_smc_handler in this service.
142
143- to use this service, custom package should implement their
144 smc handler with the name custom_smc_handler. once custom package is
145 included in TF-A build, their definition of custom_smc_handler is
146 enabled.
147
148Custom package makefile fragment inclusion in TF-A build
149--------------------------------------------------------
150
151- custom package is not directly part of TF-A source.
152
153- <CUSTOM_PKG_PATH> is the location at which user clones a
154 custom package locally.
155
156- custom package needs to implement makefile fragment named
157 custom_pkg.mk so as to get included in TF-A build.
158
159- custom_pkg.mk specify all the rules to include custom package
160 specific header files, dependent libs, source files that are
161 supposed to be included in TF-A build.
162
163- when <CUSTOM_PKG_PATH> is specified in TF-A build command,
164 custom_pkg.mk is included from <CUSTOM_PKG_PATH> in TF-A build.
165
166- TF-A build command:
167 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1
168 bl31 CUSTOM_PKG_PATH=<...>