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Paul Beesleyf3653a62019-05-22 11:22:44 +01001Xilinx Zynq UltraScale+ MPSoC
2=============================
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Dan Handley610e7e12018-03-01 18:44:00 +00004Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Xilinx Zynq
Douglas Raillardd7c21b72017-06-28 15:23:03 +01005UltraScale + MPSoC.
Dan Handley610e7e12018-03-01 18:44:00 +00006The platform only uses the runtime part of TF-A as ZynqMP already has a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01007BootROM (BL1) and FSBL (BL2).
8
Dan Handley610e7e12018-03-01 18:44:00 +00009BL31 is TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010010BL32 is an optional Secure Payload.
11BL33 is the non-secure world software (U-Boot, Linux etc).
12
13To build:
14
15.. code:: bash
16
Antonio Nino Diaz012c8bf2018-09-24 17:16:52 +010017 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31
Douglas Raillardd7c21b72017-06-28 15:23:03 +010018
19To build bl32 TSP you have to rebuild bl31 too:
20
21.. code:: bash
22
Antonio Nino Diaz012c8bf2018-09-24 17:16:52 +010023 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32
Douglas Raillardd7c21b72017-06-28 15:23:03 +010024
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -070025To build TF-A for JTAG DCC console:
26
27.. code:: bash
28
29 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 ZYNQMP_CONSOLE=dcc
30
Douglas Raillardd7c21b72017-06-28 15:23:03 +010031ZynqMP platform specific build options
Paul Beesleyf3653a62019-05-22 11:22:44 +010032--------------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010033
34- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary.
35- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary.
36- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary.
37- ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary.
38
39- ``ZYNQMP_CONSOLE``: Select the console driver. Options:
40
41 - ``cadence``, ``cadence0``: Cadence UART 0
42 - ``cadence1`` : Cadence UART 1
43
Dan Handley610e7e12018-03-01 18:44:00 +000044FSBL->TF-A Parameter Passing
Paul Beesleyf3653a62019-05-22 11:22:44 +010045----------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010046
Dan Handley610e7e12018-03-01 18:44:00 +000047The FSBL populates a data structure with image information for TF-A. TF-A uses
48that data to hand off to the loaded images. The address of the handoff data
Douglas Raillardd7c21b72017-06-28 15:23:03 +010049structure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The
Dan Handley610e7e12018-03-01 18:44:00 +000050register is free to be used by other software once TF-A has brought up
Douglas Raillardd7c21b72017-06-28 15:23:03 +010051further firmware images.
52
53Power Domain Tree
Paul Beesleyf3653a62019-05-22 11:22:44 +010054-----------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010055
Dan Handley610e7e12018-03-01 18:44:00 +000056The following power domain tree represents the power domain model used by TF-A
57for ZynqMP:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010058
59::
60
61 +-+
62 |0|
63 +-+
64 +-------+---+---+-------+
65 | | | |
66 | | | |
67 v v v v
68 +-+ +-+ +-+ +-+
69 |0| |1| |2| |3|
70 +-+ +-+ +-+ +-+
71
72The 4 leaf power domains represent the individual A53 cores, while resources
73common to the cluster are grouped in the power domain on the top.