| Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame^] | 1 | ARM Trusted Firmware for Xilinx Zynq UltraScale+ MPSoC |
| 2 | ====================================================== |
| 3 | |
| 4 | ARM Trusted Firmware implements the EL3 firmware layer for Xilinx Zynq |
| 5 | UltraScale + MPSoC. |
| 6 | The platform only uses the runtime part of ATF as ZynqMP already has a |
| 7 | BootROM (BL1) and FSBL (BL2). |
| 8 | |
| 9 | BL31 is ATF. |
| 10 | BL32 is an optional Secure Payload. |
| 11 | BL33 is the non-secure world software (U-Boot, Linux etc). |
| 12 | |
| 13 | To build: |
| 14 | |
| 15 | .. code:: bash |
| 16 | |
| 17 | make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31 |
| 18 | |
| 19 | To build bl32 TSP you have to rebuild bl31 too: |
| 20 | |
| 21 | .. code:: bash |
| 22 | |
| 23 | make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32 |
| 24 | |
| 25 | ZynqMP platform specific build options |
| 26 | ====================================== |
| 27 | |
| 28 | - ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary. |
| 29 | - ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary. |
| 30 | - ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary. |
| 31 | - ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary. |
| 32 | |
| 33 | - ``ZYNQMP_CONSOLE``: Select the console driver. Options: |
| 34 | |
| 35 | - ``cadence``, ``cadence0``: Cadence UART 0 |
| 36 | - ``cadence1`` : Cadence UART 1 |
| 37 | |
| 38 | FSBL->ATF Parameter Passing |
| 39 | =========================== |
| 40 | |
| 41 | The FSBL populates a data structure with image information for the ATF. The ATF |
| 42 | uses that data to hand off to the loaded images. The address of the handoff data |
| 43 | structure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The |
| 44 | register is free to be used by other software once the ATF is bringing up |
| 45 | further firmware images. |
| 46 | |
| 47 | Power Domain Tree |
| 48 | ================= |
| 49 | |
| 50 | The following power domain tree represents the power domain model used by the |
| 51 | ATF for ZynqMP: |
| 52 | |
| 53 | :: |
| 54 | |
| 55 | +-+ |
| 56 | |0| |
| 57 | +-+ |
| 58 | +-------+---+---+-------+ |
| 59 | | | | | |
| 60 | | | | | |
| 61 | v v v v |
| 62 | +-+ +-+ +-+ +-+ |
| 63 | |0| |1| |2| |3| |
| 64 | +-+ +-+ +-+ +-+ |
| 65 | |
| 66 | The 4 leaf power domains represent the individual A53 cores, while resources |
| 67 | common to the cluster are grouped in the power domain on the top. |