Juan Castillo | 0c70c57 | 2014-08-12 13:04:43 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __FVP_DEF_H__ |
| 32 | #define __FVP_DEF_H__ |
| 33 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 34 | #include <arm_def.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 35 | |
Juan Castillo | e33ee5f | 2014-12-19 09:51:00 +0000 | [diff] [blame] | 36 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 37 | #define FVP_MAX_CPUS_PER_CLUSTER 4 |
| 38 | |
| 39 | #define FVP_PRIMARY_CPU 0x0 |
Juan Castillo | 0c70c57 | 2014-08-12 13:04:43 +0100 | [diff] [blame] | 40 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 41 | /******************************************************************************* |
| 42 | * FVP memory map related constants |
| 43 | ******************************************************************************/ |
| 44 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 45 | #define FLASH1_BASE 0x0c000000 |
| 46 | #define FLASH1_SIZE 0x04000000 |
Juan Castillo | 0c70c57 | 2014-08-12 13:04:43 +0100 | [diff] [blame] | 47 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 48 | #define PSRAM_BASE 0x14000000 |
| 49 | #define PSRAM_SIZE 0x04000000 |
Juan Castillo | 42a617d | 2014-09-24 10:00:06 +0100 | [diff] [blame] | 50 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 51 | #define VRAM_BASE 0x18000000 |
| 52 | #define VRAM_SIZE 0x02000000 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 53 | |
| 54 | /* Aggregate of all devices in the first GB */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 55 | #define DEVICE0_BASE 0x20000000 |
| 56 | #define DEVICE0_SIZE 0x0c200000 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 57 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 58 | #define DEVICE1_BASE 0x2f000000 |
| 59 | #define DEVICE1_SIZE 0x200000 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 60 | |
Juan Castillo | 31a68f0 | 2015-04-14 12:49:03 +0100 | [diff] [blame] | 61 | /* Devices in the second GB */ |
| 62 | #define DEVICE2_BASE 0x7fe00000 |
| 63 | #define DEVICE2_SIZE 0x00200000 |
| 64 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 65 | #define NSRAM_BASE 0x2e000000 |
| 66 | #define NSRAM_SIZE 0x10000 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 67 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 68 | #define PCIE_EXP_BASE 0x40000000 |
| 69 | #define TZRNG_BASE 0x7fe60000 |
| 70 | #define TZNVCTR_BASE 0x7fe70000 |
Juan Castillo | 31a68f0 | 2015-04-14 12:49:03 +0100 | [diff] [blame] | 71 | |
| 72 | /* Keys */ |
| 73 | #define SOC_KEYS_BASE 0x7fe80000 |
| 74 | #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) |
| 75 | #define TZ_PUB_KEY_HASH_SIZE 32 |
| 76 | #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) |
| 77 | #define HU_KEY_SIZE 16 |
| 78 | #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) |
| 79 | #define END_KEY_SIZE 32 |
Juan Castillo | f3e0218 | 2014-12-19 09:28:30 +0000 | [diff] [blame] | 80 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 81 | /* Constants to distinguish FVP type */ |
| 82 | #define HBI_BASE_FVP 0x020 |
| 83 | #define REV_BASE_FVP_V0 0x0 |
Juan Castillo | f3e0218 | 2014-12-19 09:28:30 +0000 | [diff] [blame] | 84 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 85 | #define HBI_FOUNDATION_FVP 0x010 |
| 86 | #define REV_FOUNDATION_FVP_V2_0 0x0 |
| 87 | #define REV_FOUNDATION_FVP_V2_1 0x1 |
| 88 | #define REV_FOUNDATION_FVP_v9_1 0x2 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 89 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 90 | #define BLD_GIC_VE_MMAP 0x0 |
| 91 | #define BLD_GIC_A53A57_MMAP 0x1 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 92 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 93 | #define ARCH_MODEL 0x1 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 94 | |
| 95 | /* FVP Power controller base address*/ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 96 | #define PWRC_BASE 0x1c100000 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 97 | |
Ryan Harkin | f96fc8f | 2015-03-17 14:54:01 +0000 | [diff] [blame] | 98 | /* FVP SP804 timer frequency is 35 MHz*/ |
| 99 | #define SP804_TIMER_CLKMULT 35 |
| 100 | #define SP804_TIMER_CLKDIV 1 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 101 | |
| 102 | /******************************************************************************* |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 103 | * GIC-400 & interrupt handling related constants |
| 104 | ******************************************************************************/ |
| 105 | /* VE compatible GIC memory map */ |
| 106 | #define VE_GICD_BASE 0x2c001000 |
| 107 | #define VE_GICC_BASE 0x2c002000 |
| 108 | #define VE_GICH_BASE 0x2c004000 |
| 109 | #define VE_GICV_BASE 0x2c006000 |
| 110 | |
| 111 | /* Base FVP compatible GIC memory map */ |
| 112 | #define BASE_GICD_BASE 0x2f000000 |
| 113 | #define BASE_GICR_BASE 0x2f100000 |
| 114 | #define BASE_GICC_BASE 0x2c000000 |
| 115 | #define BASE_GICH_BASE 0x2c010000 |
| 116 | #define BASE_GICV_BASE 0x2c02f000 |
| 117 | |
| 118 | #define IRQ_TZ_WDOG 56 |
Soby Mathew | 69817f7 | 2014-07-14 15:43:21 +0100 | [diff] [blame] | 119 | |
Soby Mathew | 69817f7 | 2014-07-14 15:43:21 +0100 | [diff] [blame] | 120 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 121 | /******************************************************************************* |
| 122 | * TrustZone address space controller related constants |
| 123 | ******************************************************************************/ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 124 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 125 | /* NSAIDs used by devices in TZC filter 0 on FVP */ |
| 126 | #define FVP_NSAID_DEFAULT 0 |
| 127 | #define FVP_NSAID_PCI 1 |
| 128 | #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ |
| 129 | #define FVP_NSAID_AP 9 /* Application Processors */ |
| 130 | #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ |
| 131 | |
| 132 | /* NSAIDs used by devices in TZC filter 2 on FVP */ |
| 133 | #define FVP_NSAID_HDLCD0 2 |
| 134 | #define FVP_NSAID_CLCD 7 |
| 135 | |
Juan Castillo | 48e84b3 | 2014-08-12 13:51:51 +0100 | [diff] [blame] | 136 | /******************************************************************************* |
| 137 | * Shared Data |
| 138 | ******************************************************************************/ |
| 139 | |
| 140 | /* Entrypoint mailboxes */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 141 | #define MBOX_BASE ARM_SHARED_RAM_BASE |
Juan Castillo | 48e84b3 | 2014-08-12 13:51:51 +0100 | [diff] [blame] | 142 | |
Juan Castillo | 48e84b3 | 2014-08-12 13:51:51 +0100 | [diff] [blame] | 143 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 144 | #endif /* __FVP_DEF_H__ */ |