Migrate FVP port to use common code
Major update to the FVP platform port to use the common platform code
in (include/)plat/arm/* and (include/)plat/common/*. This mainly
consists of removing duplicated code but also introduces some small
behavioural changes where there was unnecessary variation between the
FVP and Juno ports. See earlier commit titled `Add common ARM and CSS
platform code` for details.
Also add support for Foundation FVP version 9.1 during FVP config
setup to prevent a warning being emitted in the console.
Change-Id: I254ca854987642ce09d1b924c9fd410a6e13e3bc
diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h
index a2f2da8..47723c7 100644
--- a/plat/fvp/fvp_def.h
+++ b/plat/fvp/fvp_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -31,215 +31,60 @@
#ifndef __FVP_DEF_H__
#define __FVP_DEF_H__
-/* Firmware Image Package */
-#define FIP_IMAGE_NAME "fip.bin"
-#define FVP_PRIMARY_CPU 0x0
+#include <arm_def.h>
-/* Memory location options for TSP */
-#define FVP_TRUSTED_SRAM_ID 0
-#define FVP_TRUSTED_DRAM_ID 1
-#define FVP_DRAM_ID 2
-/*
- * Some of the definitions in this file use the 'ull' suffix in order to avoid
- * subtle integer overflow errors due to implicit integer type promotion when
- * working with 32-bit values.
- *
- * The TSP linker script includes some of these definitions to define the BL3-2
- * memory map, but the GNU LD does not support the 'ull' suffix, causing the
- * build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x)
- * will add the 'ull' suffix only when the macro __LINKER__ is not defined
- * (__LINKER__ is defined in the command line to preprocess the linker script).
- * Constants in the linker script will not have the 'ull' suffix, but this is
- * not a problem since the linker evaluates all constant expressions to 64 bit
- * (assuming the target architecture is 64 bit).
- */
-#ifndef __LINKER__
- #define MAKE_ULL(x) x##ull
-#else
- #define MAKE_ULL(x) x
-#endif
+#define FVP_MAX_CPUS_PER_CLUSTER 4
+
+#define FVP_PRIMARY_CPU 0x0
/*******************************************************************************
* FVP memory map related constants
******************************************************************************/
-#define FVP_TRUSTED_ROM_BASE 0x00000000
-#define FVP_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
+#define FLASH1_BASE 0x0c000000
+#define FLASH1_SIZE 0x04000000
-/* The first 4KB of Trusted SRAM are used as shared memory */
-#define FVP_SHARED_MEM_BASE 0x04000000
-#define FVP_SHARED_MEM_SIZE 0x00001000 /* 4 KB */
+#define PSRAM_BASE 0x14000000
+#define PSRAM_SIZE 0x04000000
-/* The remaining Trusted SRAM is used to load the BL images */
-#define FVP_TRUSTED_SRAM_BASE 0x04001000
-#define FVP_TRUSTED_SRAM_SIZE 0x0003F000 /* 252 KB */
-
-#define FVP_TRUSTED_DRAM_BASE 0x06000000
-#define FVP_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
-
-#define FLASH0_BASE 0x08000000
-#define FLASH0_SIZE 0x04000000
-
-#define FLASH1_BASE 0x0c000000
-#define FLASH1_SIZE 0x04000000
-
-#define PSRAM_BASE 0x14000000
-#define PSRAM_SIZE 0x04000000
-
-#define VRAM_BASE 0x18000000
-#define VRAM_SIZE 0x02000000
+#define VRAM_BASE 0x18000000
+#define VRAM_SIZE 0x02000000
/* Aggregate of all devices in the first GB */
-#define DEVICE0_BASE 0x1a000000
-#define DEVICE0_SIZE 0x12200000
+#define DEVICE0_BASE 0x20000000
+#define DEVICE0_SIZE 0x0c200000
-#define DEVICE1_BASE 0x2f000000
-#define DEVICE1_SIZE 0x200000
+#define DEVICE1_BASE 0x2f000000
+#define DEVICE1_SIZE 0x200000
-#define NSRAM_BASE 0x2e000000
-#define NSRAM_SIZE 0x10000
+#define NSRAM_BASE 0x2e000000
+#define NSRAM_SIZE 0x10000
-#define DRAM1_BASE MAKE_ULL(0x80000000)
-#define DRAM1_SIZE MAKE_ULL(0x80000000)
-#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1)
+#define PCIE_EXP_BASE 0x40000000
+#define TZRNG_BASE 0x7fe60000
+#define TZNVCTR_BASE 0x7fe70000
+#define TZROOTKEY_BASE 0x7fe80000
-/* Define the top 16 MB of DRAM1 as secure */
-#define DRAM1_SEC_SIZE MAKE_ULL(0x01000000)
-#define DRAM1_SEC_BASE (DRAM1_BASE + DRAM1_SIZE - DRAM1_SEC_SIZE)
-#define DRAM1_SEC_END (DRAM1_SEC_BASE + DRAM1_SEC_SIZE - 1)
+/* Constants to distinguish FVP type */
+#define HBI_BASE_FVP 0x020
+#define REV_BASE_FVP_V0 0x0
-#define DRAM1_NS_BASE DRAM1_BASE
-#define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_SEC_SIZE)
-#define DRAM1_NS_END (DRAM1_NS_BASE + DRAM1_NS_SIZE - 1)
+#define HBI_FOUNDATION_FVP 0x010
+#define REV_FOUNDATION_FVP_V2_0 0x0
+#define REV_FOUNDATION_FVP_V2_1 0x1
+#define REV_FOUNDATION_FVP_v9_1 0x2
-#define DRAM_BASE DRAM1_BASE
-#define DRAM_SIZE DRAM1_SIZE
+#define BLD_GIC_VE_MMAP 0x0
+#define BLD_GIC_A53A57_MMAP 0x1
-#define DRAM2_BASE MAKE_ULL(0x880000000)
-#define DRAM2_SIZE MAKE_ULL(0x780000000)
-#define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1)
-
-#define PCIE_EXP_BASE 0x40000000
-#define TZRNG_BASE 0x7fe60000
-#define TZNVCTR_BASE 0x7fe70000
-#define TZROOTKEY_BASE 0x7fe80000
-
-/* Memory mapped Generic timer interfaces */
-#define SYS_CNTCTL_BASE 0x2a430000
-#define SYS_CNTREAD_BASE 0x2a800000
-#define SYS_TIMCTL_BASE 0x2a810000
-
-/* V2M motherboard system registers & offsets */
-#define VE_SYSREGS_BASE 0x1c010000
-#define V2M_SYS_ID 0x0
-#define V2M_SYS_SWITCH 0x4
-#define V2M_SYS_LED 0x8
-#define V2M_SYS_CFGDATA 0xa0
-#define V2M_SYS_CFGCTRL 0xa4
-#define V2M_SYS_CFGSTATUS 0xa8
-
-#define CFGCTRL_START (1 << 31)
-#define CFGCTRL_RW (1 << 30)
-#define CFGCTRL_FUNC_SHIFT 20
-#define CFGCTRL_FUNC(fn) (fn << CFGCTRL_FUNC_SHIFT)
-#define FUNC_CLK_GEN 0x01
-#define FUNC_TEMP 0x04
-#define FUNC_DB_RESET 0x05
-#define FUNC_SCC_CFG 0x06
-#define FUNC_SHUTDOWN 0x08
-#define FUNC_REBOOT 0x09
-
-/*
- * The number of regions like RO(code), coherent and data required by
- * different BL stages which need to be mapped in the MMU.
- */
-#if USE_COHERENT_MEM
-#define FVP_BL_REGIONS 3
-#else
-#define FVP_BL_REGIONS 2
-#endif
-
-/*
- * The FVP_MAX_MMAP_REGIONS depend on the number of entries in fvp_mmap[]
- * defined for each BL stage in fvp_common.c.
- */
-#if IMAGE_BL1
-#define FVP_MMAP_ENTRIES 5
-#endif
-#if IMAGE_BL2
-#define FVP_MMAP_ENTRIES 7
-#endif
-#if IMAGE_BL31
-#define FVP_MMAP_ENTRIES 4
-#endif
-#if IMAGE_BL32
-#define FVP_MMAP_ENTRIES 3
-#endif
-
-/* Load address of BL33 in the FVP port */
-#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
-
-/* Special value used to verify platform parameters from BL2 to BL3-1 */
-#define FVP_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
-
-/*
- * V2M sysled bit definitions. The values written to this
- * register are defined in arch.h & runtime_svc.h. Only
- * used by the primary cpu to diagnose any cold boot issues.
- *
- * SYS_LED[0] - Security state (S=0/NS=1)
- * SYS_LED[2:1] - Exception Level (EL3-EL0)
- * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
- *
- */
-#define SYS_LED_SS_SHIFT 0x0
-#define SYS_LED_EL_SHIFT 0x1
-#define SYS_LED_EC_SHIFT 0x3
-
-#define SYS_LED_SS_MASK 0x1
-#define SYS_LED_EL_MASK 0x3
-#define SYS_LED_EC_MASK 0x1f
-
-/* V2M sysid register bits */
-#define SYS_ID_REV_SHIFT 28
-#define SYS_ID_HBI_SHIFT 16
-#define SYS_ID_BLD_SHIFT 12
-#define SYS_ID_ARCH_SHIFT 8
-#define SYS_ID_FPGA_SHIFT 0
-
-#define SYS_ID_REV_MASK 0xf
-#define SYS_ID_HBI_MASK 0xfff
-#define SYS_ID_BLD_MASK 0xf
-#define SYS_ID_ARCH_MASK 0xf
-#define SYS_ID_FPGA_MASK 0xff
-
-#define SYS_ID_BLD_LENGTH 4
-
-#define HBI_FVP_BASE 0x020
-#define REV_FVP_BASE_V0 0x0
-
-#define HBI_FOUNDATION 0x010
-#define REV_FOUNDATION_V2_0 0x0
-#define REV_FOUNDATION_V2_1 0x1
-
-#define BLD_GIC_VE_MMAP 0x0
-#define BLD_GIC_A53A57_MMAP 0x1
-
-#define ARCH_MODEL 0x1
+#define ARCH_MODEL 0x1
/* FVP Power controller base address*/
-#define PWRC_BASE 0x1c100000
+#define PWRC_BASE 0x1c100000
/*******************************************************************************
- * CCI-400 related constants
- ******************************************************************************/
-#define CCI400_BASE 0x2c090000
-#define CCI400_CLUSTER0_SL_IFACE_IX 3
-#define CCI400_CLUSTER1_SL_IFACE_IX 4
-
-/*******************************************************************************
* GIC-400 & interrupt handling related constants
******************************************************************************/
/* VE compatible GIC memory map */
@@ -256,39 +101,11 @@
#define BASE_GICV_BASE 0x2c02f000
#define IRQ_TZ_WDOG 56
-#define IRQ_SEC_PHY_TIMER 29
-#define IRQ_SEC_SGI_0 8
-#define IRQ_SEC_SGI_1 9
-#define IRQ_SEC_SGI_2 10
-#define IRQ_SEC_SGI_3 11
-#define IRQ_SEC_SGI_4 12
-#define IRQ_SEC_SGI_5 13
-#define IRQ_SEC_SGI_6 14
-#define IRQ_SEC_SGI_7 15
-
-/*******************************************************************************
- * PL011 related constants
- ******************************************************************************/
-#define PL011_UART0_BASE 0x1c090000
-#define PL011_UART1_BASE 0x1c0a0000
-#define PL011_UART2_BASE 0x1c0b0000
-#define PL011_UART3_BASE 0x1c0c0000
-
-#define PL011_BAUDRATE 115200
-#define PL011_UART0_CLK_IN_HZ 24000000
-#define PL011_UART1_CLK_IN_HZ 24000000
-#define PL011_UART2_CLK_IN_HZ 24000000
-#define PL011_UART3_CLK_IN_HZ 24000000
/*******************************************************************************
* TrustZone address space controller related constants
******************************************************************************/
-#define TZC400_BASE 0x2a4a0000
-
-/*
- * The NSAIDs for this platform as used to program the TZC400.
- */
/* NSAIDs used by devices in TZC filter 0 on FVP */
#define FVP_NSAID_DEFAULT 0
@@ -306,10 +123,8 @@
******************************************************************************/
/* Entrypoint mailboxes */
-#define MBOX_BASE FVP_SHARED_MEM_BASE
-#define MBOX_SIZE 0x200
+#define MBOX_BASE ARM_SHARED_RAM_BASE
+#define MBOX_SIZE 0x200
-/* Base address where parameters to BL31 are stored */
-#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE)
#endif /* __FVP_DEF_H__ */