Juan Castillo | 0c70c57 | 2014-08-12 13:04:43 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __FVP_DEF_H__ |
| 32 | #define __FVP_DEF_H__ |
| 33 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 34 | /* Firmware Image Package */ |
| 35 | #define FIP_IMAGE_NAME "fip.bin" |
Juan Castillo | b3dbeb0 | 2014-07-16 15:53:43 +0100 | [diff] [blame] | 36 | #define FVP_PRIMARY_CPU 0x0 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 37 | |
Juan Castillo | 0c70c57 | 2014-08-12 13:04:43 +0100 | [diff] [blame] | 38 | /* Memory location options for Shared data and TSP in FVP */ |
| 39 | #define FVP_IN_TRUSTED_SRAM 0 |
| 40 | #define FVP_IN_TRUSTED_DRAM 1 |
| 41 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 42 | /******************************************************************************* |
| 43 | * FVP memory map related constants |
| 44 | ******************************************************************************/ |
| 45 | |
Juan Castillo | 0c70c57 | 2014-08-12 13:04:43 +0100 | [diff] [blame] | 46 | #define FVP_TRUSTED_ROM_BASE 0x00000000 |
| 47 | #define FVP_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ |
| 48 | |
| 49 | #define FVP_TRUSTED_SRAM_BASE 0x04000000 |
| 50 | #define FVP_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ |
| 51 | |
| 52 | #define FVP_TRUSTED_DRAM_BASE 0x06000000 |
| 53 | #define FVP_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ |
| 54 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 55 | #define FLASH0_BASE 0x08000000 |
Juan Castillo | 0c70c57 | 2014-08-12 13:04:43 +0100 | [diff] [blame] | 56 | #define FLASH0_SIZE 0x04000000 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 57 | |
| 58 | #define FLASH1_BASE 0x0c000000 |
| 59 | #define FLASH1_SIZE 0x04000000 |
| 60 | |
| 61 | #define PSRAM_BASE 0x14000000 |
| 62 | #define PSRAM_SIZE 0x04000000 |
| 63 | |
| 64 | #define VRAM_BASE 0x18000000 |
| 65 | #define VRAM_SIZE 0x02000000 |
| 66 | |
| 67 | /* Aggregate of all devices in the first GB */ |
| 68 | #define DEVICE0_BASE 0x1a000000 |
| 69 | #define DEVICE0_SIZE 0x12200000 |
| 70 | |
| 71 | #define DEVICE1_BASE 0x2f000000 |
| 72 | #define DEVICE1_SIZE 0x200000 |
| 73 | |
| 74 | #define NSRAM_BASE 0x2e000000 |
| 75 | #define NSRAM_SIZE 0x10000 |
| 76 | |
Juan Castillo | 48e84b3 | 2014-08-12 13:51:51 +0100 | [diff] [blame^] | 77 | /* 4KB shared memory */ |
| 78 | #define FVP_SHARED_RAM_SIZE 0x1000 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 79 | |
Juan Castillo | 48e84b3 | 2014-08-12 13:51:51 +0100 | [diff] [blame^] | 80 | /* Location of shared memory */ |
| 81 | #if (FVP_SHARED_DATA_LOCATION_ID == FVP_IN_TRUSTED_DRAM) |
| 82 | /* Shared memory at the base of Trusted DRAM */ |
| 83 | # define FVP_SHARED_RAM_BASE FVP_TRUSTED_DRAM_BASE |
| 84 | # define FVP_TRUSTED_SRAM_LIMIT (FVP_TRUSTED_SRAM_BASE \ |
| 85 | + FVP_TRUSTED_SRAM_SIZE) |
| 86 | #elif (FVP_SHARED_DATA_LOCATION_ID == FVP_IN_TRUSTED_SRAM) |
| 87 | # if (FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM) |
| 88 | # error "Shared data in Trusted SRAM and TSP in Trusted DRAM is not supported" |
| 89 | # endif |
| 90 | /* Shared memory at the top of the Trusted SRAM */ |
| 91 | # define FVP_SHARED_RAM_BASE (FVP_TRUSTED_SRAM_BASE \ |
| 92 | + FVP_TRUSTED_SRAM_SIZE \ |
| 93 | - FVP_SHARED_RAM_SIZE) |
| 94 | # define FVP_TRUSTED_SRAM_LIMIT FVP_SHARED_RAM_BASE |
| 95 | #else |
| 96 | # error "Unsupported FVP_SHARED_DATA_LOCATION_ID value" |
| 97 | #endif |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 98 | |
| 99 | #define DRAM1_BASE 0x80000000ull |
| 100 | #define DRAM1_SIZE 0x80000000ull |
| 101 | #define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1) |
| 102 | #define DRAM1_SEC_SIZE 0x01000000ull |
| 103 | |
| 104 | #define DRAM_BASE DRAM1_BASE |
| 105 | #define DRAM_SIZE DRAM1_SIZE |
| 106 | |
| 107 | #define DRAM2_BASE 0x880000000ull |
| 108 | #define DRAM2_SIZE 0x780000000ull |
| 109 | #define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1) |
| 110 | |
| 111 | #define PCIE_EXP_BASE 0x40000000 |
| 112 | #define TZRNG_BASE 0x7fe60000 |
| 113 | #define TZNVCTR_BASE 0x7fe70000 |
| 114 | #define TZROOTKEY_BASE 0x7fe80000 |
| 115 | |
| 116 | /* Memory mapped Generic timer interfaces */ |
| 117 | #define SYS_CNTCTL_BASE 0x2a430000 |
| 118 | #define SYS_CNTREAD_BASE 0x2a800000 |
| 119 | #define SYS_TIMCTL_BASE 0x2a810000 |
| 120 | |
| 121 | /* V2M motherboard system registers & offsets */ |
| 122 | #define VE_SYSREGS_BASE 0x1c010000 |
| 123 | #define V2M_SYS_ID 0x0 |
| 124 | #define V2M_SYS_LED 0x8 |
| 125 | #define V2M_SYS_CFGDATA 0xa0 |
| 126 | #define V2M_SYS_CFGCTRL 0xa4 |
| 127 | |
| 128 | /* Load address of BL33 in the FVP port */ |
| 129 | #define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */ |
| 130 | |
Andrew Thoelke | a55566d | 2014-05-28 22:22:55 +0100 | [diff] [blame] | 131 | /* Special value used to verify platform parameters from BL2 to BL3-1 */ |
| 132 | #define FVP_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL |
| 133 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 134 | /* |
| 135 | * V2M sysled bit definitions. The values written to this |
| 136 | * register are defined in arch.h & runtime_svc.h. Only |
| 137 | * used by the primary cpu to diagnose any cold boot issues. |
| 138 | * |
| 139 | * SYS_LED[0] - Security state (S=0/NS=1) |
| 140 | * SYS_LED[2:1] - Exception Level (EL3-EL0) |
| 141 | * SYS_LED[7:3] - Exception Class (Sync/Async & origin) |
| 142 | * |
| 143 | */ |
| 144 | #define SYS_LED_SS_SHIFT 0x0 |
| 145 | #define SYS_LED_EL_SHIFT 0x1 |
| 146 | #define SYS_LED_EC_SHIFT 0x3 |
| 147 | |
| 148 | #define SYS_LED_SS_MASK 0x1 |
| 149 | #define SYS_LED_EL_MASK 0x3 |
| 150 | #define SYS_LED_EC_MASK 0x1f |
| 151 | |
| 152 | /* V2M sysid register bits */ |
Juan Castillo | d73898a | 2014-06-13 17:10:00 +0100 | [diff] [blame] | 153 | #define SYS_ID_REV_SHIFT 28 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 154 | #define SYS_ID_HBI_SHIFT 16 |
| 155 | #define SYS_ID_BLD_SHIFT 12 |
| 156 | #define SYS_ID_ARCH_SHIFT 8 |
| 157 | #define SYS_ID_FPGA_SHIFT 0 |
| 158 | |
| 159 | #define SYS_ID_REV_MASK 0xf |
| 160 | #define SYS_ID_HBI_MASK 0xfff |
| 161 | #define SYS_ID_BLD_MASK 0xf |
| 162 | #define SYS_ID_ARCH_MASK 0xf |
| 163 | #define SYS_ID_FPGA_MASK 0xff |
| 164 | |
| 165 | #define SYS_ID_BLD_LENGTH 4 |
| 166 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 167 | #define HBI_FVP_BASE 0x020 |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 168 | #define REV_FVP_BASE_V0 0x0 |
| 169 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 170 | #define HBI_FOUNDATION 0x010 |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 171 | #define REV_FOUNDATION_V2_0 0x0 |
| 172 | #define REV_FOUNDATION_V2_1 0x1 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 173 | |
| 174 | #define BLD_GIC_VE_MMAP 0x0 |
| 175 | #define BLD_GIC_A53A57_MMAP 0x1 |
| 176 | |
| 177 | #define ARCH_MODEL 0x1 |
| 178 | |
| 179 | /* FVP Power controller base address*/ |
| 180 | #define PWRC_BASE 0x1c100000 |
| 181 | |
| 182 | |
| 183 | /******************************************************************************* |
| 184 | * CCI-400 related constants |
| 185 | ******************************************************************************/ |
| 186 | #define CCI400_BASE 0x2c090000 |
| 187 | #define CCI400_SL_IFACE_CLUSTER0 3 |
| 188 | #define CCI400_SL_IFACE_CLUSTER1 4 |
| 189 | #define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \ |
| 190 | CCI400_SL_IFACE_CLUSTER1 : \ |
| 191 | CCI400_SL_IFACE_CLUSTER0) |
| 192 | |
| 193 | /******************************************************************************* |
| 194 | * GIC-400 & interrupt handling related constants |
| 195 | ******************************************************************************/ |
| 196 | /* VE compatible GIC memory map */ |
| 197 | #define VE_GICD_BASE 0x2c001000 |
| 198 | #define VE_GICC_BASE 0x2c002000 |
| 199 | #define VE_GICH_BASE 0x2c004000 |
| 200 | #define VE_GICV_BASE 0x2c006000 |
| 201 | |
| 202 | /* Base FVP compatible GIC memory map */ |
| 203 | #define BASE_GICD_BASE 0x2f000000 |
| 204 | #define BASE_GICR_BASE 0x2f100000 |
| 205 | #define BASE_GICC_BASE 0x2c000000 |
| 206 | #define BASE_GICH_BASE 0x2c010000 |
| 207 | #define BASE_GICV_BASE 0x2c02f000 |
| 208 | |
| 209 | #define IRQ_TZ_WDOG 56 |
| 210 | #define IRQ_SEC_PHY_TIMER 29 |
| 211 | #define IRQ_SEC_SGI_0 8 |
| 212 | #define IRQ_SEC_SGI_1 9 |
| 213 | #define IRQ_SEC_SGI_2 10 |
| 214 | #define IRQ_SEC_SGI_3 11 |
| 215 | #define IRQ_SEC_SGI_4 12 |
| 216 | #define IRQ_SEC_SGI_5 13 |
| 217 | #define IRQ_SEC_SGI_6 14 |
| 218 | #define IRQ_SEC_SGI_7 15 |
| 219 | #define IRQ_SEC_SGI_8 16 |
| 220 | |
| 221 | /******************************************************************************* |
| 222 | * PL011 related constants |
| 223 | ******************************************************************************/ |
| 224 | #define PL011_UART0_BASE 0x1c090000 |
| 225 | #define PL011_UART1_BASE 0x1c0a0000 |
| 226 | #define PL011_UART2_BASE 0x1c0b0000 |
| 227 | #define PL011_UART3_BASE 0x1c0c0000 |
| 228 | |
Soby Mathew | 69817f7 | 2014-07-14 15:43:21 +0100 | [diff] [blame] | 229 | #define PL011_BAUDRATE 115200 |
| 230 | |
| 231 | #define PL011_UART0_CLK_IN_HZ 24000000 |
| 232 | #define PL011_UART1_CLK_IN_HZ 24000000 |
| 233 | #define PL011_UART2_CLK_IN_HZ 24000000 |
| 234 | #define PL011_UART3_CLK_IN_HZ 24000000 |
| 235 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 236 | /******************************************************************************* |
| 237 | * TrustZone address space controller related constants |
| 238 | ******************************************************************************/ |
| 239 | #define TZC400_BASE 0x2a4a0000 |
| 240 | |
| 241 | /* |
| 242 | * The NSAIDs for this platform as used to program the TZC400. |
| 243 | */ |
| 244 | |
| 245 | /* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */ |
| 246 | #define FVP_AID_WIDTH 4 |
| 247 | |
| 248 | /* NSAIDs used by devices in TZC filter 0 on FVP */ |
| 249 | #define FVP_NSAID_DEFAULT 0 |
| 250 | #define FVP_NSAID_PCI 1 |
| 251 | #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ |
| 252 | #define FVP_NSAID_AP 9 /* Application Processors */ |
| 253 | #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ |
| 254 | |
| 255 | /* NSAIDs used by devices in TZC filter 2 on FVP */ |
| 256 | #define FVP_NSAID_HDLCD0 2 |
| 257 | #define FVP_NSAID_CLCD 7 |
| 258 | |
Juan Castillo | 48e84b3 | 2014-08-12 13:51:51 +0100 | [diff] [blame^] | 259 | /******************************************************************************* |
| 260 | * Shared Data |
| 261 | ******************************************************************************/ |
| 262 | |
| 263 | /* Entrypoint mailboxes */ |
| 264 | #define MBOX_BASE FVP_SHARED_RAM_BASE |
| 265 | #define MBOX_SIZE 0x200 |
| 266 | |
| 267 | /* Base address where parameters to BL31 are stored */ |
| 268 | #define PARAMS_BASE (MBOX_BASE + MBOX_SIZE) |
| 269 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 270 | #endif /* __FVP_DEF_H__ */ |