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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
Michal Simekb8eca3b2024-04-19 12:16:46 +02003 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05304 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
Tejas Patel54d13192019-02-27 18:44:55 +05308#include <assert.h>
Prasad Kummari536e1102023-06-22 10:50:02 +05309
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/debug.h>
11#include <lib/mmio.h>
12#include <lib/psci/psci.h>
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -080013#include <plat/arm/common/plat_arm.h>
Prasad Kummari536e1102023-06-22 10:50:02 +053014#include <plat/common/platform.h>
15#include <plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016
Jay Buddhabhatti10e71e42023-06-19 05:08:54 -070017#include "drivers/delay_timer.h"
Prasad Kummari536e1102023-06-22 10:50:02 +053018#include <plat_private.h>
Tejas Patel61717112019-02-27 18:44:57 +053019#include "pm_api_sys.h"
20#include "pm_client.h"
Prasad Kummari536e1102023-06-22 10:50:02 +053021#include <pm_common.h>
Jay Buddhabhatti10e71e42023-06-19 05:08:54 -070022#include "pm_ipi.h"
23#include "pm_svc_main.h"
Tejas Patel61717112019-02-27 18:44:57 +053024
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053025static uintptr_t versal_sec_entry;
26
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053027static int32_t versal_pwr_domain_on(u_register_t mpidr)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053028{
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053029 int32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
Tejas Patel61717112019-02-27 18:44:57 +053030 const struct pm_proc *proc;
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053031
32 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
33
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -070034 if (cpu_id == -1) {
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053035 return PSCI_E_INTERN_FAIL;
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -070036 }
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053037
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053038 proc = pm_get_proc((uint32_t)cpu_id);
Ronak Jain807f41b2024-05-08 02:41:13 -070039 if (proc == NULL) {
Michal Simekb8eca3b2024-04-19 12:16:46 +020040 return PSCI_E_INTERN_FAIL;
41 }
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053042
Tejas Patel61717112019-02-27 18:44:57 +053043 /* Send request to PMC to wake up selected ACPU core */
Abhyuday Godhasaraf435a142021-08-20 00:04:33 -070044 (void)pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFFU) | 0x1U,
45 versal_sec_entry >> 32, 0, SECURE_FLAG);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053046
Tejas Patel61717112019-02-27 18:44:57 +053047 /* Clear power down request */
48 pm_client_wakeup(proc);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053049
50 return PSCI_E_SUCCESS;
51}
52
Tejas Patel54d13192019-02-27 18:44:55 +053053/**
54 * versal_pwr_domain_suspend() - This function sends request to PMC to suspend
Prasad Kummari7d0623a2023-06-09 14:32:00 +053055 * core.
56 * @target_state: Targated state.
Tejas Patel54d13192019-02-27 18:44:55 +053057 *
Tejas Patel54d13192019-02-27 18:44:55 +053058 */
59static void versal_pwr_domain_suspend(const psci_power_state_t *target_state)
60{
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053061 uint32_t state;
62 uint32_t cpu_id = plat_my_core_pos();
Tejas Patel54d13192019-02-27 18:44:55 +053063 const struct pm_proc *proc = pm_get_proc(cpu_id);
64
Ronak Jain807f41b2024-05-08 02:41:13 -070065 if (proc == NULL) {
Michal Simekb8eca3b2024-04-19 12:16:46 +020066 return;
67 }
68
Abhyuday Godhasara589afa52021-08-11 06:15:13 -070069 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
Tejas Patel54d13192019-02-27 18:44:55 +053070 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
71 __func__, i, target_state->pwr_domain_state[i]);
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -070072 }
Tejas Patel54d13192019-02-27 18:44:55 +053073
74 plat_versal_gic_cpuif_disable();
75
Ravi Pateleafc8782019-06-21 05:00:49 -070076 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
77 plat_versal_gic_save();
78 }
Tejas Patel54d13192019-02-27 18:44:55 +053079
80 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
81 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
82
83 /* Send request to PMC to suspend this core */
Abhyuday Godhasaraf435a142021-08-20 00:04:33 -070084 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_sec_entry,
85 SECURE_FLAG);
Tejas Patel54d13192019-02-27 18:44:55 +053086
87 /* APU is to be turned off */
88 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
89 /* disable coherency */
90 plat_arm_interconnect_exit_coherency();
91 }
92}
93
94/**
95 * versal_pwr_domain_suspend_finish() - This function performs actions to finish
Prasad Kummari7d0623a2023-06-09 14:32:00 +053096 * suspend procedure.
97 * @target_state: Targated state.
Tejas Patel54d13192019-02-27 18:44:55 +053098 *
Tejas Patel54d13192019-02-27 18:44:55 +053099 */
100static void versal_pwr_domain_suspend_finish(
101 const psci_power_state_t *target_state)
102{
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +0530103 uint32_t cpu_id = plat_my_core_pos();
Tejas Patel54d13192019-02-27 18:44:55 +0530104 const struct pm_proc *proc = pm_get_proc(cpu_id);
105
Ronak Jain807f41b2024-05-08 02:41:13 -0700106 if (proc == NULL) {
Michal Simekb8eca3b2024-04-19 12:16:46 +0200107 return;
108 }
109
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700110 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
Tejas Patel54d13192019-02-27 18:44:55 +0530111 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
112 __func__, i, target_state->pwr_domain_state[i]);
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700113 }
Tejas Patel54d13192019-02-27 18:44:55 +0530114
115 /* Clear the APU power control register for this cpu */
116 pm_client_wakeup(proc);
117
118 /* enable coherency */
119 plat_arm_interconnect_enter_coherency();
120
121 /* APU was turned off, so restore GIC context */
122 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
123 plat_versal_gic_resume();
Tejas Patel54d13192019-02-27 18:44:55 +0530124 }
Ravi Pateleafc8782019-06-21 05:00:49 -0700125
126 plat_versal_gic_cpuif_enable();
Tejas Patel54d13192019-02-27 18:44:55 +0530127}
128
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530129void versal_pwr_domain_on_finish(const psci_power_state_t *target_state)
130{
131 /* Enable the gic cpu interface */
132 plat_versal_gic_pcpu_init();
133
134 /* Program the gic per-cpu distributor or re-distributor interface */
135 plat_versal_gic_cpuif_enable();
136}
137
Tejas Patel54d13192019-02-27 18:44:55 +0530138/**
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530139 * versal_system_off() - This function sends the system off request to firmware.
140 * This function does not return.
141 *
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800142 */
143static void __dead2 versal_system_off(void)
144{
145 /* Send the power down request to the PMC */
Abhyuday Godhasaraf435a142021-08-20 00:04:33 -0700146 (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
147 pm_get_shutdown_scope(), SECURE_FLAG);
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800148
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700149 while (1) {
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800150 wfi();
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700151 }
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800152}
153
154/**
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530155 * versal_system_reset() - This function sends the reset request to firmware
156 * for the system to reset. This function does not
157 * return.
158 *
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800159 */
160static void __dead2 versal_system_reset(void)
161{
Jay Buddhabhatti10e71e42023-06-19 05:08:54 -0700162 uint32_t ret, timeout = 10000U;
163
164 request_cpu_pwrdwn();
165
166 /*
167 * Send the system reset request to the firmware if power down request
168 * is not received from firmware.
169 */
170 if (!pwrdwn_req_received) {
171 (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET,
172 pm_get_shutdown_scope(), SECURE_FLAG);
173
174 /*
175 * Wait for system shutdown request completed and idle callback
176 * not received.
177 */
178 do {
179 ret = ipi_mb_enquire_status(primary_proc->ipi->local_ipi_id,
180 primary_proc->ipi->remote_ipi_id);
181 udelay(100);
182 timeout--;
183 } while ((ret != IPI_MB_STATUS_RECV_PENDING) && (timeout > 0U));
184 }
185
186 (void)psci_cpu_off();
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800187
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700188 while (1) {
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800189 wfi();
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700190 }
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800191}
192
193/**
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530194 * versal_pwr_domain_off() - This function performs actions to turn off core.
195 * @target_state: Targated state.
Tejas Patel54d13192019-02-27 18:44:55 +0530196 *
Tejas Patel54d13192019-02-27 18:44:55 +0530197 */
198static void versal_pwr_domain_off(const psci_power_state_t *target_state)
199{
Jay Buddhabhattib8c581f2024-06-24 01:47:39 -0700200 uint32_t ret, fw_api_version, version[RET_PAYLOAD_ARG_CNT] = {0U};
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +0530201 uint32_t cpu_id = plat_my_core_pos();
Tejas Patel54d13192019-02-27 18:44:55 +0530202 const struct pm_proc *proc = pm_get_proc(cpu_id);
203
Ronak Jain807f41b2024-05-08 02:41:13 -0700204 if (proc == NULL) {
Michal Simekb8eca3b2024-04-19 12:16:46 +0200205 return;
206 }
207
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700208 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
Tejas Patel54d13192019-02-27 18:44:55 +0530209 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
210 __func__, i, target_state->pwr_domain_state[i]);
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700211 }
Tejas Patel54d13192019-02-27 18:44:55 +0530212
213 /* Prevent interrupts from spuriously waking up this cpu */
214 plat_versal_gic_cpuif_disable();
215
216 /*
217 * Send request to PMC to power down the appropriate APU CPU
218 * core.
219 * According to PSCI specification, CPU_off function does not
220 * have resume address and CPU core can only be woken up
221 * invoking CPU_on function, during which resume address will
222 * be set.
223 */
Jay Buddhabhatti31488a32023-09-11 23:50:06 -0700224 ret = pm_feature_check((uint32_t)PM_SELF_SUSPEND, &version[0], SECURE_FLAG);
225 if (ret == PM_RET_SUCCESS) {
226 fw_api_version = version[0] & 0xFFFFU;
227 if (fw_api_version >= 3U) {
228 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_OFF, 0,
229 SECURE_FLAG);
230 } else {
231 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0,
232 SECURE_FLAG);
233 }
234 }
Tejas Patel54d13192019-02-27 18:44:55 +0530235}
236
237/**
238 * versal_validate_power_state() - This function ensures that the power state
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530239 * parameter in request is valid.
240 * @power_state: Power state of core.
241 * @req_state: Requested state.
Tejas Patel54d13192019-02-27 18:44:55 +0530242 *
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530243 * Return: Returns status, either success or reason.
Tejas Patel54d13192019-02-27 18:44:55 +0530244 *
Tejas Patel54d13192019-02-27 18:44:55 +0530245 */
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +0530246static int32_t versal_validate_power_state(uint32_t power_state,
Tejas Patel54d13192019-02-27 18:44:55 +0530247 psci_power_state_t *req_state)
248{
249 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
250
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +0530251 uint32_t pstate = psci_get_pstate_type(power_state);
Tejas Patel54d13192019-02-27 18:44:55 +0530252
253 assert(req_state);
254
255 /* Sanity check the requested state */
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700256 if (pstate == PSTATE_TYPE_STANDBY) {
Tejas Patel54d13192019-02-27 18:44:55 +0530257 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700258 } else {
Tejas Patel54d13192019-02-27 18:44:55 +0530259 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700260 }
Tejas Patel54d13192019-02-27 18:44:55 +0530261
262 /* We expect the 'state id' to be zero */
Abhyuday Godhasarabacbdee2021-08-20 00:27:03 -0700263 if (psci_get_pstate_id(power_state) != 0U) {
Tejas Patel54d13192019-02-27 18:44:55 +0530264 return PSCI_E_INVALID_PARAMS;
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700265 }
Tejas Patel54d13192019-02-27 18:44:55 +0530266
267 return PSCI_E_SUCCESS;
268}
269
270/**
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530271 * versal_get_sys_suspend_power_state() - Get power state for system suspend.
272 * @req_state: Requested state.
Tejas Patel54d13192019-02-27 18:44:55 +0530273 *
Tejas Patel54d13192019-02-27 18:44:55 +0530274 */
275static void versal_get_sys_suspend_power_state(psci_power_state_t *req_state)
276{
277 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
278 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
279}
280
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530281static const struct plat_psci_ops versal_nopmc_psci_ops = {
Tejas Patel61717112019-02-27 18:44:57 +0530282 .pwr_domain_on = versal_pwr_domain_on,
Tejas Patel54d13192019-02-27 18:44:55 +0530283 .pwr_domain_off = versal_pwr_domain_off,
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530284 .pwr_domain_on_finish = versal_pwr_domain_on_finish,
Tejas Patel54d13192019-02-27 18:44:55 +0530285 .pwr_domain_suspend = versal_pwr_domain_suspend,
286 .pwr_domain_suspend_finish = versal_pwr_domain_suspend_finish,
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800287 .system_off = versal_system_off,
288 .system_reset = versal_system_reset,
Tejas Patel54d13192019-02-27 18:44:55 +0530289 .validate_power_state = versal_validate_power_state,
290 .get_sys_suspend_power_state = versal_get_sys_suspend_power_state,
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530291};
292
293/*******************************************************************************
294 * Export the platform specific power ops.
295 ******************************************************************************/
Venkatesh Yadav Abbarapu2cefbcd2022-07-31 14:05:40 +0530296int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint,
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530297 const struct plat_psci_ops **psci_ops)
298{
299 versal_sec_entry = sec_entrypoint;
300
301 *psci_ops = &versal_nopmc_psci_ops;
302
303 return 0;
304}