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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathew981487a2015-07-13 14:10:57 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Soby Mathew96168382014-12-17 14:47:57 +000034#include <debug.h>
35#include <platform.h>
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000036#include <runtime_svc.h>
Soby Mathew6cdddaf2015-01-07 11:10:22 +000037#include <std_svc.h>
Soby Mathew981487a2015-07-13 14:10:57 +010038#include <string.h>
Dan Handley714a0d22014-04-09 13:13:04 +010039#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
41/*******************************************************************************
42 * PSCI frontend api for servicing SMCs. Described in the PSCI spec.
43 ******************************************************************************/
44int psci_cpu_on(unsigned long target_cpu,
45 unsigned long entrypoint,
46 unsigned long context_id)
47
48{
49 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +010050 unsigned int end_pwrlvl;
Soby Mathew8595b872015-01-06 15:36:38 +000051 entry_point_info_t ep;
Achin Gupta4f6ad662013-10-25 09:08:21 +010052
53 /* Determine if the cpu exists of not */
Soby Mathew981487a2015-07-13 14:10:57 +010054 rc = psci_validate_mpidr(target_cpu);
55 if (rc != PSCI_E_SUCCESS)
Soby Mathew74e52a72014-10-02 16:56:51 +010056 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +010057
58 /* Validate the entrypoint using platform pm_ops */
59 if (psci_plat_pm_ops->validate_ns_entrypoint) {
60 rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint);
61 if (rc != PSCI_E_SUCCESS) {
62 assert(rc == PSCI_E_INVALID_PARAMS);
63 return PSCI_E_INVALID_PARAMS;
64 }
Achin Gupta4f6ad662013-10-25 09:08:21 +010065 }
66
Achin Gupta0959db52013-12-02 17:33:04 +000067 /*
Soby Mathew8595b872015-01-06 15:36:38 +000068 * Verify and derive the re-entry information for
69 * the non-secure world from the non-secure state from
70 * where this call originated.
71 */
72 rc = psci_get_ns_ep_info(&ep, entrypoint, context_id);
73 if (rc != PSCI_E_SUCCESS)
74 return rc;
75
Soby Mathew8595b872015-01-06 15:36:38 +000076 /*
Soby Mathew981487a2015-07-13 14:10:57 +010077 * To turn this cpu on, specify which power
Achin Gupta0959db52013-12-02 17:33:04 +000078 * levels need to be turned on
79 */
Soby Mathew981487a2015-07-13 14:10:57 +010080 end_pwrlvl = PLAT_MAX_PWR_LVL;
81 rc = psci_cpu_on_start(target_cpu,
Soby Mathew8595b872015-01-06 15:36:38 +000082 &ep,
Soby Mathew981487a2015-07-13 14:10:57 +010083 end_pwrlvl);
Achin Gupta4f6ad662013-10-25 09:08:21 +010084 return rc;
85}
86
87unsigned int psci_version(void)
88{
89 return PSCI_MAJOR_VER | PSCI_MINOR_VER;
90}
91
92int psci_cpu_suspend(unsigned int power_state,
93 unsigned long entrypoint,
94 unsigned long context_id)
95{
96 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +010097 unsigned int target_pwrlvl, is_power_down_state;
Soby Mathew8595b872015-01-06 15:36:38 +000098 entry_point_info_t ep;
Soby Mathew981487a2015-07-13 14:10:57 +010099 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
100 plat_local_state_t cpu_pd_state;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100101
Soby Mathew981487a2015-07-13 14:10:57 +0100102 /* Validate the power_state parameter */
103 rc = psci_validate_power_state(power_state, &state_info);
104 if (rc != PSCI_E_SUCCESS) {
105 assert(rc == PSCI_E_INVALID_PARAMS);
106 return rc;
107 }
Vikram Kanigirif100f412014-04-01 19:26:26 +0100108
Soby Mathew981487a2015-07-13 14:10:57 +0100109 /*
110 * Get the value of the state type bit from the power state parameter.
111 */
112 is_power_down_state = psci_get_pstate_type(power_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100113
Soby Mathew981487a2015-07-13 14:10:57 +0100114 /* Sanity check the requested suspend levels */
115 assert (psci_validate_suspend_req(&state_info, is_power_down_state)
116 == PSCI_E_SUCCESS);
Soby Mathew74e52a72014-10-02 16:56:51 +0100117
Soby Mathew981487a2015-07-13 14:10:57 +0100118 target_pwrlvl = psci_find_target_suspend_lvl(&state_info);
119
120 /* Fast path for CPU standby.*/
121 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
122 if (!psci_plat_pm_ops->cpu_standby)
Soby Mathew74e52a72014-10-02 16:56:51 +0100123 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +0100124
Soby Mathew981487a2015-07-13 14:10:57 +0100125 /*
126 * Set the state of the CPU power domain to the platform
127 * specific retention state and enter the standby state.
128 */
129 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL];
130 psci_set_cpu_local_state(cpu_pd_state);
131 psci_plat_pm_ops->cpu_standby(cpu_pd_state);
Achin Gupta42c52802014-05-09 19:32:25 +0100132
Soby Mathew981487a2015-07-13 14:10:57 +0100133 /* Upon exit from standby, set the state back to RUN. */
134 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
Achin Gupta42c52802014-05-09 19:32:25 +0100135
Soby Mathew74e52a72014-10-02 16:56:51 +0100136 return PSCI_E_SUCCESS;
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000137 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100138
Achin Gupta42c52802014-05-09 19:32:25 +0100139 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100140 * If a power down state has been requested, we need to verify entry
141 * point and program entry information.
Soby Mathew8595b872015-01-06 15:36:38 +0000142 */
Soby Mathew981487a2015-07-13 14:10:57 +0100143 if (is_power_down_state) {
144 if (psci_plat_pm_ops->validate_ns_entrypoint) {
145 rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint);
146 if (rc != PSCI_E_SUCCESS) {
147 assert(rc == PSCI_E_INVALID_PARAMS);
148 return rc;
149 }
150 }
Soby Mathew8595b872015-01-06 15:36:38 +0000151
Soby Mathew981487a2015-07-13 14:10:57 +0100152 /*
153 * Verify and derive the re-entry information for
154 * the non-secure world from the non-secure state from
155 * where this call originated.
156 */
157 rc = psci_get_ns_ep_info(&ep, entrypoint, context_id);
158 if (rc != PSCI_E_SUCCESS)
159 return rc;
160 }
Soby Mathewf5121572014-09-30 11:19:51 +0100161
Soby Mathew8595b872015-01-06 15:36:38 +0000162 /*
Achin Gupta42c52802014-05-09 19:32:25 +0100163 * Do what is needed to enter the power down state. Upon success,
Soby Mathew981487a2015-07-13 14:10:57 +0100164 * enter the final wfi which will power down this CPU. This function
165 * might return if the power down was abandoned for any reason, e.g.
166 * arrival of an interrupt
Achin Gupta42c52802014-05-09 19:32:25 +0100167 */
Soby Mathew981487a2015-07-13 14:10:57 +0100168 psci_cpu_suspend_start(&ep,
169 target_pwrlvl,
170 &state_info,
171 is_power_down_state);
Soby Mathew74e52a72014-10-02 16:56:51 +0100172
Soby Mathew74e52a72014-10-02 16:56:51 +0100173 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174}
175
Soby Mathew96168382014-12-17 14:47:57 +0000176int psci_system_suspend(unsigned long entrypoint,
177 unsigned long context_id)
178{
179 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +0100180 psci_power_state_t state_info;
Soby Mathew96168382014-12-17 14:47:57 +0000181 entry_point_info_t ep;
182
183 /* Validate the entrypoint using platform pm_ops */
184 if (psci_plat_pm_ops->validate_ns_entrypoint) {
185 rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint);
186 if (rc != PSCI_E_SUCCESS) {
187 assert(rc == PSCI_E_INVALID_PARAMS);
Soby Mathew981487a2015-07-13 14:10:57 +0100188 return rc;
Soby Mathew96168382014-12-17 14:47:57 +0000189 }
190 }
191
192 /* Check if the current CPU is the last ON CPU in the system */
193 if (!psci_is_last_on_cpu())
194 return PSCI_E_DENIED;
195
196 /*
197 * Verify and derive the re-entry information for
198 * the non-secure world from the non-secure state from
199 * where this call originated.
200 */
201 rc = psci_get_ns_ep_info(&ep, entrypoint, context_id);
202 if (rc != PSCI_E_SUCCESS)
203 return rc;
204
Soby Mathew981487a2015-07-13 14:10:57 +0100205 /* Query the psci_power_state for system suspend */
206 psci_query_sys_suspend_pwrstate(&state_info);
Soby Mathew96168382014-12-17 14:47:57 +0000207
Soby Mathew981487a2015-07-13 14:10:57 +0100208 /* Ensure that the psci_power_state makes sense */
209 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL);
210 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN)
211 == PSCI_E_SUCCESS);
212 assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]));
Soby Mathew96168382014-12-17 14:47:57 +0000213
214 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100215 * Do what is needed to enter the system suspend state. This function
216 * might return if the power down was abandoned for any reason, e.g.
217 * arrival of an interrupt
Soby Mathew96168382014-12-17 14:47:57 +0000218 */
Soby Mathew981487a2015-07-13 14:10:57 +0100219 psci_cpu_suspend_start(&ep,
220 PLAT_MAX_PWR_LVL,
221 &state_info,
222 PSTATE_TYPE_POWERDOWN);
Soby Mathew96168382014-12-17 14:47:57 +0000223
Soby Mathew96168382014-12-17 14:47:57 +0000224 return PSCI_E_SUCCESS;
225}
226
Achin Gupta4f6ad662013-10-25 09:08:21 +0100227int psci_cpu_off(void)
228{
229 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +0100230 int target_pwrlvl = PLAT_MAX_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100231
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100233 * Do what is needed to power off this CPU and possible higher power
234 * levels if it able to do so. Upon success, enter the final wfi
235 * which will power down this CPU.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236 */
Soby Mathew981487a2015-07-13 14:10:57 +0100237 rc = psci_do_cpu_off(target_pwrlvl);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100238
Achin Gupta3140a9e2013-12-02 16:23:12 +0000239 /*
240 * The only error cpu_off can return is E_DENIED. So check if that's
241 * indeed the case.
242 */
Achin Gupta42c52802014-05-09 19:32:25 +0100243 assert (rc == PSCI_E_DENIED);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100244
245 return rc;
246}
247
248int psci_affinity_info(unsigned long target_affinity,
249 unsigned int lowest_affinity_level)
250{
Soby Mathew981487a2015-07-13 14:10:57 +0100251 unsigned int target_idx;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100252
Soby Mathew981487a2015-07-13 14:10:57 +0100253 /* We dont support level higher than PSCI_CPU_PWR_LVL */
254 if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
255 return PSCI_E_INVALID_PARAMS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100256
Soby Mathew981487a2015-07-13 14:10:57 +0100257 /* Calculate the cpu index of the target */
258 target_idx = plat_core_pos_by_mpidr(target_affinity);
259 if (target_idx == -1)
260 return PSCI_E_INVALID_PARAMS;
Achin Gupta75f73672013-12-05 16:33:10 +0000261
Soby Mathew981487a2015-07-13 14:10:57 +0100262 return psci_get_aff_info_state_by_idx(target_idx);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100263}
264
Soby Mathew110fe362014-10-23 10:35:34 +0100265int psci_migrate(unsigned long target_cpu)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100266{
Soby Mathew110fe362014-10-23 10:35:34 +0100267 int rc;
268 unsigned long resident_cpu_mpidr;
269
270 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
271 if (rc != PSCI_TOS_UP_MIG_CAP)
272 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
273 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED;
274
275 /*
276 * Migrate should only be invoked on the CPU where
277 * the Secure OS is resident.
278 */
279 if (resident_cpu_mpidr != read_mpidr_el1())
280 return PSCI_E_NOT_PRESENT;
281
282 /* Check the validity of the specified target cpu */
Soby Mathew981487a2015-07-13 14:10:57 +0100283 rc = psci_validate_mpidr(target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100284 if (rc != PSCI_E_SUCCESS)
285 return PSCI_E_INVALID_PARAMS;
286
287 assert(psci_spd_pm && psci_spd_pm->svc_migrate);
288
289 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu);
290 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL);
291
292 return rc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100293}
294
Soby Mathew110fe362014-10-23 10:35:34 +0100295int psci_migrate_info_type(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100296{
Soby Mathew110fe362014-10-23 10:35:34 +0100297 unsigned long resident_cpu_mpidr;
298
299 return psci_spd_migrate_info(&resident_cpu_mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100300}
301
Soby Mathew110fe362014-10-23 10:35:34 +0100302long psci_migrate_info_up_cpu(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100303{
Soby Mathew110fe362014-10-23 10:35:34 +0100304 unsigned long resident_cpu_mpidr;
305 int rc;
306
Achin Gupta4f6ad662013-10-25 09:08:21 +0100307 /*
Soby Mathew110fe362014-10-23 10:35:34 +0100308 * Return value of this depends upon what
309 * psci_spd_migrate_info() returns.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100310 */
Soby Mathew110fe362014-10-23 10:35:34 +0100311 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
312 if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP)
313 return PSCI_E_INVALID_PARAMS;
314
315 return resident_cpu_mpidr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100316}
317
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000318int psci_features(unsigned int psci_fid)
319{
320 uint32_t local_caps = psci_caps;
321
322 /* Check if it is a 64 bit function */
323 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64)
324 local_caps &= PSCI_CAP_64BIT_MASK;
325
326 /* Check for invalid fid */
327 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid)
328 && is_psci_fid(psci_fid)))
329 return PSCI_E_NOT_SUPPORTED;
330
331
332 /* Check if the psci fid is supported or not */
333 if (!(local_caps & define_psci_cap(psci_fid)))
334 return PSCI_E_NOT_SUPPORTED;
335
336 /* Format the feature flags */
337 if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 ||
338 psci_fid == PSCI_CPU_SUSPEND_AARCH64) {
339 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100340 * The trusted firmware does not support OS Initiated Mode.
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000341 */
Soby Mathew981487a2015-07-13 14:10:57 +0100342 return (FF_PSTATE << FF_PSTATE_SHIFT) |
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000343 ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT);
344 }
345
346 /* Return 0 for all other fid's */
347 return PSCI_E_SUCCESS;
348}
349
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000350/*******************************************************************************
351 * PSCI top level handler for servicing SMCs.
352 ******************************************************************************/
353uint64_t psci_smc_handler(uint32_t smc_fid,
354 uint64_t x1,
355 uint64_t x2,
356 uint64_t x3,
357 uint64_t x4,
358 void *cookie,
359 void *handle,
360 uint64_t flags)
361{
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100362 if (is_caller_secure(flags))
363 SMC_RET1(handle, SMC_UNK);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000364
Soby Mathew61e615b2015-01-15 11:49:49 +0000365 /* Check the fid against the capabilities */
366 if (!(psci_caps & define_psci_cap(smc_fid)))
367 SMC_RET1(handle, SMC_UNK);
368
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100369 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
370 /* 32-bit PSCI function, clear top parameter bits */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000371
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100372 x1 = (uint32_t)x1;
373 x2 = (uint32_t)x2;
374 x3 = (uint32_t)x3;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000375
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100376 switch (smc_fid) {
377 case PSCI_VERSION:
378 SMC_RET1(handle, psci_version());
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000379
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100380 case PSCI_CPU_OFF:
Achin Guptae1aa5162014-06-26 09:58:52 +0100381 SMC_RET1(handle, psci_cpu_off());
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000382
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100383 case PSCI_CPU_SUSPEND_AARCH32:
Achin Guptae1aa5162014-06-26 09:58:52 +0100384 SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000385
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100386 case PSCI_CPU_ON_AARCH32:
387 SMC_RET1(handle, psci_cpu_on(x1, x2, x3));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000388
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100389 case PSCI_AFFINITY_INFO_AARCH32:
390 SMC_RET1(handle, psci_affinity_info(x1, x2));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000391
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100392 case PSCI_MIG_AARCH32:
393 SMC_RET1(handle, psci_migrate(x1));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000394
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100395 case PSCI_MIG_INFO_TYPE:
396 SMC_RET1(handle, psci_migrate_info_type());
397
398 case PSCI_MIG_INFO_UP_CPU_AARCH32:
399 SMC_RET1(handle, psci_migrate_info_up_cpu());
400
Soby Mathew96168382014-12-17 14:47:57 +0000401 case PSCI_SYSTEM_SUSPEND_AARCH32:
402 SMC_RET1(handle, psci_system_suspend(x1, x2));
403
Juan Castillo4dc4a472014-08-12 11:17:06 +0100404 case PSCI_SYSTEM_OFF:
405 psci_system_off();
406 /* We should never return from psci_system_off() */
407
408 case PSCI_SYSTEM_RESET:
409 psci_system_reset();
410 /* We should never return from psci_system_reset() */
411
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000412 case PSCI_FEATURES:
413 SMC_RET1(handle, psci_features(x1));
414
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100415 default:
416 break;
417 }
418 } else {
419 /* 64-bit PSCI function */
420
421 switch (smc_fid) {
422 case PSCI_CPU_SUSPEND_AARCH64:
Achin Guptae1aa5162014-06-26 09:58:52 +0100423 SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3));
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100424
425 case PSCI_CPU_ON_AARCH64:
426 SMC_RET1(handle, psci_cpu_on(x1, x2, x3));
427
428 case PSCI_AFFINITY_INFO_AARCH64:
429 SMC_RET1(handle, psci_affinity_info(x1, x2));
430
431 case PSCI_MIG_AARCH64:
432 SMC_RET1(handle, psci_migrate(x1));
433
434 case PSCI_MIG_INFO_UP_CPU_AARCH64:
435 SMC_RET1(handle, psci_migrate_info_up_cpu());
436
Soby Mathew96168382014-12-17 14:47:57 +0000437 case PSCI_SYSTEM_SUSPEND_AARCH64:
438 SMC_RET1(handle, psci_system_suspend(x1, x2));
439
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100440 default:
441 break;
442 }
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000443 }
444
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100445 WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid);
446 SMC_RET1(handle, SMC_UNK);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000447}