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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Vikram Kanigirifbb13012016-02-15 11:54:14 +00002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Achin Gupta4f6ad662013-10-25 09:08:21 +01007#include <arch_helpers.h>
Dan Handley2b6b5742015-03-19 19:17:53 +00008#include <arm_config.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +01009#include <assert.h>
Juan Castillo4dc4a472014-08-12 11:17:06 +010010#include <debug.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000011#include <errno.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010012#include <mmio.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000013#include <plat_arm.h>
Isla Mitchelld2548792017-07-14 10:48:25 +010014#include <platform.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010015#include <psci.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000016#include <v2m_def.h>
Dan Handley4d2e49d2014-04-11 11:52:12 +010017#include "drivers/pwrc/fvp_pwrc.h"
Dan Handleyed6ff952014-05-14 17:44:19 +010018#include "fvp_def.h"
19#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010020
Dan Handley2b6b5742015-03-19 19:17:53 +000021
Soby Mathew7799cf72015-04-16 14:49:09 +010022#if ARM_RECOM_STATE_ID_ENC
23/*
24 * The table storing the valid idle power states. Ensure that the
25 * array entries are populated in ascending order of state-id to
26 * enable us to use binary search during power state validation.
27 * The table must be terminated by a NULL entry.
28 */
29const unsigned int arm_pm_idle_states[] = {
30 /* State-id - 0x01 */
31 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET,
32 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
33 /* State-id - 0x02 */
34 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
35 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
36 /* State-id - 0x22 */
37 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
38 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
39 0,
40};
41#endif
42
Achin Gupta4f6ad662013-10-25 09:08:21 +010043/*******************************************************************************
Achin Gupta85876392014-07-31 17:45:51 +010044 * Function which implements the common FVP specific operations to power down a
Achin Gupta85876392014-07-31 17:45:51 +010045 * cluster in response to a CPU_OFF or CPU_SUSPEND request.
46 ******************************************************************************/
Sandrine Bailleuxa64a8542015-03-05 10:54:34 +000047static void fvp_cluster_pwrdwn_common(void)
Achin Gupta85876392014-07-31 17:45:51 +010048{
49 uint64_t mpidr = read_mpidr_el1();
50
dp-armee3457b2017-05-23 09:32:49 +010051#if ENABLE_SPE_FOR_LOWER_ELS
52 /*
53 * On power down we need to disable statistical profiling extensions
54 * before exiting coherency.
55 */
56 arm_disable_spe();
57#endif
58
Achin Gupta85876392014-07-31 17:45:51 +010059 /* Disable coherency if this cluster is to be turned off */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000060 fvp_interconnect_disable();
Achin Gupta85876392014-07-31 17:45:51 +010061
62 /* Program the power controller to turn the cluster off */
63 fvp_pwrc_write_pcoffr(mpidr);
64}
65
Soby Mathew12012dd2015-10-26 14:01:53 +000066static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state)
67{
68 unsigned long mpidr;
69
70 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
71 ARM_LOCAL_STATE_OFF);
72
73 /* Get the mpidr for this cpu */
74 mpidr = read_mpidr_el1();
75
76 /* Perform the common cluster specific operations */
77 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
78 ARM_LOCAL_STATE_OFF) {
79 /*
80 * This CPU might have woken up whilst the cluster was
81 * attempting to power down. In this case the FVP power
82 * controller will have a pending cluster power off request
83 * which needs to be cleared by writing to the PPONR register.
84 * This prevents the power controller from interpreting a
85 * subsequent entry of this cpu into a simple wfi as a power
86 * down request.
87 */
88 fvp_pwrc_write_pponr(mpidr);
89
90 /* Enable coherency if this cluster was off */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000091 fvp_interconnect_enable();
Soby Mathew12012dd2015-10-26 14:01:53 +000092 }
93
94 /*
95 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
96 * with a cpu power down unless the bit is set again
97 */
98 fvp_pwrc_clr_wen(mpidr);
99}
100
101
Achin Gupta85876392014-07-31 17:45:51 +0100102/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100103 * FVP handler called when a CPU is about to enter standby.
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000104 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100105void fvp_cpu_standby(plat_local_state_t cpu_state)
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000106{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100107
108 assert(cpu_state == ARM_LOCAL_STATE_RET);
109
Andrew Thoelke42e75a72014-04-28 12:28:39 +0100110 /*
111 * Enter standby state
112 * dsb is good practice before using wfi to enter low power states
113 */
114 dsb();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000115 wfi();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000116}
117
118/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100119 * FVP handler called when a power domain is about to be turned on. The
120 * mpidr determines the CPU to be turned on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100121 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100122int fvp_pwr_domain_on(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100123{
124 int rc = PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100125 unsigned int psysr;
126
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127 /*
Sandrine Bailleux7175bde2015-12-08 14:18:24 +0000128 * Ensure that we do not cancel an inflight power off request for the
129 * target cpu. That would leave it in a zombie wfi. Wait for it to power
130 * off and then program the power controller to turn that CPU on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100131 */
132 do {
133 psysr = fvp_pwrc_read_psysr(mpidr);
134 } while (psysr & PSYSR_AFF_L0);
135
Achin Gupta4f6ad662013-10-25 09:08:21 +0100136 fvp_pwrc_write_pponr(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137 return rc;
138}
139
140/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100141 * FVP handler called when a power domain is about to be turned off. The
142 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100143 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100144void fvp_pwr_domain_off(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100145{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100146 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
147 ARM_LOCAL_STATE_OFF);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100148
Achin Gupta85876392014-07-31 17:45:51 +0100149 /*
Soby Mathewfec4eb72015-07-01 16:16:20 +0100150 * If execution reaches this stage then this power domain will be
151 * suspended. Perform at least the cpu specific actions followed
152 * by the cluster specific operations if applicable.
Achin Gupta85876392014-07-31 17:45:51 +0100153 */
Jeenu Viswambharan6ad35482016-12-09 11:14:34 +0000154
155 /* Prevent interrupts from spuriously waking up this cpu */
156 plat_arm_gic_cpuif_disable();
157
158 /* Turn redistributor off */
159 plat_arm_gic_redistif_off();
160
161 /* Program the power controller to power off this cpu. */
162 fvp_pwrc_write_ppoffr(read_mpidr_el1());
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163
Soby Mathewfec4eb72015-07-01 16:16:20 +0100164 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
165 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100166 fvp_cluster_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100167
Achin Gupta4f6ad662013-10-25 09:08:21 +0100168}
169
170/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100171 * FVP handler called when a power domain is about to be suspended. The
172 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100173 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100174void fvp_pwr_domain_suspend(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100175{
Soby Mathewffb4ab12014-09-26 15:08:52 +0100176 unsigned long mpidr;
177
Soby Mathewfec4eb72015-07-01 16:16:20 +0100178 /*
179 * FVP has retention only at cpu level. Just return
180 * as nothing is to be done for retention.
181 */
182 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
183 ARM_LOCAL_STATE_RET)
Soby Mathew74e52a72014-10-02 16:56:51 +0100184 return;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100185
Soby Mathewfec4eb72015-07-01 16:16:20 +0100186 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
187 ARM_LOCAL_STATE_OFF);
188
Soby Mathewffb4ab12014-09-26 15:08:52 +0100189 /* Get the mpidr for this cpu */
190 mpidr = read_mpidr_el1();
191
Achin Gupta85876392014-07-31 17:45:51 +0100192 /* Program the power controller to enable wakeup interrupts. */
193 fvp_pwrc_set_wen(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100194
Jeenu Viswambharan6ad35482016-12-09 11:14:34 +0000195 /* Prevent interrupts from spuriously waking up this cpu */
196 plat_arm_gic_cpuif_disable();
197
198 /*
199 * The Redistributor is not powered off as it can potentially prevent
200 * wake up events reaching the CPUIF and/or might lead to losing
201 * register context.
202 */
203
204 /* Program the power controller to power off this cpu. */
205 fvp_pwrc_write_ppoffr(read_mpidr_el1());
Achin Gupta4f6ad662013-10-25 09:08:21 +0100206
Achin Gupta85876392014-07-31 17:45:51 +0100207 /* Perform the common cluster specific operations */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100208 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
209 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100210 fvp_cluster_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100211}
212
213/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100214 * FVP handler called when a power domain has just been powered on after
215 * being turned off earlier. The target_state encodes the low power state that
216 * each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100217 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100218void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100219{
Soby Mathew12012dd2015-10-26 14:01:53 +0000220 fvp_power_domain_on_finish_common(target_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100221
Achin Gupta85876392014-07-31 17:45:51 +0100222 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000223 plat_arm_gic_pcpu_init();
224
225 /* Program the gic per-cpu distributor or re-distributor interface */
226 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100227}
228
229/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100230 * FVP handler called when a power domain has just been powered on after
231 * having been suspended earlier. The target_state encodes the low power state
232 * that each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100233 * TODO: At the moment we reuse the on finisher and reinitialize the secure
234 * context. Need to implement a separate suspend finisher.
235 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100236void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100237{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100238 /*
239 * Nothing to be done on waking up from retention from CPU level.
240 */
241 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
242 ARM_LOCAL_STATE_RET)
243 return;
244
Soby Mathew12012dd2015-10-26 14:01:53 +0000245 fvp_power_domain_on_finish_common(target_state);
246
247 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000248 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100249}
250
Juan Castillo4dc4a472014-08-12 11:17:06 +0100251/*******************************************************************************
252 * FVP handlers to shutdown/reboot the system
253 ******************************************************************************/
254static void __dead2 fvp_system_off(void)
255{
256 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000257 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
258 V2M_CFGCTRL_START |
259 V2M_CFGCTRL_RW |
260 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100261 wfi();
262 ERROR("FVP System Off: operation not handled.\n");
263 panic();
264}
265
266static void __dead2 fvp_system_reset(void)
267{
268 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000269 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
270 V2M_CFGCTRL_START |
271 V2M_CFGCTRL_RW |
272 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100273 wfi();
274 ERROR("FVP System Reset: operation not handled.\n");
275 panic();
276}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100277
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100278static int fvp_node_hw_state(u_register_t target_cpu,
279 unsigned int power_level)
280{
281 unsigned int psysr;
282 int ret;
283
284 /*
285 * The format of 'power_level' is implementation-defined, but 0 must
286 * mean a CPU. We also allow 1 to denote the cluster
287 */
288 if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1)
289 return PSCI_E_INVALID_PARAMS;
290
291 /*
292 * Read the status of the given MPDIR from FVP power controller. The
293 * power controller only gives us on/off status, so map that to expected
294 * return values of the PSCI call
295 */
296 psysr = fvp_pwrc_read_psysr(target_cpu);
297 if (psysr == PSYSR_INVALID)
298 return PSCI_E_INVALID_PARAMS;
299
300 switch (power_level) {
301 case ARM_PWR_LVL0:
302 ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF;
303 break;
304 case ARM_PWR_LVL1:
305 ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF;
306 break;
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100307 }
308
309 return ret;
310}
311
Achin Gupta4f6ad662013-10-25 09:08:21 +0100312/*******************************************************************************
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100313 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
314 * platform layer will take care of registering the handlers with PSCI.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100315 ******************************************************************************/
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100316plat_psci_ops_t plat_arm_psci_pm_ops = {
Soby Mathewfec4eb72015-07-01 16:16:20 +0100317 .cpu_standby = fvp_cpu_standby,
318 .pwr_domain_on = fvp_pwr_domain_on,
319 .pwr_domain_off = fvp_pwr_domain_off,
320 .pwr_domain_suspend = fvp_pwr_domain_suspend,
321 .pwr_domain_on_finish = fvp_pwr_domain_on_finish,
322 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish,
Juan Castillo4dc4a472014-08-12 11:17:06 +0100323 .system_off = fvp_system_off,
Soby Mathew74e52a72014-10-02 16:56:51 +0100324 .system_reset = fvp_system_reset,
Soby Mathew0d9e8522015-07-15 13:36:24 +0100325 .validate_power_state = arm_validate_power_state,
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100326 .validate_ns_entrypoint = arm_validate_ns_entrypoint,
327 .get_node_hw_state = fvp_node_hw_state
Achin Gupta4f6ad662013-10-25 09:08:21 +0100328};