Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 1 | /* |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <assert.h> |
| 10 | #include <cassert.h> |
| 11 | #include <platform_def.h> |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 12 | #include <stdbool.h> |
Isla Mitchell | c4a1a07 | 2017-08-07 11:20:13 +0100 | [diff] [blame] | 13 | #include <utils_def.h> |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 14 | #include <xlat_tables_v2.h> |
| 15 | #include "../xlat_tables_private.h" |
| 16 | |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 17 | #if (ARM_ARCH_MAJOR == 7) && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING) |
Etienne Carriere | 0af78b6 | 2017-11-08 13:53:47 +0100 | [diff] [blame] | 18 | #error ARMv7 target does not support LPAE MMU descriptors |
| 19 | #endif |
| 20 | |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 21 | /* |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 22 | * Returns true if the provided granule size is supported, false otherwise. |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 23 | */ |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 24 | bool xlat_arch_is_granule_size_supported(size_t size) |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 25 | { |
| 26 | /* |
Antonio Nino Diaz | 0842bd6 | 2018-07-12 15:54:10 +0100 | [diff] [blame] | 27 | * The library uses the long descriptor translation table format, which |
| 28 | * supports 4 KiB pages only. |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 29 | */ |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 30 | return size == PAGE_SIZE_4KB; |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 31 | } |
| 32 | |
| 33 | size_t xlat_arch_get_max_supported_granule_size(void) |
| 34 | { |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 35 | return PAGE_SIZE_4KB; |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 36 | } |
| 37 | |
Antonio Nino Diaz | 3759e3f | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 38 | #if ENABLE_ASSERTIONS |
Sandrine Bailleux | c5b6377 | 2017-05-31 13:31:48 +0100 | [diff] [blame] | 39 | unsigned long long xlat_arch_get_max_supported_pa(void) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 40 | { |
| 41 | /* Physical address space size for long descriptor format. */ |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 42 | return (1ULL << 40) - 1ULL; |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 43 | } |
Antonio Nino Diaz | 3759e3f | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 44 | #endif /* ENABLE_ASSERTIONS*/ |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 45 | |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 46 | bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 47 | { |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 48 | if (ctx->xlat_regime == EL1_EL0_REGIME) { |
| 49 | assert(xlat_arch_current_el() == 1U); |
| 50 | return (read_sctlr() & SCTLR_M_BIT) != 0U; |
| 51 | } else { |
| 52 | assert(ctx->xlat_regime == EL2_REGIME); |
| 53 | assert(xlat_arch_current_el() == 2U); |
| 54 | return (read_hsctlr() & HSCTLR_M_BIT) != 0U; |
| 55 | } |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 56 | } |
| 57 | |
Antonio Nino Diaz | 37a5efa | 2018-08-07 12:47:12 +0100 | [diff] [blame] | 58 | bool is_dcache_enabled(void) |
| 59 | { |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 60 | if (IS_IN_EL2()) { |
| 61 | return (read_hsctlr() & HSCTLR_C_BIT) != 0U; |
| 62 | } else { |
| 63 | return (read_sctlr() & SCTLR_C_BIT) != 0U; |
| 64 | } |
Antonio Nino Diaz | 37a5efa | 2018-08-07 12:47:12 +0100 | [diff] [blame] | 65 | } |
| 66 | |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 67 | uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime) |
Antonio Nino Diaz | 44d3c21 | 2018-07-05 08:11:48 +0100 | [diff] [blame] | 68 | { |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 69 | if (xlat_regime == EL1_EL0_REGIME) { |
| 70 | return UPPER_ATTRS(XN) | UPPER_ATTRS(PXN); |
| 71 | } else { |
| 72 | assert(xlat_regime == EL2_REGIME); |
| 73 | return UPPER_ATTRS(XN); |
| 74 | } |
Antonio Nino Diaz | 44d3c21 | 2018-07-05 08:11:48 +0100 | [diff] [blame] | 75 | } |
| 76 | |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 77 | void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime) |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 78 | { |
| 79 | /* |
| 80 | * Ensure the translation table write has drained into memory before |
| 81 | * invalidating the TLB entry. |
| 82 | */ |
| 83 | dsbishst(); |
| 84 | |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 85 | if (xlat_regime == EL1_EL0_REGIME) { |
| 86 | tlbimvaais(TLBI_ADDR(va)); |
| 87 | } else { |
| 88 | assert(xlat_regime == EL2_REGIME); |
| 89 | tlbimvahis(TLBI_ADDR(va)); |
| 90 | } |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 91 | } |
| 92 | |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 93 | void xlat_arch_tlbi_va_sync(void) |
| 94 | { |
| 95 | /* Invalidate all entries from branch predictors. */ |
| 96 | bpiallis(); |
| 97 | |
| 98 | /* |
| 99 | * A TLB maintenance instruction can complete at any time after |
| 100 | * it is issued, but is only guaranteed to be complete after the |
| 101 | * execution of DSB by the PE that executed the TLB maintenance |
| 102 | * instruction. After the TLB invalidate instruction is |
| 103 | * complete, no new memory accesses using the invalidated TLB |
| 104 | * entries will be observed by any observer of the system |
| 105 | * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph |
| 106 | * "Ordering and completion of TLB maintenance instructions". |
| 107 | */ |
| 108 | dsbish(); |
| 109 | |
| 110 | /* |
| 111 | * The effects of a completed TLB maintenance instruction are |
| 112 | * only guaranteed to be visible on the PE that executed the |
| 113 | * instruction after the execution of an ISB instruction by the |
| 114 | * PE that executed the TLB maintenance instruction. |
| 115 | */ |
| 116 | isb(); |
| 117 | } |
| 118 | |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 119 | unsigned int xlat_arch_current_el(void) |
Antonio Nino Diaz | efabaa9 | 2017-04-27 13:30:22 +0100 | [diff] [blame] | 120 | { |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 121 | if (IS_IN_HYP()) { |
| 122 | return 2U; |
| 123 | } else { |
| 124 | assert(IS_IN_SVC() || IS_IN_MON()); |
| 125 | /* |
| 126 | * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, |
| 127 | * System, SVC, Abort, UND, IRQ and FIQ modes) execute at EL3. |
| 128 | * |
| 129 | * The PL1&0 translation regime in AArch32 behaves like the |
| 130 | * EL1&0 regime in AArch64 except for the XN bits, but we set |
| 131 | * and unset them at the same time, so there's no difference in |
| 132 | * practice. |
| 133 | */ |
| 134 | return 1U; |
| 135 | } |
Antonio Nino Diaz | efabaa9 | 2017-04-27 13:30:22 +0100 | [diff] [blame] | 136 | } |
| 137 | |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 138 | /******************************************************************************* |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 139 | * Function for enabling the MMU in PL1 or PL2, assuming that the page tables |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 140 | * have already been created. |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 141 | ******************************************************************************/ |
Antonio Nino Diaz | 67f799e | 2018-07-15 16:42:01 +0100 | [diff] [blame] | 142 | void setup_mmu_cfg(uint64_t *params, unsigned int flags, |
| 143 | const uint64_t *base_table, unsigned long long max_pa, |
| 144 | uintptr_t max_va, __unused int xlat_regime) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 145 | { |
Antonio Nino Diaz | 668d9ee | 2018-07-12 15:44:42 +0100 | [diff] [blame] | 146 | uint64_t mair, ttbr0; |
| 147 | uint32_t ttbcr; |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 148 | |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 149 | /* Set attributes in the right indices of the MAIR */ |
Antonio Nino Diaz | 668d9ee | 2018-07-12 15:44:42 +0100 | [diff] [blame] | 150 | mair = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); |
| 151 | mair |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 152 | ATTR_IWBWA_OWBWA_NTR_INDEX); |
Antonio Nino Diaz | 668d9ee | 2018-07-12 15:44:42 +0100 | [diff] [blame] | 153 | mair |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 154 | ATTR_NON_CACHEABLE_INDEX); |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 155 | |
| 156 | /* |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 157 | * Configure the control register for stage 1 of the PL1&0 or EL2 |
| 158 | * translation regimes. |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 159 | */ |
| 160 | |
| 161 | /* Use the Long-descriptor translation table format. */ |
| 162 | ttbcr = TTBCR_EAE_BIT; |
| 163 | |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 164 | if (xlat_regime == EL1_EL0_REGIME) { |
| 165 | assert(IS_IN_SVC() || IS_IN_MON()); |
| 166 | /* |
| 167 | * Disable translation table walk for addresses that are |
| 168 | * translated using TTBR1. Therefore, only TTBR0 is used. |
| 169 | */ |
| 170 | ttbcr |= TTBCR_EPD1_BIT; |
| 171 | } else { |
| 172 | assert(xlat_regime == EL2_REGIME); |
| 173 | assert(IS_IN_HYP()); |
| 174 | |
| 175 | /* |
| 176 | * Set HTCR bits as well. Set HTTBR table properties |
| 177 | * as Inner & outer WBWA & shareable. |
| 178 | */ |
| 179 | ttbcr |= HTCR_RES1 | |
| 180 | HTCR_SH0_INNER_SHAREABLE | HTCR_RGN0_OUTER_WBA | |
| 181 | HTCR_RGN0_INNER_WBA; |
| 182 | } |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 183 | |
| 184 | /* |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 185 | * Limit the input address ranges and memory region sizes translated |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 186 | * using TTBR0 to the given virtual address space size, if smaller than |
| 187 | * 32 bits. |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 188 | */ |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 189 | if (max_va != UINT32_MAX) { |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 190 | uintptr_t virtual_addr_space_size = max_va + 1U; |
| 191 | |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 192 | assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); |
| 193 | /* |
Sandrine Bailleux | 12e8644 | 2017-07-19 10:11:13 +0100 | [diff] [blame] | 194 | * __builtin_ctzll(0) is undefined but here we are guaranteed |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 195 | * that virtual_addr_space_size is in the range [1, UINT32_MAX]. |
| 196 | */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 197 | int t0sz = 32 - __builtin_ctzll(virtual_addr_space_size); |
| 198 | |
| 199 | ttbcr |= (uint32_t) t0sz; |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 200 | } |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 201 | |
| 202 | /* |
| 203 | * Set the cacheability and shareability attributes for memory |
| 204 | * associated with translation table walks using TTBR0. |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 205 | */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 206 | if ((flags & XLAT_TABLE_NC) != 0U) { |
Summer Qin | daf5dbb | 2017-03-16 17:16:34 +0000 | [diff] [blame] | 207 | /* Inner & outer non-cacheable non-shareable. */ |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 208 | ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | |
| 209 | TTBCR_RGN0_INNER_NC; |
Summer Qin | daf5dbb | 2017-03-16 17:16:34 +0000 | [diff] [blame] | 210 | } else { |
| 211 | /* Inner & outer WBWA & shareable. */ |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 212 | ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | |
| 213 | TTBCR_RGN0_INNER_WBA; |
Summer Qin | daf5dbb | 2017-03-16 17:16:34 +0000 | [diff] [blame] | 214 | } |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 215 | |
| 216 | /* Set TTBR0 bits as well */ |
| 217 | ttbr0 = (uint64_t)(uintptr_t) base_table; |
Antonio Nino Diaz | 668d9ee | 2018-07-12 15:44:42 +0100 | [diff] [blame] | 218 | |
Isla Mitchell | c4a1a07 | 2017-08-07 11:20:13 +0100 | [diff] [blame] | 219 | #if ARM_ARCH_AT_LEAST(8, 2) |
| 220 | /* |
Antonio Nino Diaz | 668d9ee | 2018-07-12 15:44:42 +0100 | [diff] [blame] | 221 | * Enable CnP bit so as to share page tables with all PEs. This |
| 222 | * is mandatory for ARMv8.2 implementations. |
Isla Mitchell | c4a1a07 | 2017-08-07 11:20:13 +0100 | [diff] [blame] | 223 | */ |
| 224 | ttbr0 |= TTBR_CNP_BIT; |
| 225 | #endif |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 226 | |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 227 | /* Now populate MMU configuration */ |
Antonio Nino Diaz | 67f799e | 2018-07-15 16:42:01 +0100 | [diff] [blame] | 228 | params[MMU_CFG_MAIR] = mair; |
| 229 | params[MMU_CFG_TCR] = (uint64_t) ttbcr; |
| 230 | params[MMU_CFG_TTBR0] = ttbr0; |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 231 | } |