Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame^] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <assert.h> |
| 10 | #include <cassert.h> |
| 11 | #include <platform_def.h> |
| 12 | #include <utils.h> |
| 13 | #include <xlat_tables_v2.h> |
| 14 | #include "../xlat_tables_private.h" |
| 15 | |
Antonio Nino Diaz | 3759e3f | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 16 | #if ENABLE_ASSERTIONS |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 17 | static unsigned long long xlat_arch_get_max_supported_pa(void) |
| 18 | { |
| 19 | /* Physical address space size for long descriptor format. */ |
| 20 | return (1ull << 40) - 1ull; |
| 21 | } |
Antonio Nino Diaz | 3759e3f | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 22 | #endif /* ENABLE_ASSERTIONS*/ |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 23 | |
| 24 | int is_mmu_enabled(void) |
| 25 | { |
| 26 | return (read_sctlr() & SCTLR_M_BIT) != 0; |
| 27 | } |
| 28 | |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 29 | #if PLAT_XLAT_TABLES_DYNAMIC |
| 30 | |
| 31 | void xlat_arch_tlbi_va(uintptr_t va) |
| 32 | { |
| 33 | /* |
| 34 | * Ensure the translation table write has drained into memory before |
| 35 | * invalidating the TLB entry. |
| 36 | */ |
| 37 | dsbishst(); |
| 38 | |
| 39 | tlbimvaais(TLBI_ADDR(va)); |
| 40 | } |
| 41 | |
| 42 | void xlat_arch_tlbi_va_sync(void) |
| 43 | { |
| 44 | /* Invalidate all entries from branch predictors. */ |
| 45 | bpiallis(); |
| 46 | |
| 47 | /* |
| 48 | * A TLB maintenance instruction can complete at any time after |
| 49 | * it is issued, but is only guaranteed to be complete after the |
| 50 | * execution of DSB by the PE that executed the TLB maintenance |
| 51 | * instruction. After the TLB invalidate instruction is |
| 52 | * complete, no new memory accesses using the invalidated TLB |
| 53 | * entries will be observed by any observer of the system |
| 54 | * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph |
| 55 | * "Ordering and completion of TLB maintenance instructions". |
| 56 | */ |
| 57 | dsbish(); |
| 58 | |
| 59 | /* |
| 60 | * The effects of a completed TLB maintenance instruction are |
| 61 | * only guaranteed to be visible on the PE that executed the |
| 62 | * instruction after the execution of an ISB instruction by the |
| 63 | * PE that executed the TLB maintenance instruction. |
| 64 | */ |
| 65 | isb(); |
| 66 | } |
| 67 | |
| 68 | #endif /* PLAT_XLAT_TABLES_DYNAMIC */ |
| 69 | |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 70 | void init_xlat_tables_arch(unsigned long long max_pa) |
| 71 | { |
| 72 | assert((PLAT_PHY_ADDR_SPACE_SIZE - 1) <= |
| 73 | xlat_arch_get_max_supported_pa()); |
| 74 | } |
| 75 | |
| 76 | /******************************************************************************* |
| 77 | * Function for enabling the MMU in Secure PL1, assuming that the |
| 78 | * page-tables have already been created. |
| 79 | ******************************************************************************/ |
| 80 | void enable_mmu_internal_secure(unsigned int flags, uint64_t *base_table) |
| 81 | |
| 82 | { |
| 83 | u_register_t mair0, ttbcr, sctlr; |
| 84 | uint64_t ttbr0; |
| 85 | |
| 86 | assert(IS_IN_SECURE()); |
| 87 | assert((read_sctlr() & SCTLR_M_BIT) == 0); |
| 88 | |
| 89 | /* Invalidate TLBs at the current exception level */ |
| 90 | tlbiall(); |
| 91 | |
| 92 | /* Set attributes in the right indices of the MAIR */ |
| 93 | mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); |
| 94 | mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, |
| 95 | ATTR_IWBWA_OWBWA_NTR_INDEX); |
| 96 | mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, |
| 97 | ATTR_NON_CACHEABLE_INDEX); |
| 98 | write_mair0(mair0); |
| 99 | |
| 100 | /* |
Summer Qin | daf5dbb | 2017-03-16 17:16:34 +0000 | [diff] [blame] | 101 | * Set TTBCR bits as well. Set TTBR0 table properties. Disable TTBR1. |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 102 | */ |
Summer Qin | daf5dbb | 2017-03-16 17:16:34 +0000 | [diff] [blame] | 103 | if (flags & XLAT_TABLE_NC) { |
| 104 | /* Inner & outer non-cacheable non-shareable. */ |
| 105 | ttbcr = TTBCR_EAE_BIT | |
| 106 | TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | |
| 107 | TTBCR_RGN0_INNER_NC | |
| 108 | (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE)); |
| 109 | } else { |
| 110 | /* Inner & outer WBWA & shareable. */ |
| 111 | ttbcr = TTBCR_EAE_BIT | |
| 112 | TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | |
| 113 | TTBCR_RGN0_INNER_WBA | |
| 114 | (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE)); |
| 115 | } |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 116 | ttbcr |= TTBCR_EPD1_BIT; |
| 117 | write_ttbcr(ttbcr); |
| 118 | |
| 119 | /* Set TTBR0 bits as well */ |
| 120 | ttbr0 = (uint64_t)(uintptr_t) base_table; |
| 121 | write64_ttbr0(ttbr0); |
| 122 | write64_ttbr1(0); |
| 123 | |
| 124 | /* |
| 125 | * Ensure all translation table writes have drained |
| 126 | * into memory, the TLB invalidation is complete, |
| 127 | * and translation register writes are committed |
| 128 | * before enabling the MMU |
| 129 | */ |
| 130 | dsb(); |
| 131 | isb(); |
| 132 | |
| 133 | sctlr = read_sctlr(); |
| 134 | sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; |
| 135 | |
| 136 | if (flags & DISABLE_DCACHE) |
| 137 | sctlr &= ~SCTLR_C_BIT; |
| 138 | else |
| 139 | sctlr |= SCTLR_C_BIT; |
| 140 | |
| 141 | write_sctlr(sctlr); |
| 142 | |
| 143 | /* Ensure the MMU enable takes effect immediately */ |
| 144 | isb(); |
| 145 | } |
| 146 | |
| 147 | void enable_mmu_arch(unsigned int flags, uint64_t *base_table) |
| 148 | { |
| 149 | enable_mmu_internal_secure(flags, base_table); |
| 150 | } |