Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
| 33 | #include <assert.h> |
| 34 | #include <cassert.h> |
| 35 | #include <platform_def.h> |
| 36 | #include <utils.h> |
| 37 | #include <xlat_tables_v2.h> |
| 38 | #include "../xlat_tables_private.h" |
| 39 | |
| 40 | #if DEBUG |
| 41 | static unsigned long long xlat_arch_get_max_supported_pa(void) |
| 42 | { |
| 43 | /* Physical address space size for long descriptor format. */ |
| 44 | return (1ull << 40) - 1ull; |
| 45 | } |
| 46 | #endif /* DEBUG*/ |
| 47 | |
| 48 | int is_mmu_enabled(void) |
| 49 | { |
| 50 | return (read_sctlr() & SCTLR_M_BIT) != 0; |
| 51 | } |
| 52 | |
| 53 | void init_xlat_tables_arch(unsigned long long max_pa) |
| 54 | { |
| 55 | assert((PLAT_PHY_ADDR_SPACE_SIZE - 1) <= |
| 56 | xlat_arch_get_max_supported_pa()); |
| 57 | } |
| 58 | |
| 59 | /******************************************************************************* |
| 60 | * Function for enabling the MMU in Secure PL1, assuming that the |
| 61 | * page-tables have already been created. |
| 62 | ******************************************************************************/ |
| 63 | void enable_mmu_internal_secure(unsigned int flags, uint64_t *base_table) |
| 64 | |
| 65 | { |
| 66 | u_register_t mair0, ttbcr, sctlr; |
| 67 | uint64_t ttbr0; |
| 68 | |
| 69 | assert(IS_IN_SECURE()); |
| 70 | assert((read_sctlr() & SCTLR_M_BIT) == 0); |
| 71 | |
| 72 | /* Invalidate TLBs at the current exception level */ |
| 73 | tlbiall(); |
| 74 | |
| 75 | /* Set attributes in the right indices of the MAIR */ |
| 76 | mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); |
| 77 | mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, |
| 78 | ATTR_IWBWA_OWBWA_NTR_INDEX); |
| 79 | mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, |
| 80 | ATTR_NON_CACHEABLE_INDEX); |
| 81 | write_mair0(mair0); |
| 82 | |
| 83 | /* |
| 84 | * Set TTBCR bits as well. Set TTBR0 table properties as Inner |
| 85 | * & outer WBWA & shareable. Disable TTBR1. |
| 86 | */ |
| 87 | ttbcr = TTBCR_EAE_BIT | |
| 88 | TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | |
| 89 | TTBCR_RGN0_INNER_WBA | |
| 90 | (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE)); |
| 91 | ttbcr |= TTBCR_EPD1_BIT; |
| 92 | write_ttbcr(ttbcr); |
| 93 | |
| 94 | /* Set TTBR0 bits as well */ |
| 95 | ttbr0 = (uint64_t)(uintptr_t) base_table; |
| 96 | write64_ttbr0(ttbr0); |
| 97 | write64_ttbr1(0); |
| 98 | |
| 99 | /* |
| 100 | * Ensure all translation table writes have drained |
| 101 | * into memory, the TLB invalidation is complete, |
| 102 | * and translation register writes are committed |
| 103 | * before enabling the MMU |
| 104 | */ |
| 105 | dsb(); |
| 106 | isb(); |
| 107 | |
| 108 | sctlr = read_sctlr(); |
| 109 | sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; |
| 110 | |
| 111 | if (flags & DISABLE_DCACHE) |
| 112 | sctlr &= ~SCTLR_C_BIT; |
| 113 | else |
| 114 | sctlr |= SCTLR_C_BIT; |
| 115 | |
| 116 | write_sctlr(sctlr); |
| 117 | |
| 118 | /* Ensure the MMU enable takes effect immediately */ |
| 119 | isb(); |
| 120 | } |
| 121 | |
| 122 | void enable_mmu_arch(unsigned int flags, uint64_t *base_table) |
| 123 | { |
| 124 | enable_mmu_internal_secure(flags, base_table); |
| 125 | } |