Pritesh Raithatha | 8a45c72 | 2017-12-15 15:00:09 -0800 | [diff] [blame] | 1 | /* |
Varun Wadekar | 2909fa3 | 2020-01-09 08:52:10 -0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved. |
Pritesh Raithatha | 8a45c72 | 2017-12-15 15:00:09 -0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Varun Wadekar | 2909fa3 | 2020-01-09 08:52:10 -0800 | [diff] [blame] | 7 | #ifndef TEGRA_MC_DEF_H |
| 8 | #define TEGRA_MC_DEF_H |
Pritesh Raithatha | 8a45c72 | 2017-12-15 15:00:09 -0800 | [diff] [blame] | 9 | |
| 10 | /******************************************************************************* |
| 11 | * Memory Controller Order_id registers |
| 12 | ******************************************************************************/ |
| 13 | #define MC_CLIENT_ORDER_ID_9 U(0x2a24) |
| 14 | #define MC_CLIENT_ORDER_ID_9_RESET_VAL 0x00000000U |
| 15 | #define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_MASK (0x3U << 12) |
| 16 | #define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_ORDER_ID (3U << 12) |
| 17 | |
| 18 | #define MC_CLIENT_ORDER_ID_27 U(0x2a6c) |
| 19 | #define MC_CLIENT_ORDER_ID_27_RESET_VAL 0x00000000U |
| 20 | #define MC_CLIENT_ORDER_ID_27_PCIE0W_MASK (0x3U << 4) |
Puneet Saxena | 5b526df | 2018-01-05 07:04:35 -0800 | [diff] [blame] | 21 | #define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (2U << 4) |
Pritesh Raithatha | 8a45c72 | 2017-12-15 15:00:09 -0800 | [diff] [blame] | 22 | |
| 23 | #define MC_CLIENT_ORDER_ID_28 U(0x2a70) |
| 24 | #define MC_CLIENT_ORDER_ID_28_RESET_VAL 0x00000000U |
| 25 | #define MC_CLIENT_ORDER_ID_28_PCIE4W_MASK (0x3U << 4) |
| 26 | #define MC_CLIENT_ORDER_ID_28_PCIE4W_ORDER_ID (3U << 4) |
| 27 | #define MC_CLIENT_ORDER_ID_28_PCIE5W_MASK (0x3U << 12) |
Puneet Saxena | 5b526df | 2018-01-05 07:04:35 -0800 | [diff] [blame] | 28 | #define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (1U << 12) |
Pritesh Raithatha | 8a45c72 | 2017-12-15 15:00:09 -0800 | [diff] [blame] | 29 | |
Krishna Reddy | a1673b3 | 2017-12-17 16:21:47 -0800 | [diff] [blame] | 30 | #define mc_client_order_id(val, id, client) \ |
| 31 | ((val & ~MC_CLIENT_ORDER_ID_##id##_##client##_MASK) | \ |
Pritesh Raithatha | 8a45c72 | 2017-12-15 15:00:09 -0800 | [diff] [blame] | 32 | MC_CLIENT_ORDER_ID_##id##_##client##_ORDER_ID) |
| 33 | |
| 34 | /******************************************************************************* |
| 35 | * Memory Controller's VC ID configuration registers |
| 36 | ******************************************************************************/ |
| 37 | #define VC_NISO 0U |
| 38 | #define VC_SISO 1U |
| 39 | #define VC_ISO 2U |
| 40 | |
| 41 | #define MC_HUB_PC_VC_ID_0 U(0x2a78) |
| 42 | #define MC_HUB_PC_VC_ID_0_RESET_VAL 0x00020100U |
| 43 | #define MC_HUB_PC_VC_ID_0_APB_VC_ID_MASK (0x3U << 8) |
| 44 | #define MC_HUB_PC_VC_ID_0_APB_VC_ID (VC_NISO << 8) |
| 45 | |
| 46 | #define MC_HUB_PC_VC_ID_2 U(0x2a80) |
| 47 | #define MC_HUB_PC_VC_ID_2_RESET_VAL 0x10001000U |
| 48 | #define MC_HUB_PC_VC_ID_2_SD_VC_ID_MASK (0x3U << 28) |
| 49 | #define MC_HUB_PC_VC_ID_2_SD_VC_ID (VC_NISO << 28) |
| 50 | |
| 51 | #define MC_HUB_PC_VC_ID_4 U(0x2a88) |
| 52 | #define MC_HUB_PC_VC_ID_4_RESET_VAL 0x10020011U |
| 53 | #define MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK (0x3U << 28) |
| 54 | #define MC_HUB_PC_VC_ID_4_NIC_VC_ID (VC_NISO << 28) |
| 55 | |
Puneet Saxena | 5b526df | 2018-01-05 07:04:35 -0800 | [diff] [blame] | 56 | #define MC_HUB_PC_VC_ID_12 U(0x2aa8) |
| 57 | #define MC_HUB_PC_VC_ID_12_RESET_VAL 0x11001011U |
| 58 | #define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID_MASK (0x3U << 12) |
| 59 | #define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID (VC_NISO << 12) |
| 60 | |
Krishna Reddy | 3d8d2ab | 2017-12-22 20:17:09 -0800 | [diff] [blame] | 61 | #define mc_hub_vc_id(val, id, client) \ |
| 62 | ((val & ~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK) | \ |
Pritesh Raithatha | 8a45c72 | 2017-12-15 15:00:09 -0800 | [diff] [blame] | 63 | MC_HUB_PC_VC_ID_##id##_##client##_VC_ID) |
| 64 | |
| 65 | /******************************************************************************* |
| 66 | * Memory Controller's PCFIFO client configuration registers |
| 67 | ******************************************************************************/ |
| 68 | #define MC_PCFIFO_CLIENT_CONFIG0 0xdd0U |
| 69 | |
| 70 | #define MC_PCFIFO_CLIENT_CONFIG1 0xdd4U |
| 71 | #define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20200000U |
| 72 | #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0U << 17) |
| 73 | #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1U << 17) |
| 74 | #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0U << 21) |
| 75 | #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1U << 21) |
| 76 | #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0U << 29) |
| 77 | #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_ORDERED (1U << 29) |
| 78 | #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1U << 29) |
| 79 | |
| 80 | #define MC_PCFIFO_CLIENT_CONFIG2 0xdd8U |
| 81 | #define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x00002800U |
| 82 | #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0U << 11) |
| 83 | #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1U << 11) |
| 84 | #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0U << 13) |
| 85 | #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_ORDERED (1U << 13) |
| 86 | #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1U << 13) |
| 87 | #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_UNORDERED (0U << 21) |
| 88 | #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_MASK (1U << 21) |
| 89 | |
| 90 | #define MC_PCFIFO_CLIENT_CONFIG3 0xddcU |
| 91 | #define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0x08000080U |
| 92 | #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_UNORDERED (0U << 4) |
| 93 | #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_MASK (1U << 4) |
| 94 | #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_UNORDERED (0U << 6) |
| 95 | #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_MASK (1U << 6) |
| 96 | #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0U << 7) |
| 97 | #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1U << 7) |
| 98 | #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_UNORDERED (0U << 13) |
| 99 | #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_MASK (1U << 13) |
| 100 | #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_UNORDERED (0U << 27) |
| 101 | #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_MASK (1U << 27) |
| 102 | |
| 103 | #define MC_PCFIFO_CLIENT_CONFIG4 0xde0U |
| 104 | #define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0x5552a022U |
| 105 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0U << 1) |
| 106 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1U << 1) |
| 107 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0U << 5) |
| 108 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1U << 5) |
| 109 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_UNORDERED (0U << 7) |
| 110 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_MASK (1U << 7) |
| 111 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0U << 13) |
| 112 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1U << 13) |
Puneet Saxena | 5b526df | 2018-01-05 07:04:35 -0800 | [diff] [blame] | 113 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0U << 15) |
Pritesh Raithatha | 8a45c72 | 2017-12-15 15:00:09 -0800 | [diff] [blame] | 114 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1U << 15) |
| 115 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0U << 17) |
| 116 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1U << 17) |
| 117 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_UNORDERED (0U << 20) |
| 118 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_MASK (1U << 20) |
| 119 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0U << 22) |
| 120 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1U << 22) |
| 121 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_UNORDERED (0U << 24) |
| 122 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_MASK (1U << 24) |
| 123 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0U << 26) |
| 124 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1U << 26) |
| 125 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_UNORDERED (0U << 28) |
| 126 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_MASK (1U << 28) |
| 127 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0U << 30) |
| 128 | #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1U << 30) |
| 129 | |
| 130 | #define MC_PCFIFO_CLIENT_CONFIG5 0xbf4U |
| 131 | #define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0x20000001U |
| 132 | #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0U << 0) |
| 133 | #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1U << 0) |
| 134 | #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_UNORDERED (0U << 30) |
| 135 | #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_MASK (1U << 30) |
| 136 | |
| 137 | #define MC_PCFIFO_CLIENT_CONFIG6 0xb90U |
| 138 | #define MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL 0xaa280000U |
| 139 | #define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_UNORDERED (0U << 19) |
| 140 | #define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_MASK (1U << 19) |
| 141 | #define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_UNORDERED (0U << 21) |
| 142 | #define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_MASK (1U << 21) |
| 143 | #define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_UNORDERED (0U << 25) |
| 144 | #define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_MASK (1U << 25) |
| 145 | #define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_ORDERED (1U << 27) |
| 146 | #define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_MASK (1U << 27) |
| 147 | #define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_ORDERED (1U << 29) |
| 148 | #define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_MASK (1U << 29) |
| 149 | #define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_ORDERED (1U << 31) |
| 150 | #define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_MASK (1U << 31) |
| 151 | |
| 152 | #define MC_PCFIFO_CLIENT_CONFIG7 0xaccU |
| 153 | #define MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL 0x0000000aU |
| 154 | #define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_UNORDERED (0U << 1) |
| 155 | #define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_MASK (1U << 1) |
| 156 | #define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_UNORDERED (0U << 3) |
| 157 | #define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_MASK (1U << 3) |
| 158 | |
| 159 | /******************************************************************************* |
| 160 | * StreamID to indicate no SMMU translations (requests to be steered on the |
| 161 | * SMMU bypass path) |
| 162 | ******************************************************************************/ |
| 163 | #define MC_STREAM_ID_MAX 0x7FU |
| 164 | |
| 165 | /******************************************************************************* |
| 166 | * Stream ID Override Config registers |
| 167 | ******************************************************************************/ |
| 168 | #define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U |
| 169 | #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xe0U |
| 170 | #define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3f8U |
| 171 | #define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U |
| 172 | #define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U |
| 173 | #define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5f0U |
| 174 | #define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498U |
| 175 | #define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4f8U |
| 176 | #define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460U |
| 177 | #define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2a0U |
| 178 | #define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5f8U |
| 179 | #define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U |
| 180 | #define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1c8U |
| 181 | #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U |
| 182 | #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250U |
| 183 | #define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U |
| 184 | #define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U |
| 185 | #define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6d8U |
| 186 | #define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U |
| 187 | #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258U |
| 188 | #define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U |
| 189 | #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338U |
| 190 | #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1e8U |
| 191 | #define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U |
| 192 | #define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6f0U |
| 193 | #define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U |
| 194 | #define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4e8U |
| 195 | #define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xb0U |
| 196 | #define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320U |
| 197 | #define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U |
| 198 | #define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500U |
| 199 | #define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6e8U |
| 200 | #define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408U |
| 201 | #define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U |
| 202 | #define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468U |
| 203 | #define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U |
| 204 | #define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4d0U |
| 205 | #define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438U |
| 206 | #define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238U |
| 207 | #define MC_STREAMID_OVERRIDE_CFG_HDAR 0xa8U |
| 208 | #define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300U |
| 209 | #define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428U |
| 210 | #define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6a8U |
| 211 | #define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2a8U |
| 212 | #define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420U |
| 213 | #define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310U |
| 214 | #define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3f0U |
| 215 | #define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4c8U |
| 216 | #define MC_STREAMID_OVERRIDE_CFG_SCER 0x4d8U |
| 217 | #define MC_STREAMID_OVERRIDE_CFG_MIU5W 0x7e8U |
| 218 | #define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6b0U |
| 219 | #define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U |
| 220 | #define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230U |
| 221 | #define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6c8U |
| 222 | #define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U |
| 223 | #define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U |
| 224 | #define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368U |
| 225 | #define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400U |
| 226 | #define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330U |
| 227 | #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318U |
| 228 | #define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U |
| 229 | #define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478U |
| 230 | #define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6a0U |
| 231 | #define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U |
| 232 | #define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3c8U |
| 233 | #define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480U |
| 234 | #define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U |
| 235 | #define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360U |
| 236 | #define MC_STREAMID_OVERRIDE_CFG_APER 0x3d0U |
| 237 | #define MC_STREAMID_OVERRIDE_CFG_MIU7R 0x8U |
| 238 | #define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7c8U |
| 239 | #define MC_STREAMID_OVERRIDE_CFG_MIU7W 0x10U |
| 240 | #define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U |
| 241 | #define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U |
| 242 | #define MC_STREAMID_OVERRIDE_CFG_AONW 0x4c0U |
| 243 | #define MC_STREAMID_OVERRIDE_CFG_MIU4W 0x598U |
| 244 | #define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1a8U |
| 245 | #define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4a0U |
| 246 | #define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U |
| 247 | #define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U |
| 248 | #define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U |
| 249 | #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508U |
| 250 | #define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510U |
| 251 | #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4b0U |
| 252 | #define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7d8U |
| 253 | #define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U |
| 254 | #define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U |
| 255 | #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260U |
| 256 | #define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488U |
| 257 | #define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U |
| 258 | #define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U |
| 259 | #define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U |
| 260 | #define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6b8U |
| 261 | #define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6c0U |
| 262 | #define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6f8U |
| 263 | #define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U |
| 264 | #define MC_STREAMID_OVERRIDE_CFG_MIU6W 0x7f8U |
| 265 | #define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6d0U |
| 266 | #define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7d0U |
| 267 | #define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U |
| 268 | #define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U |
| 269 | #define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U |
| 270 | #define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U |
| 271 | #define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138U |
| 272 | #define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U |
| 273 | #define MC_STREAMID_OVERRIDE_CFG_AONR 0x4b8U |
| 274 | #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4a8U |
| 275 | #define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U |
| 276 | #define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5e8U |
| 277 | #define MC_STREAMID_OVERRIDE_CFG_MIU6R 0x7f0U |
| 278 | #define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470U |
| 279 | #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3c0U |
| 280 | #define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430U |
| 281 | #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518U |
| 282 | #define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U |
| 283 | #define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U |
| 284 | #define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4f0U |
| 285 | #define MC_STREAMID_OVERRIDE_CFG_APEW 0x3d8U |
| 286 | #define MC_STREAMID_OVERRIDE_CFG_MIU5R 0x7e0U |
| 287 | #define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U |
| 288 | #define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U |
| 289 | #define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U |
| 290 | #define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0U |
| 291 | #define MC_STREAMID_OVERRIDE_CFG_MIU4R 0x590U |
| 292 | #define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220U |
| 293 | #define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5e0U |
| 294 | #define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6e0U |
| 295 | #define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U |
| 296 | #define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U |
| 297 | #define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4e0U |
| 298 | #define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U |
| 299 | #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268U |
| 300 | #define MC_STREAMID_OVERRIDE_CFG_SATAR 0xf8U |
| 301 | #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490U |
| 302 | #define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U |
| 303 | #define MC_STREAMID_OVERRIDE_CFG_VIW 0x390U |
| 304 | #define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158U |
| 305 | #define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U |
| 306 | |
| 307 | /******************************************************************************* |
| 308 | * Macro to calculate Security cfg register addr from StreamID Override register |
| 309 | ******************************************************************************/ |
| 310 | #define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t)) |
| 311 | |
| 312 | #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0U << 4) |
| 313 | #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1U << 4) |
| 314 | #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2U << 4) |
| 315 | #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3U << 4) |
| 316 | |
| 317 | #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0U << 8) |
| 318 | #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1U << 8) |
| 319 | #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2U << 8) |
| 320 | #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3U << 8) |
| 321 | |
| 322 | #define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0U << 12) |
| 323 | #define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1U << 12) |
| 324 | |
| 325 | /******************************************************************************* |
| 326 | * Memory Controller transaction override config registers |
| 327 | ******************************************************************************/ |
| 328 | #define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8U |
| 329 | #define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624U |
| 330 | #define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16dcU |
| 331 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644U |
| 332 | #define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000U |
| 333 | #define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478U |
| 334 | #define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8U |
| 335 | #define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162cU |
| 336 | #define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460U |
| 337 | #define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654U |
| 338 | #define MC_TXN_OVERRIDE_CONFIG_MIU6R 0x17f4U |
| 339 | #define MC_TXN_OVERRIDE_CONFIG_MIU5R 0x17e4U |
| 340 | #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784U |
| 341 | #define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16c4U |
| 342 | #define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470U |
| 343 | #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0U |
| 344 | #define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178cU |
| 345 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774U |
| 346 | #define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16bcU |
| 347 | #define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510U |
| 348 | #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8U |
| 349 | #define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390U |
| 350 | #define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714U |
| 351 | #define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468U |
| 352 | #define MC_TXN_OVERRIDE_CONFIG_MIU6W 0x17fcU |
| 353 | #define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480U |
| 354 | #define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179cU |
| 355 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764U |
| 356 | #define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8U |
| 357 | #define MC_TXN_OVERRIDE_CONFIG_MIU7R 0x1008U |
| 358 | #define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8U |
| 359 | #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258U |
| 360 | #define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15f4U |
| 361 | #define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438U |
| 362 | #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17dcU |
| 363 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176cU |
| 364 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166cU |
| 365 | #define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0U |
| 366 | #define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0U |
| 367 | #define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420U |
| 368 | #define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16ecU |
| 369 | #define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16d4U |
| 370 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674U |
| 371 | #define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164cU |
| 372 | #define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430U |
| 373 | #define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548U |
| 374 | #define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16ccU |
| 375 | #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17ccU |
| 376 | #define MC_TXN_OVERRIDE_CONFIG_MIU7W 0x1010U |
| 377 | #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518U |
| 378 | #define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580U |
| 379 | #define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158cU |
| 380 | #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250U |
| 381 | #define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400U |
| 382 | #define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8U |
| 383 | #define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138U |
| 384 | #define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320U |
| 385 | #define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8U |
| 386 | #define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8U |
| 387 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634U |
| 388 | #define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8U |
| 389 | #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338U |
| 390 | #define MC_TXN_OVERRIDE_CONFIG_ISPFALR 0x1228U |
| 391 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175cU |
| 392 | #define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16b4U |
| 393 | #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508U |
| 394 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664U |
| 395 | #define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174cU |
| 396 | #define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238U |
| 397 | #define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8U |
| 398 | #define MC_TXN_OVERRIDE_CONFIG_AXIAPR 0x1410U |
| 399 | #define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16e4U |
| 400 | #define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724U |
| 401 | #define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310U |
| 402 | #define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578U |
| 403 | #define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694U |
| 404 | #define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170cU |
| 405 | #define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0U |
| 406 | #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490U |
| 407 | #define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220U |
| 408 | #define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8U |
| 409 | #define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360U |
| 410 | #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17d4U |
| 411 | #define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614U |
| 412 | #define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0U |
| 413 | #define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330U |
| 414 | #define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161cU |
| 415 | #define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8U |
| 416 | #define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169cU |
| 417 | #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318U |
| 418 | #define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604U |
| 419 | #define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15e4U |
| 420 | #define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16f4U |
| 421 | #define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540U |
| 422 | #define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171cU |
| 423 | #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260U |
| 424 | #define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538U |
| 425 | #define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160cU |
| 426 | #define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15ecU |
| 427 | #define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15fcU |
| 428 | #define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16fcU |
| 429 | #define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530U |
| 430 | #define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165cU |
| 431 | #define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8U |
| 432 | #define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500U |
| 433 | #define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0U |
| 434 | #define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408U |
| 435 | #define MC_TXN_OVERRIDE_CONFIG_AXIAPW 0x1418U |
| 436 | #define MC_TXN_OVERRIDE_CONFIG_MIU4R 0x1594U |
| 437 | #define MC_TXN_OVERRIDE_CONFIG_MIU4W 0x159cU |
| 438 | #define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0U |
| 439 | #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0U |
| 440 | #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0U |
| 441 | #define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0U |
| 442 | #define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754U |
| 443 | #define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684U |
| 444 | #define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230U |
| 445 | #define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168cU |
| 446 | #define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16a4U |
| 447 | #define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794U |
| 448 | #define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8U |
| 449 | #define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16acU |
| 450 | #define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488U |
| 451 | #define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428U |
| 452 | #define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8U |
| 453 | #define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368U |
| 454 | #define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158U |
| 455 | #define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177cU |
| 456 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163cU |
| 457 | #define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300U |
| 458 | #define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167cU |
| 459 | #define MC_TXN_OVERRIDE_CONFIG_MIU5W 0x17ecU |
| 460 | #define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498U |
| 461 | #define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570U |
| 462 | #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268U |
| 463 | #define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0U |
| 464 | #define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704U |
| 465 | #define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0U |
| 466 | |
| 467 | #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1U << 0) |
| 468 | #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2U << 4) |
| 469 | #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1U << 12) |
| 470 | |
| 471 | /******************************************************************************* |
| 472 | * Non-SO_DEV transactions override values for CGID_TAG bitfield for the |
| 473 | * MC_TXN_OVERRIDE_CONFIG_{module} registers |
| 474 | ******************************************************************************/ |
| 475 | #define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0U |
| 476 | #define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1U |
| 477 | #define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2U |
| 478 | #define MC_TXN_OVERRIDE_CGID_TAG_ADR 3U |
| 479 | #define MC_TXN_OVERRIDE_CGID_TAG_MASK 3ULL |
| 480 | |
| 481 | /******************************************************************************* |
| 482 | * Memory Controller Reset Control registers |
| 483 | ******************************************************************************/ |
| 484 | #define MC_CLIENT_HOTRESET_CTRL0 0x200U |
| 485 | #define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0U |
| 486 | #define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1U << 0) |
| 487 | #define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1U << 6) |
| 488 | #define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1U << 7) |
| 489 | #define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1U << 8) |
| 490 | #define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1U << 9) |
| 491 | #define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1U << 11) |
| 492 | #define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1U << 15) |
| 493 | #define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1U << 17) |
| 494 | #define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1U << 18) |
| 495 | #define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1U << 19) |
| 496 | #define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1U << 20) |
| 497 | #define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1U << 22) |
| 498 | #define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1U << 29) |
| 499 | #define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1U << 30) |
| 500 | #define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1U << 31) |
| 501 | #define MC_CLIENT_HOTRESET_STATUS0 0x204U |
| 502 | #define MC_CLIENT_HOTRESET_CTRL1 0x970U |
| 503 | #define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0U |
| 504 | #define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1U << 0) |
| 505 | #define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1U << 2) |
| 506 | #define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1U << 5) |
| 507 | #define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1U << 6) |
| 508 | #define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1U << 7) |
| 509 | #define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1U << 8) |
| 510 | #define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1U << 12) |
| 511 | #define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1U << 13) |
| 512 | #define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1U << 17) |
| 513 | #define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1U << 18) |
| 514 | #define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1U << 19) |
| 515 | #define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1U << 20) |
| 516 | #define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1U << 21) |
| 517 | #define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1U << 22) |
| 518 | #define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 23) |
| 519 | #define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1U << 26) |
| 520 | #define MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB (1U << 31) |
| 521 | #define MC_CLIENT_HOTRESET_STATUS1 0x974U |
| 522 | #define MC_CLIENT_HOTRESET_CTRL2 0x97cU |
| 523 | #define MC_CLIENT_HOTRESET_CTRL2_RESET_VAL 0U |
| 524 | #define MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB (1U << 0) |
| 525 | #define MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB (1U << 2) |
| 526 | #define MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB (1U << 4) |
| 527 | #define MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB (1U << 9) |
| 528 | #define MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB (1U << 10) |
| 529 | #define MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB (1U << 11) |
| 530 | #define MC_CLIENT_HOTRESET_CTRL2_APEDMA_FLUSH_ENB (1U << 14) |
| 531 | #define MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB (1U << 16) |
| 532 | #define MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB (1U << 17) |
| 533 | #define MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB (1U << 22) |
| 534 | #define MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB (1U << 23) |
| 535 | #define MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB (1U << 25) |
| 536 | #define MC_CLIENT_HOTRESET_STATUS2 0x1898U |
| 537 | |
Pritesh Raithatha | 45ea689 | 2017-12-18 23:00:05 -0800 | [diff] [blame] | 538 | #define MC_COALESCE_CTRL 0x2930U |
Arto Merilainen | 919e0e2 | 2018-01-18 19:47:36 +0200 | [diff] [blame] | 539 | #define MC_COALESCE_CTRL_COALESCER_ENABLE (1U << 31) |
| 540 | #define MC_COALESCE_CONFIG_6_0 0x294cU |
| 541 | #define MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED (1U << 8) |
| 542 | #define MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED (1U << 14) |
Pritesh Raithatha | 45ea689 | 2017-12-18 23:00:05 -0800 | [diff] [blame] | 543 | |
Pritesh Raithatha | 8a45c72 | 2017-12-15 15:00:09 -0800 | [diff] [blame] | 544 | /******************************************************************************* |
| 545 | * Tegra TSA Controller constants |
| 546 | ******************************************************************************/ |
| 547 | #define TEGRA_TSA_BASE U(0x02000000) |
| 548 | |
| 549 | #define TSA_CONFIG_STATIC0_CSR_RESET_R 0x20000000U |
| 550 | #define TSA_CONFIG_STATIC0_CSW_RESET_W 0x20001000U |
| 551 | #define TSA_CONFIG_STATIC0_CSW_RESET_SO_DEV 0x20001000U |
| 552 | |
| 553 | #define TSA_CONFIG_STATIC0_CSW_PCIE1W 0x1004U |
| 554 | #define TSA_CONFIG_STATIC0_CSW_PCIE2AW 0x1008U |
| 555 | #define TSA_CONFIG_STATIC0_CSW_PCIE3W 0x100cU |
| 556 | #define TSA_CONFIG_STATIC0_CSW_PCIE4W 0x1028U |
| 557 | #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x2004U |
| 558 | #define TSA_CONFIG_STATIC0_CSR_SATAR 0x2010U |
| 559 | #define TSA_CONFIG_STATIC0_CSW_SATAW 0x2014U |
| 560 | #define TSA_CONFIG_STATIC0_CSW_PCIE0W 0x2020U |
| 561 | #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x202cU |
| 562 | #define TSA_CONFIG_STATIC0_CSW_NVENC1SWR 0x3004U |
| 563 | #define TSA_CONFIG_STATIC0_CSW_NVENCSWR 0x3010U |
| 564 | #define TSA_CONFIG_STATIC0_CSW_NVDEC1SWR 0x4004U |
| 565 | #define TSA_CONFIG_STATIC0_CSR_ISPFALR 0x4010U |
| 566 | #define TSA_CONFIG_STATIC0_CSW_ISPWA 0x4014U |
| 567 | #define TSA_CONFIG_STATIC0_CSW_ISPWB 0x4018U |
| 568 | #define TSA_CONFIG_STATIC0_CSW_ISPFALW 0x401cU |
| 569 | #define TSA_CONFIG_STATIC0_CSW_NVDECSWR 0x5004U |
| 570 | #define TSA_CONFIG_STATIC0_CSR_EQOSR 0x5010U |
| 571 | #define TSA_CONFIG_STATIC0_CSW_EQOSW 0x5014U |
| 572 | #define TSA_CONFIG_STATIC0_CSR_SDMMCRAB 0x5020U |
| 573 | #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5024U |
| 574 | #define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6004U |
| 575 | #define TSA_CONFIG_STATIC0_CSR_SDMMCR 0x6010U |
| 576 | #define TSA_CONFIG_STATIC0_CSR_SDMMCRA 0x6014U |
| 577 | #define TSA_CONFIG_STATIC0_CSW_SDMMCW 0x6018U |
| 578 | #define TSA_CONFIG_STATIC0_CSW_SDMMCWA 0x601cU |
| 579 | #define TSA_CONFIG_STATIC0_CSR_RCER 0x6030U |
| 580 | #define TSA_CONFIG_STATIC0_CSR_RCEDMAR 0x6034U |
| 581 | #define TSA_CONFIG_STATIC0_CSW_RCEW 0x6038U |
| 582 | #define TSA_CONFIG_STATIC0_CSW_RCEDMAW 0x603cU |
| 583 | #define TSA_CONFIG_STATIC0_CSR_SCER 0x6050U |
| 584 | #define TSA_CONFIG_STATIC0_CSR_SCEDMAR 0x6054U |
| 585 | #define TSA_CONFIG_STATIC0_CSW_SCEW 0x6058U |
| 586 | #define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x605cU |
| 587 | #define TSA_CONFIG_STATIC0_CSR_AXIAPR 0x7004U |
| 588 | #define TSA_CONFIG_STATIC0_CSR_ETRR 0x7008U |
| 589 | #define TSA_CONFIG_STATIC0_CSR_HOST1XDMAR 0x700cU |
| 590 | #define TSA_CONFIG_STATIC0_CSW_AXIAPW 0x7010U |
| 591 | #define TSA_CONFIG_STATIC0_CSW_ETRW 0x7014U |
| 592 | #define TSA_CONFIG_STATIC0_CSR_NVJPGSRD 0x8004U |
| 593 | #define TSA_CONFIG_STATIC0_CSW_NVJPGSWR 0x8008U |
| 594 | #define TSA_CONFIG_STATIC0_CSR_AXISR 0x8014U |
| 595 | #define TSA_CONFIG_STATIC0_CSW_AXISW 0x8018U |
| 596 | #define TSA_CONFIG_STATIC0_CSR_BPMPR 0x9004U |
| 597 | #define TSA_CONFIG_STATIC0_CSR_BPMPDMAR 0x9008U |
| 598 | #define TSA_CONFIG_STATIC0_CSW_BPMPW 0x900cU |
| 599 | #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9010U |
| 600 | #define TSA_CONFIG_STATIC0_CSR_SESRD 0x9024U |
| 601 | #define TSA_CONFIG_STATIC0_CSR_TSECSRD 0x9028U |
| 602 | #define TSA_CONFIG_STATIC0_CSR_TSECSRDB 0x902cU |
| 603 | #define TSA_CONFIG_STATIC0_CSW_SESWR 0x9030U |
| 604 | #define TSA_CONFIG_STATIC0_CSW_TSECSWR 0x9034U |
| 605 | #define TSA_CONFIG_STATIC0_CSW_TSECSWRB 0x9038U |
| 606 | #define TSA_CONFIG_STATIC0_CSW_PCIE5W 0xb004U |
| 607 | #define TSA_CONFIG_STATIC0_CSW_VICSWR 0xc004U |
| 608 | #define TSA_CONFIG_STATIC0_CSR_APER 0xd004U |
| 609 | #define TSA_CONFIG_STATIC0_CSR_APEDMAR 0xd008U |
| 610 | #define TSA_CONFIG_STATIC0_CSW_APEW 0xd00cU |
| 611 | #define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xd010U |
| 612 | #define TSA_CONFIG_STATIC0_CSR_HDAR 0xf004U |
| 613 | #define TSA_CONFIG_STATIC0_CSW_HDAW 0xf008U |
| 614 | #define TSA_CONFIG_STATIC0_CSR_NVDISPLAYR 0xf014U |
| 615 | #define TSA_CONFIG_STATIC0_CSR_VIFALR 0x10004U |
| 616 | #define TSA_CONFIG_STATIC0_CSW_VIW 0x10008U |
| 617 | #define TSA_CONFIG_STATIC0_CSW_VIFALW 0x1000cU |
| 618 | #define TSA_CONFIG_STATIC0_CSR_AONR 0x12004U |
| 619 | #define TSA_CONFIG_STATIC0_CSR_AONDMAR 0x12008U |
| 620 | #define TSA_CONFIG_STATIC0_CSW_AONW 0x1200cU |
| 621 | #define TSA_CONFIG_STATIC0_CSW_AONDMAW 0x12010U |
| 622 | #define TSA_CONFIG_STATIC0_CSR_PCIE1R 0x14004U |
| 623 | #define TSA_CONFIG_STATIC0_CSR_PCIE2AR 0x14008U |
| 624 | #define TSA_CONFIG_STATIC0_CSR_PCIE3R 0x1400cU |
| 625 | #define TSA_CONFIG_STATIC0_CSR_PCIE4R 0x14028U |
| 626 | #define TSA_CONFIG_STATIC0_CSR_XUSB_DEVR 0x15004U |
| 627 | #define TSA_CONFIG_STATIC0_CSR_XUSB_HOSTR 0x15010U |
| 628 | #define TSA_CONFIG_STATIC0_CSR_UFSHCR 0x16004U |
| 629 | #define TSA_CONFIG_STATIC0_CSW_DLA1WRA 0x18004U |
| 630 | #define TSA_CONFIG_STATIC0_CSR_DLA1FALRDB 0x18010U |
| 631 | #define TSA_CONFIG_STATIC0_CSW_DLA1FALWRB 0x18014U |
| 632 | #define TSA_CONFIG_STATIC0_CSW_DLA0WRA 0x19004U |
| 633 | #define TSA_CONFIG_STATIC0_CSR_DLA0FALRDB 0x19010U |
| 634 | #define TSA_CONFIG_STATIC0_CSW_DLA0FALWRB 0x19014U |
| 635 | #define TSA_CONFIG_STATIC0_CSR_PVA1RDC 0x1a004U |
| 636 | #define TSA_CONFIG_STATIC0_CSW_PVA1WRC 0x1a008U |
| 637 | #define TSA_CONFIG_STATIC0_CSW_PVA1WRA 0x1a014U |
| 638 | #define TSA_CONFIG_STATIC0_CSW_PVA1WRB 0x1a020U |
| 639 | #define TSA_CONFIG_STATIC0_CSW_PVA0WRB 0x1b004U |
| 640 | #define TSA_CONFIG_STATIC0_CSR_PVA0RDC 0x1b010U |
| 641 | #define TSA_CONFIG_STATIC0_CSW_PVA0WRC 0x1b014U |
| 642 | #define TSA_CONFIG_STATIC0_CSW_PVA0WRA 0x1b020U |
| 643 | #define TSA_CONFIG_STATIC0_CSR_NVENC1SRD 0x1d004U |
| 644 | #define TSA_CONFIG_STATIC0_CSR_NVENCSRD 0x1d010U |
| 645 | #define TSA_CONFIG_STATIC0_CSR_NVDEC1SRD 0x1e004U |
| 646 | #define TSA_CONFIG_STATIC0_CSR_ISPRA 0x1e010U |
| 647 | #define TSA_CONFIG_STATIC0_CSR_NVDECSRD 0x1f004U |
| 648 | #define TSA_CONFIG_STATIC0_CSR_PCIE0R 0x21004U |
| 649 | #define TSA_CONFIG_STATIC0_CSR_PCIE5R 0x23004U |
| 650 | #define TSA_CONFIG_STATIC0_CSR_VICSRD 0x24004U |
| 651 | #define TSA_CONFIG_STATIC0_CSR_DLA1RDA 0x26004U |
| 652 | #define TSA_CONFIG_STATIC0_CSR_DLA0RDA 0x27004U |
| 653 | #define TSA_CONFIG_STATIC0_CSR_PVA1RDA 0x28004U |
| 654 | #define TSA_CONFIG_STATIC0_CSR_PVA1RDB 0x28010U |
| 655 | #define TSA_CONFIG_STATIC0_CSR_PVA0RDB 0x29004U |
| 656 | #define TSA_CONFIG_STATIC0_CSR_PVA0RDA 0x29010U |
| 657 | |
| 658 | #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11) |
| 659 | #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11) |
Puneet Saxena | 5b526df | 2018-01-05 07:04:35 -0800 | [diff] [blame] | 660 | #define TSA_CONFIG_CSW_SO_DEV_HUBID_MASK (ULL(0x3) << 15) |
| 661 | #define TSA_CONFIG_CSW_SO_DEV_HUB2 (ULL(2) << 15) |
| 662 | |
Puneet Saxena | 1654e1c | 2018-03-07 14:06:30 +0530 | [diff] [blame] | 663 | #define REORDER_DEPTH_LIMIT 16 |
| 664 | #define TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK (ULL(0x7FF) << 21) |
| 665 | #define reorder_depth_limit(limit) (ULL(limit) << 21) |
| 666 | |
Puneet Saxena | 5b526df | 2018-01-05 07:04:35 -0800 | [diff] [blame] | 667 | #define tsa_read_32(client) \ |
| 668 | mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client) |
| 669 | |
| 670 | #define mc_set_tsa_hub2(val, client) \ |
| 671 | { \ |
| 672 | mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ |
| 673 | ((val & ~TSA_CONFIG_CSW_SO_DEV_HUBID_MASK) | \ |
| 674 | TSA_CONFIG_CSW_SO_DEV_HUB2)); \ |
| 675 | } |
Pritesh Raithatha | 8a45c72 | 2017-12-15 15:00:09 -0800 | [diff] [blame] | 676 | |
Puneet Saxena | 1654e1c | 2018-03-07 14:06:30 +0530 | [diff] [blame] | 677 | #define mc_set_tsa_depth_limit(limit, client) \ |
| 678 | { \ |
| 679 | uint32_t val = mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client); \ |
| 680 | mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ |
| 681 | ((val & ~TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK) | \ |
| 682 | reorder_depth_limit(limit))); \ |
| 683 | } |
| 684 | |
Varun Wadekar | 2909fa3 | 2020-01-09 08:52:10 -0800 | [diff] [blame] | 685 | #endif /* TEGRA_MC_DEF_H */ |