| commit | 1654e1ca12af14b98fab777b5f93671dc3b60463 | [log] [tgz] |
|---|---|---|
| author | Puneet Saxena <puneets@nvidia.com> | Wed Mar 07 14:06:30 2018 +0530 |
| committer | Varun Wadekar <vwadekar@nvidia.com> | Thu Jan 23 09:01:25 2020 -0800 |
| tree | 11d43649903e1cd50460152ce3ced093496a0d32 | |
| parent | e0dd683339eda9d235b2ef7246741f5ceca174c1 [diff] |
Tegra194: memctrl: set reorder depth limit for PCIE blocks HW bug in third party PCIE IP - PCIE datapath hangs when there are more than 28 outstanding requests on data backbone for x1 controller. Suggested SW WAR is to limit reorder_depth_limit to 16 for PCIE 1W/2AW/3W clients. Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067 Signed-off-by: Puneet Saxena <puneets@nvidia.com>