Tegra194: memctrl: update mss reprogramming as HW PROD settings
Memory clients are divided in to ISO/NonISO/Order/Unordered/Low
BW/High BW. Based on the client types, HW team recommends, different
memory ordering settings, IO coherency settings and SMMU register settings
for optimized performance of the MC clients.
For example ordered ISO clients should be set as strongly ordered and
should bypass SCF and directly access MC hence set as
FORCE_NON_COHERENT. Like this there are multiple recommendations
for all of the MC clients.
This change sets all these MC registers as per HW spec file.
Change-Id: I8a8a0887cd86bf6fe8ac7835df6c888855738cd9
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
index 5da770f..6911ba1 100644
--- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
@@ -18,14 +18,14 @@
#define MC_CLIENT_ORDER_ID_27 U(0x2a6c)
#define MC_CLIENT_ORDER_ID_27_RESET_VAL 0x00000000U
#define MC_CLIENT_ORDER_ID_27_PCIE0W_MASK (0x3U << 4)
-#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (1U << 4)
+#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (2U << 4)
#define MC_CLIENT_ORDER_ID_28 U(0x2a70)
#define MC_CLIENT_ORDER_ID_28_RESET_VAL 0x00000000U
#define MC_CLIENT_ORDER_ID_28_PCIE4W_MASK (0x3U << 4)
#define MC_CLIENT_ORDER_ID_28_PCIE4W_ORDER_ID (3U << 4)
#define MC_CLIENT_ORDER_ID_28_PCIE5W_MASK (0x3U << 12)
-#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (2U << 12)
+#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (1U << 12)
#define mc_client_order_id(val, id, client) \
((val & ~MC_CLIENT_ORDER_ID_##id##_##client##_MASK) | \
@@ -53,6 +53,11 @@
#define MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK (0x3U << 28)
#define MC_HUB_PC_VC_ID_4_NIC_VC_ID (VC_NISO << 28)
+#define MC_HUB_PC_VC_ID_12 U(0x2aa8)
+#define MC_HUB_PC_VC_ID_12_RESET_VAL 0x11001011U
+#define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID_MASK (0x3U << 12)
+#define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID (VC_NISO << 12)
+
#define mc_hub_vc_id(val, id, client) \
((val & ~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK) | \
MC_HUB_PC_VC_ID_##id##_##client##_VC_ID)
@@ -105,7 +110,7 @@
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_MASK (1U << 7)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0U << 13)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1U << 13)
-#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1U << 15)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0U << 15)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1U << 15)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0U << 17)
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1U << 17)
@@ -652,5 +657,17 @@
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11)
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11)
+#define TSA_CONFIG_CSW_SO_DEV_HUBID_MASK (ULL(0x3) << 15)
+#define TSA_CONFIG_CSW_SO_DEV_HUB2 (ULL(2) << 15)
+
+#define tsa_read_32(client) \
+ mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client)
+
+#define mc_set_tsa_hub2(val, client) \
+ { \
+ mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
+ ((val & ~TSA_CONFIG_CSW_SO_DEV_HUBID_MASK) | \
+ TSA_CONFIG_CSW_SO_DEV_HUB2)); \
+ }
#endif /* TEGRA_MC_DEF_H */