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Hadi Asyrafi616da772019-06-27 11:34:03 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <common/debug.h>
9#include <common/runtime_svc.h>
Hadi Asyrafi67942302019-10-22 13:28:51 +080010#include <lib/mmio.h>
Hadi Asyrafi616da772019-06-27 11:34:03 +080011#include <tools_share/uuid.h>
12
Hadi Asyrafi6f8a2b22019-10-23 18:34:14 +080013#include "socfpga_mailbox.h"
Hadi Asyrafi36a9f302019-12-24 10:42:52 +080014#include "socfpga_reset_manager.h"
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080015#include "socfpga_sip_svc.h"
Hadi Asyrafi616da772019-06-27 11:34:03 +080016
17/* Number of SiP Calls implemented */
18#define SIP_NUM_CALLS 0x3
19
20/* Total buffer the driver can hold */
21#define FPGA_CONFIG_BUFFER_SIZE 4
22
Tien Hock, Loh500b2322019-10-30 14:49:40 +080023static int current_block;
24static int read_block;
25static int current_buffer;
26static int send_id;
27static int rcv_id;
28static int max_blocks;
29static uint32_t bytes_per_block;
30static uint32_t blocks_submitted;
Hadi Asyrafi36a9f302019-12-24 10:42:52 +080031static int is_partial_reconfig;
Hadi Asyrafi616da772019-06-27 11:34:03 +080032
33struct fpga_config_info {
34 uint32_t addr;
35 int size;
36 int size_written;
37 uint32_t write_requested;
38 int subblocks_sent;
39 int block_number;
40};
41
42/* SiP Service UUID */
43DEFINE_SVC_UUID2(intl_svc_uid,
44 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
45 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
46
Hadi Asyraficee6aa92019-12-17 15:25:04 +080047static uint64_t socfpga_sip_handler(uint32_t smc_fid,
Hadi Asyrafi616da772019-06-27 11:34:03 +080048 uint64_t x1,
49 uint64_t x2,
50 uint64_t x3,
51 uint64_t x4,
52 void *cookie,
53 void *handle,
54 uint64_t flags)
55{
56 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
57 SMC_RET1(handle, SMC_UNK);
58}
59
60struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
61
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080062static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
Hadi Asyrafi616da772019-06-27 11:34:03 +080063{
64 uint32_t args[3];
65
66 while (max_blocks > 0 && buffer->size > buffer->size_written) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080067 args[0] = (1<<8);
68 args[1] = buffer->addr + buffer->size_written;
69 if (buffer->size - buffer->size_written <= bytes_per_block) {
Hadi Asyrafi616da772019-06-27 11:34:03 +080070 args[2] = buffer->size - buffer->size_written;
Hadi Asyrafi616da772019-06-27 11:34:03 +080071 current_buffer++;
72 current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080073 } else
Hadi Asyrafi616da772019-06-27 11:34:03 +080074 args[2] = bytes_per_block;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080075
76 buffer->size_written += args[2];
77 mailbox_send_cmd_async(
78 send_id++ % MBOX_MAX_JOB_ID,
79 MBOX_RECONFIG_DATA,
80 args, 3, 0);
81
82 buffer->subblocks_sent++;
Hadi Asyrafi616da772019-06-27 11:34:03 +080083 max_blocks--;
84 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080085
86 return !max_blocks;
Hadi Asyrafi616da772019-06-27 11:34:03 +080087}
88
89static int intel_fpga_sdm_write_all(void)
90{
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080091 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
92 if (intel_fpga_sdm_write_buffer(
93 &fpga_config_buffers[current_buffer]))
94 break;
Hadi Asyrafi616da772019-06-27 11:34:03 +080095 return 0;
96}
97
Hadi Asyrafi0c6dae22019-12-17 23:33:39 +080098static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type)
Hadi Asyrafi616da772019-06-27 11:34:03 +080099{
Hadi Asyrafi0c6dae22019-12-17 23:33:39 +0800100 uint32_t ret;
101
102 if (query_type == 1)
103 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
104 else
105 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS);
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800106
107 if (ret) {
108 if (ret == MBOX_CFGSTAT_STATE_CONFIG)
109 return INTEL_SIP_SMC_STATUS_BUSY;
110 else
111 return INTEL_SIP_SMC_STATUS_ERROR;
112 }
113
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800114 if (query_type != 1) {
115 /* full reconfiguration */
116 if (!is_partial_reconfig)
117 socfpga_bridges_enable(); /* Enable bridge */
118 }
119
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800120 return INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800121}
122
123static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
124{
125 int i;
126
127 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
128 if (fpga_config_buffers[i].block_number == current_block) {
129 fpga_config_buffers[i].subblocks_sent--;
130 if (fpga_config_buffers[i].subblocks_sent == 0
131 && fpga_config_buffers[i].size <=
132 fpga_config_buffers[i].size_written) {
133 fpga_config_buffers[i].write_requested = 0;
134 current_block++;
135 *buffer_addr_completed =
136 fpga_config_buffers[i].addr;
137 return 0;
138 }
139 }
140 }
141
142 return -1;
143}
144
Hadi Asyraficee6aa92019-12-17 15:25:04 +0800145static int intel_fpga_config_completed_write(uint32_t *completed_addr,
Hadi Asyrafi616da772019-06-27 11:34:03 +0800146 uint32_t *count)
147{
148 uint32_t status = INTEL_SIP_SMC_STATUS_OK;
149 *count = 0;
150 int resp_len = 0;
151 uint32_t resp[5];
152 int all_completed = 1;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800153
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800154 while (*count < 3) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800155
Hadi Asyrafi9dfc0472019-11-12 16:39:46 +0800156 resp_len = mailbox_read_response(rcv_id % MBOX_MAX_JOB_ID,
157 resp, sizeof(resp) / sizeof(resp[0]));
Hadi Asyrafi616da772019-06-27 11:34:03 +0800158
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800159 if (resp_len < 0)
160 break;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800161
Hadi Asyrafi616da772019-06-27 11:34:03 +0800162 max_blocks++;
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800163 rcv_id++;
164
Hadi Asyrafi616da772019-06-27 11:34:03 +0800165 if (mark_last_buffer_xfer_completed(
166 &completed_addr[*count]) == 0)
167 *count = *count + 1;
168 else
169 break;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800170 }
171
172 if (*count <= 0) {
173 if (resp_len != MBOX_NO_RESPONSE &&
174 resp_len != MBOX_TIMEOUT && resp_len != 0) {
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800175 mailbox_clear_response();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800176 return INTEL_SIP_SMC_STATUS_ERROR;
177 }
178
179 *count = 0;
180 }
181
182 intel_fpga_sdm_write_all();
183
184 if (*count > 0)
185 status = INTEL_SIP_SMC_STATUS_OK;
186 else if (*count == 0)
187 status = INTEL_SIP_SMC_STATUS_BUSY;
188
189 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
190 if (fpga_config_buffers[i].write_requested != 0) {
191 all_completed = 0;
192 break;
193 }
194 }
195
196 if (all_completed == 1)
197 return INTEL_SIP_SMC_STATUS_OK;
198
199 return status;
200}
201
Hadi Asyraficee6aa92019-12-17 15:25:04 +0800202static int intel_fpga_config_start(uint32_t config_type)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800203{
204 uint32_t response[3];
205 int status = 0;
206
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800207 is_partial_reconfig = config_type;
208
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800209 mailbox_clear_response();
210
Hadi Asyrafi9dfc0472019-11-12 16:39:46 +0800211 mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0);
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800212
213 status = mailbox_send_cmd(1, MBOX_RECONFIG, 0, 0, 0,
Hadi Asyrafi9dfc0472019-11-12 16:39:46 +0800214 response, sizeof(response) / sizeof(response[0]));
Hadi Asyrafi616da772019-06-27 11:34:03 +0800215
216 if (status < 0)
217 return status;
218
219 max_blocks = response[0];
220 bytes_per_block = response[1];
221
222 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
223 fpga_config_buffers[i].size = 0;
224 fpga_config_buffers[i].size_written = 0;
225 fpga_config_buffers[i].addr = 0;
226 fpga_config_buffers[i].write_requested = 0;
227 fpga_config_buffers[i].block_number = 0;
228 fpga_config_buffers[i].subblocks_sent = 0;
229 }
230
231 blocks_submitted = 0;
232 current_block = 0;
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800233 read_block = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800234 current_buffer = 0;
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800235 send_id = 0;
236 rcv_id = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800237
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800238 /* full reconfiguration */
239 if (!is_partial_reconfig) {
240 /* Disable bridge */
241 socfpga_bridges_disable();
242 }
243
Hadi Asyrafi616da772019-06-27 11:34:03 +0800244 return 0;
245}
246
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800247static bool is_fpga_config_buffer_full(void)
248{
249 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
250 if (!fpga_config_buffers[i].write_requested)
251 return false;
252 return true;
253}
254
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800255static bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800256{
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800257 if (size > (UINT64_MAX - addr))
258 return false;
259 if (addr < DRAM_BASE)
260 return false;
261 if (addr + size > DRAM_BASE + DRAM_SIZE)
262 return false;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800263
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800264 return true;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800265}
Hadi Asyrafi616da772019-06-27 11:34:03 +0800266
Hadi Asyraficee6aa92019-12-17 15:25:04 +0800267static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800268{
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800269 int i;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800270
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800271 intel_fpga_sdm_write_all();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800272
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800273 if (!is_address_in_ddr_range(mem, size) ||
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800274 is_fpga_config_buffer_full())
275 return INTEL_SIP_SMC_STATUS_REJECTED;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800276
277 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800278 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
279
280 if (!fpga_config_buffers[j].write_requested) {
281 fpga_config_buffers[j].addr = mem;
282 fpga_config_buffers[j].size = size;
283 fpga_config_buffers[j].size_written = 0;
284 fpga_config_buffers[j].write_requested = 1;
285 fpga_config_buffers[j].block_number =
Hadi Asyrafi616da772019-06-27 11:34:03 +0800286 blocks_submitted++;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800287 fpga_config_buffers[j].subblocks_sent = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800288 break;
289 }
290 }
291
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800292 if (is_fpga_config_buffer_full())
293 return INTEL_SIP_SMC_STATUS_BUSY;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800294
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800295 return INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800296}
297
Hadi Asyrafi67942302019-10-22 13:28:51 +0800298static int is_out_of_sec_range(uint64_t reg_addr)
299{
300 switch (reg_addr) {
301 case(0xF8011100): /* ECCCTRL1 */
302 case(0xF8011104): /* ECCCTRL2 */
303 case(0xF8011110): /* ERRINTEN */
304 case(0xF8011114): /* ERRINTENS */
305 case(0xF8011118): /* ERRINTENR */
306 case(0xF801111C): /* INTMODE */
307 case(0xF8011120): /* INTSTAT */
308 case(0xF8011124): /* DIAGINTTEST */
309 case(0xF801112C): /* DERRADDRA */
310 case(0xFFD12028): /* SDMMCGRP_CTRL */
311 case(0xFFD12044): /* EMAC0 */
312 case(0xFFD12048): /* EMAC1 */
313 case(0xFFD1204C): /* EMAC2 */
314 case(0xFFD12090): /* ECC_INT_MASK_VALUE */
315 case(0xFFD12094): /* ECC_INT_MASK_SET */
316 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */
317 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */
318 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */
319 case(0xFFD120C0): /* NOC_TIMEOUT */
320 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
321 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
322 case(0xFFD120D0): /* NOC_IDLEACK */
323 case(0xFFD120D4): /* NOC_IDLESTATUS */
324 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */
325 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */
326 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */
327 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */
328 return 0;
329
330 default:
331 break;
332 }
333
334 return -1;
335}
336
337/* Secure register access */
338uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval)
339{
340 if (is_out_of_sec_range(reg_addr))
341 return INTEL_SIP_SMC_STATUS_ERROR;
342
343 *retval = mmio_read_32(reg_addr);
344
345 return INTEL_SIP_SMC_STATUS_OK;
346}
347
348uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
349 uint32_t *retval)
350{
351 if (is_out_of_sec_range(reg_addr))
352 return INTEL_SIP_SMC_STATUS_ERROR;
353
354 mmio_write_32(reg_addr, val);
355
356 return intel_secure_reg_read(reg_addr, retval);
357}
358
359uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
360 uint32_t val, uint32_t *retval)
361{
362 if (!intel_secure_reg_read(reg_addr, retval)) {
363 *retval &= ~mask;
364 *retval |= val;
365 return intel_secure_reg_write(reg_addr, *retval, retval);
366 }
367
368 return INTEL_SIP_SMC_STATUS_ERROR;
369}
370
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800371/* Intel Remote System Update (RSU) services */
372uint64_t intel_rsu_update_address;
373
374static uint32_t intel_rsu_status(uint64_t *respbuf, uint32_t respbuf_sz)
375{
376 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0)
377 return INTEL_SIP_SMC_STATUS_ERROR;
378
379 return INTEL_SIP_SMC_STATUS_OK;
380}
381
382static uint32_t intel_rsu_update(uint64_t update_address)
383{
384 intel_rsu_update_address = update_address;
385 return INTEL_SIP_SMC_STATUS_OK;
386}
387
388static uint32_t intel_rsu_notify(uint64_t execution_stage)
389{
390 if (mailbox_hps_stage_notify((uint32_t)execution_stage) < 0)
391 return INTEL_SIP_SMC_STATUS_ERROR;
392
393 return INTEL_SIP_SMC_STATUS_OK;
394}
395
396static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
397 uint32_t *ret_stat)
398{
399 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0)
400 return INTEL_SIP_SMC_STATUS_ERROR;
401
402 *ret_stat = respbuf[8];
403 return INTEL_SIP_SMC_STATUS_OK;
404}
405
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800406/* Mailbox services */
407static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, int len,
408 int urgent, uint32_t *response,
409 int resp_len, int *mbox_status,
410 int *len_in_resp)
411{
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800412 *len_in_resp = 0;
413 *mbox_status = 0;
414
415 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len))
416 return INTEL_SIP_SMC_STATUS_REJECTED;
417
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800418 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent,
419 response, resp_len);
420
421 if (status < 0) {
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800422 *mbox_status = -status;
423 return INTEL_SIP_SMC_STATUS_ERROR;
424 }
425
426 *mbox_status = 0;
427 *len_in_resp = status;
428 return INTEL_SIP_SMC_STATUS_OK;
429}
430
Hadi Asyrafi616da772019-06-27 11:34:03 +0800431/*
432 * This function is responsible for handling all SiP calls from the NS world
433 */
434
435uintptr_t sip_smc_handler(uint32_t smc_fid,
436 u_register_t x1,
437 u_register_t x2,
438 u_register_t x3,
439 u_register_t x4,
440 void *cookie,
441 void *handle,
442 u_register_t flags)
443{
Hadi Asyrafi67942302019-10-22 13:28:51 +0800444 uint32_t val = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800445 uint32_t status = INTEL_SIP_SMC_STATUS_OK;
446 uint32_t completed_addr[3];
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800447 uint64_t rsu_respbuf[9];
Hadi Asyrafi616da772019-06-27 11:34:03 +0800448 uint32_t count = 0;
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800449 u_register_t x5, x6;
450 int mbox_status, len_in_resp;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800451
452 switch (smc_fid) {
453 case SIP_SVC_UID:
454 /* Return UID to the caller */
455 SMC_UUID_RET(handle, intl_svc_uid);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800456
Hadi Asyrafi616da772019-06-27 11:34:03 +0800457 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
Hadi Asyrafi0c6dae22019-12-17 23:33:39 +0800458 status = intel_mailbox_fpga_config_isdone(x1);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800459 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800460
Hadi Asyrafi616da772019-06-27 11:34:03 +0800461 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
462 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
463 INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
464 INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
465 INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800466
Hadi Asyrafi616da772019-06-27 11:34:03 +0800467 case INTEL_SIP_SMC_FPGA_CONFIG_START:
468 status = intel_fpga_config_start(x1);
469 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800470
Hadi Asyrafi616da772019-06-27 11:34:03 +0800471 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
472 status = intel_fpga_config_write(x1, x2);
473 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800474
Hadi Asyrafi616da772019-06-27 11:34:03 +0800475 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
476 status = intel_fpga_config_completed_write(completed_addr,
477 &count);
478 switch (count) {
479 case 1:
480 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
481 completed_addr[0], 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800482
Hadi Asyrafi616da772019-06-27 11:34:03 +0800483 case 2:
484 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
485 completed_addr[0],
486 completed_addr[1], 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800487
Hadi Asyrafi616da772019-06-27 11:34:03 +0800488 case 3:
489 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
490 completed_addr[0],
491 completed_addr[1],
492 completed_addr[2]);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800493
Hadi Asyrafi616da772019-06-27 11:34:03 +0800494 case 0:
495 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800496
Hadi Asyrafi616da772019-06-27 11:34:03 +0800497 default:
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800498 mailbox_clear_response();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800499 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
500 }
Hadi Asyrafi67942302019-10-22 13:28:51 +0800501
502 case INTEL_SIP_SMC_REG_READ:
503 status = intel_secure_reg_read(x1, &val);
504 SMC_RET3(handle, status, val, x1);
505
506 case INTEL_SIP_SMC_REG_WRITE:
507 status = intel_secure_reg_write(x1, (uint32_t)x2, &val);
508 SMC_RET3(handle, status, val, x1);
509
510 case INTEL_SIP_SMC_REG_UPDATE:
511 status = intel_secure_reg_update(x1, (uint32_t)x2,
512 (uint32_t)x3, &val);
513 SMC_RET3(handle, status, val, x1);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800514
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800515 case INTEL_SIP_SMC_RSU_STATUS:
516 status = intel_rsu_status(rsu_respbuf,
517 ARRAY_SIZE(rsu_respbuf));
518 if (status) {
519 SMC_RET1(handle, status);
520 } else {
521 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1],
522 rsu_respbuf[2], rsu_respbuf[3]);
523 }
524
525 case INTEL_SIP_SMC_RSU_UPDATE:
526 status = intel_rsu_update(x1);
527 SMC_RET1(handle, status);
528
529 case INTEL_SIP_SMC_RSU_NOTIFY:
530 status = intel_rsu_notify(x1);
531 SMC_RET1(handle, status);
532
533 case INTEL_SIP_SMC_RSU_RETRY_COUNTER:
534 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
535 ARRAY_SIZE(rsu_respbuf), &val);
536 if (status) {
537 SMC_RET1(handle, status);
538 } else {
539 SMC_RET2(handle, status, val);
540 }
541
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800542 case INTEL_SIP_SMC_MBOX_SEND_CMD:
543 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
544 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
545 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4,
546 (uint32_t *)x5, x6, &mbox_status,
547 &len_in_resp);
548 SMC_RET4(handle, status, mbox_status, x5, len_in_resp);
549
Hadi Asyrafi616da772019-06-27 11:34:03 +0800550 default:
551 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
552 cookie, handle, flags);
553 }
554}
555
556DECLARE_RT_SVC(
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +0800557 socfpga_sip_svc,
Hadi Asyrafi616da772019-06-27 11:34:03 +0800558 OEN_SIP_START,
559 OEN_SIP_END,
560 SMC_TYPE_FAST,
561 NULL,
562 sip_smc_handler
563);
564
565DECLARE_RT_SVC(
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +0800566 socfpga_sip_svc_std,
Hadi Asyrafi616da772019-06-27 11:34:03 +0800567 OEN_SIP_START,
568 OEN_SIP_END,
569 SMC_TYPE_YIELD,
570 NULL,
571 sip_smc_handler
572);