Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 3c817f4 | 2018-03-21 10:49:27 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 7 | #include <amu.h> |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 8 | #include <arch.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 9 | #include <arch_helpers.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 10 | #include <assert.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 11 | #include <bl_common.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 12 | #include <context.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 13 | #include <context_mgmt.h> |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 14 | #include <interrupt_mgmt.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 15 | #include <platform.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 16 | #include <platform_def.h> |
Dimitris Papastamos | a7921b9 | 2017-10-13 15:27:58 +0100 | [diff] [blame] | 17 | #include <pubsub_events.h> |
Antonio Nino Diaz | 3c817f4 | 2018-03-21 10:49:27 +0000 | [diff] [blame] | 18 | #include <smccc_helpers.h> |
Dimitris Papastamos | 5bdbb47 | 2017-10-13 12:06:06 +0100 | [diff] [blame] | 19 | #include <spe.h> |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 20 | #include <string.h> |
David Cunado | ce88eee | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 21 | #include <sve.h> |
Douglas Raillard | a8954fc | 2017-01-26 15:54:44 +0000 | [diff] [blame] | 22 | #include <utils.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 23 | |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 24 | |
| 25 | /******************************************************************************* |
| 26 | * Context management library initialisation routine. This library is used by |
| 27 | * runtime services to share pointers to 'cpu_context' structures for the secure |
| 28 | * and non-secure states. Management of the structures and their associated |
| 29 | * memory is not done by the context management library e.g. the PSCI service |
| 30 | * manages the cpu context used for entry from and exit to the non-secure state. |
| 31 | * The Secure payload dispatcher service manages the context(s) corresponding to |
| 32 | * the secure state. It also uses this library to get access to the non-secure |
| 33 | * state cpu context pointers. |
| 34 | * Lastly, this library provides the api to make SP_EL3 point to the cpu context |
| 35 | * which will used for programming an entry into a lower EL. The same context |
| 36 | * will used to save state upon exception entry from that EL. |
| 37 | ******************************************************************************/ |
Juan Castillo | 2d55240 | 2014-06-13 17:05:10 +0100 | [diff] [blame] | 38 | void cm_init(void) |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 39 | { |
| 40 | /* |
| 41 | * The context management library has only global data to intialize, but |
| 42 | * that will be done when the BSS is zeroed out |
| 43 | */ |
| 44 | } |
| 45 | |
| 46 | /******************************************************************************* |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 47 | * The following function initializes the cpu_context 'ctx' for |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 48 | * first use, and sets the initial entrypoint state as specified by the |
| 49 | * entry_point_info structure. |
| 50 | * |
| 51 | * The security state to initialize is determined by the SECURE attribute |
Antonio Nino Diaz | 28dce9e | 2018-05-22 10:09:10 +0100 | [diff] [blame] | 52 | * of the entry_point_info. |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 53 | * |
| 54 | * The EE and ST attributes are used to configure the endianess and secure |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 55 | * timer availability for the new execution context. |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 56 | * |
| 57 | * To prepare the register state for entry call cm_prepare_el3_exit() and |
| 58 | * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to |
| 59 | * cm_e1_sysreg_context_restore(). |
| 60 | ******************************************************************************/ |
Antonio Nino Diaz | 28dce9e | 2018-05-22 10:09:10 +0100 | [diff] [blame] | 61 | void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 62 | { |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 63 | unsigned int security_state; |
David Cunado | 4168f2f | 2017-10-02 17:41:39 +0100 | [diff] [blame] | 64 | uint32_t scr_el3, pmcr_el0; |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 65 | el3_state_t *state; |
| 66 | gp_regs_t *gp_regs; |
Varun Wadekar | b6dd0b3 | 2018-05-08 10:52:36 -0700 | [diff] [blame] | 67 | unsigned long sctlr_elx, actlr_elx; |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 68 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 69 | assert(ctx); |
| 70 | |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 71 | security_state = GET_SECURITY_STATE(ep->h.attr); |
| 72 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 73 | /* Clear any residual register values from the context */ |
Douglas Raillard | a8954fc | 2017-01-26 15:54:44 +0000 | [diff] [blame] | 74 | zeromem(ctx, sizeof(*ctx)); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 75 | |
| 76 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 77 | * SCR_EL3 was initialised during reset sequence in macro |
| 78 | * el3_arch_init_common. This code modifies the SCR_EL3 fields that |
| 79 | * affect the next EL. |
| 80 | * |
| 81 | * The following fields are initially set to zero and then updated to |
| 82 | * the required value depending on the state of the SPSR_EL3 and the |
| 83 | * Security state and entrypoint attributes of the next EL. |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 84 | */ |
| 85 | scr_el3 = read_scr(); |
| 86 | scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | |
| 87 | SCR_ST_BIT | SCR_HCE_BIT); |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 88 | /* |
| 89 | * SCR_NS: Set the security state of the next EL. |
| 90 | */ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 91 | if (security_state != SECURE) |
| 92 | scr_el3 |= SCR_NS_BIT; |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 93 | /* |
| 94 | * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next |
| 95 | * Exception level as specified by SPSR. |
| 96 | */ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 97 | if (GET_RW(ep->spsr) == MODE_RW_64) |
| 98 | scr_el3 |= SCR_RW_BIT; |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 99 | /* |
| 100 | * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical |
| 101 | * Secure timer registers to EL3, from AArch64 state only, if specified |
| 102 | * by the entrypoint attributes. |
| 103 | */ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 104 | if (EP_GET_ST(ep->h.attr)) |
| 105 | scr_el3 |= SCR_ST_BIT; |
| 106 | |
Gerald Lejeune | 632d6df | 2016-03-22 09:29:23 +0100 | [diff] [blame] | 107 | #ifndef HANDLE_EA_EL3_FIRST |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 108 | /* |
| 109 | * SCR_EL3.EA: Do not route External Abort and SError Interrupt External |
| 110 | * to EL3 when executing at a lower EL. When executing at EL3, External |
| 111 | * Aborts are taken to EL3. |
| 112 | */ |
Gerald Lejeune | 632d6df | 2016-03-22 09:29:23 +0100 | [diff] [blame] | 113 | scr_el3 &= ~SCR_EA_BIT; |
| 114 | #endif |
| 115 | |
Jeenu Viswambharan | f00da74 | 2017-12-08 12:13:51 +0000 | [diff] [blame] | 116 | #if FAULT_INJECTION_SUPPORT |
| 117 | /* Enable fault injection from lower ELs */ |
| 118 | scr_el3 |= SCR_FIEN_BIT; |
| 119 | #endif |
| 120 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 121 | #ifdef IMAGE_BL31 |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 122 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 123 | * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ rounting as |
| 124 | * indicated by the interrupt routing model for BL31. |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 125 | */ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 126 | scr_el3 |= get_scr_el3_from_routing_model(security_state); |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 127 | #endif |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 128 | |
| 129 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 130 | * SCR_EL3.HCE: Enable HVC instructions if next execution state is |
| 131 | * AArch64 and next EL is EL2, or if next execution state is AArch32 and |
| 132 | * next mode is Hyp. |
| 133 | */ |
| 134 | if ((GET_RW(ep->spsr) == MODE_RW_64 |
| 135 | && GET_EL(ep->spsr) == MODE_EL2) |
| 136 | || (GET_RW(ep->spsr) != MODE_RW_64 |
| 137 | && GET_M32(ep->spsr) == MODE32_hyp)) { |
| 138 | scr_el3 |= SCR_HCE_BIT; |
| 139 | } |
| 140 | |
| 141 | /* |
| 142 | * Initialise SCTLR_EL1 to the reset value corresponding to the target |
| 143 | * execution state setting all fields rather than relying of the hw. |
| 144 | * Some fields have architecturally UNKNOWN reset values and these are |
| 145 | * set to zero. |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 146 | * |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 147 | * SCTLR.EE: Endianness is taken from the entrypoint attributes. |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 148 | * |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 149 | * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as |
| 150 | * required by PSCI specification) |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 151 | */ |
| 152 | sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; |
Jens Wiklander | c93c9df | 2014-09-04 10:23:27 +0200 | [diff] [blame] | 153 | if (GET_RW(ep->spsr) == MODE_RW_64) |
| 154 | sctlr_elx |= SCTLR_EL1_RES1; |
Soby Mathew | a993c42 | 2016-09-29 14:15:57 +0100 | [diff] [blame] | 155 | else { |
Soby Mathew | a993c42 | 2016-09-29 14:15:57 +0100 | [diff] [blame] | 156 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 157 | * If the target execution state is AArch32 then the following |
| 158 | * fields need to be set. |
| 159 | * |
| 160 | * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE |
| 161 | * instructions are not trapped to EL1. |
| 162 | * |
| 163 | * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI |
| 164 | * instructions are not trapped to EL1. |
| 165 | * |
| 166 | * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the |
| 167 | * CP15DMB, CP15DSB, and CP15ISB instructions. |
Soby Mathew | a993c42 | 2016-09-29 14:15:57 +0100 | [diff] [blame] | 168 | */ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 169 | sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT |
| 170 | | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; |
Soby Mathew | a993c42 | 2016-09-29 14:15:57 +0100 | [diff] [blame] | 171 | } |
| 172 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 173 | /* |
| 174 | * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 |
David Cunado | 4168f2f | 2017-10-02 17:41:39 +0100 | [diff] [blame] | 175 | * and other EL2 registers are set up by cm_preapre_ns_entry() as they |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 176 | * are not part of the stored cpu_context. |
| 177 | */ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 178 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); |
| 179 | |
Varun Wadekar | b6dd0b3 | 2018-05-08 10:52:36 -0700 | [diff] [blame] | 180 | /* |
| 181 | * Base the context ACTLR_EL1 on the current value, as it is |
| 182 | * implementation defined. The context restore process will write |
| 183 | * the value from the context to the actual register and can cause |
| 184 | * problems for processor cores that don't expect certain bits to |
| 185 | * be zero. |
| 186 | */ |
| 187 | actlr_elx = read_actlr_el1(); |
| 188 | write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); |
| 189 | |
David Cunado | 4168f2f | 2017-10-02 17:41:39 +0100 | [diff] [blame] | 190 | if (security_state == SECURE) { |
| 191 | /* |
| 192 | * Initialise PMCR_EL0 for secure context only, setting all |
| 193 | * fields rather than relying on hw. Some fields are |
| 194 | * architecturally UNKNOWN on reset. |
| 195 | * |
| 196 | * PMCR_EL0.LC: Set to one so that cycle counter overflow, that |
| 197 | * is recorded in PMOVSCLR_EL0[31], occurs on the increment |
| 198 | * that changes PMCCNTR_EL0[63] from 1 to 0. |
| 199 | * |
| 200 | * PMCR_EL0.DP: Set to one so that the cycle counter, |
| 201 | * PMCCNTR_EL0 does not count when event counting is prohibited. |
| 202 | * |
| 203 | * PMCR_EL0.X: Set to zero to disable export of events. |
| 204 | * |
| 205 | * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 |
| 206 | * counts on every clock cycle. |
| 207 | */ |
| 208 | pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT |
| 209 | | PMCR_EL0_DP_BIT) |
| 210 | & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)); |
| 211 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0); |
| 212 | } |
| 213 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 214 | /* Populate EL3 state so that we've the right context before doing ERET */ |
| 215 | state = get_el3state_ctx(ctx); |
| 216 | write_ctx_reg(state, CTX_SCR_EL3, scr_el3); |
| 217 | write_ctx_reg(state, CTX_ELR_EL3, ep->pc); |
| 218 | write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); |
| 219 | |
| 220 | /* |
| 221 | * Store the X0-X7 value from the entrypoint into the context |
| 222 | * Use memcpy as we are in control of the layout of the structures |
| 223 | */ |
| 224 | gp_regs = get_gpregs_ctx(ctx); |
| 225 | memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); |
| 226 | } |
| 227 | |
| 228 | /******************************************************************************* |
Dimitris Papastamos | 1e6f93e | 2017-11-07 09:55:29 +0000 | [diff] [blame] | 229 | * Enable architecture extensions on first entry to Non-secure world. |
| 230 | * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise |
| 231 | * it is zero. |
| 232 | ******************************************************************************/ |
| 233 | static void enable_extensions_nonsecure(int el2_unused) |
| 234 | { |
| 235 | #if IMAGE_BL31 |
Dimitris Papastamos | 5bdbb47 | 2017-10-13 12:06:06 +0100 | [diff] [blame] | 236 | #if ENABLE_SPE_FOR_LOWER_ELS |
| 237 | spe_enable(el2_unused); |
| 238 | #endif |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 239 | |
| 240 | #if ENABLE_AMU |
| 241 | amu_enable(el2_unused); |
| 242 | #endif |
David Cunado | ce88eee | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 243 | |
| 244 | #if ENABLE_SVE_FOR_NS |
| 245 | sve_enable(el2_unused); |
| 246 | #endif |
Dimitris Papastamos | 1e6f93e | 2017-11-07 09:55:29 +0000 | [diff] [blame] | 247 | #endif |
| 248 | } |
| 249 | |
| 250 | /******************************************************************************* |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 251 | * The following function initializes the cpu_context for a CPU specified by |
| 252 | * its `cpu_idx` for first use, and sets the initial entrypoint state as |
| 253 | * specified by the entry_point_info structure. |
| 254 | ******************************************************************************/ |
| 255 | void cm_init_context_by_index(unsigned int cpu_idx, |
| 256 | const entry_point_info_t *ep) |
| 257 | { |
| 258 | cpu_context_t *ctx; |
| 259 | ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); |
Antonio Nino Diaz | 28dce9e | 2018-05-22 10:09:10 +0100 | [diff] [blame] | 260 | cm_setup_context(ctx, ep); |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | /******************************************************************************* |
| 264 | * The following function initializes the cpu_context for the current CPU |
| 265 | * for first use, and sets the initial entrypoint state as specified by the |
| 266 | * entry_point_info structure. |
| 267 | ******************************************************************************/ |
| 268 | void cm_init_my_context(const entry_point_info_t *ep) |
| 269 | { |
| 270 | cpu_context_t *ctx; |
| 271 | ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); |
Antonio Nino Diaz | 28dce9e | 2018-05-22 10:09:10 +0100 | [diff] [blame] | 272 | cm_setup_context(ctx, ep); |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 273 | } |
| 274 | |
| 275 | /******************************************************************************* |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 276 | * Prepare the CPU system registers for first entry into secure or normal world |
| 277 | * |
| 278 | * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized |
| 279 | * If execution is requested to non-secure EL1 or svc mode, and the CPU supports |
| 280 | * EL2 then EL2 is disabled by configuring all necessary EL2 registers. |
| 281 | * For all entries, the EL1 registers are initialized from the cpu_context |
| 282 | ******************************************************************************/ |
| 283 | void cm_prepare_el3_exit(uint32_t security_state) |
| 284 | { |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 285 | uint32_t sctlr_elx, scr_el3, mdcr_el2; |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 286 | cpu_context_t *ctx = cm_get_context(security_state); |
Dimitris Papastamos | 1e6f93e | 2017-11-07 09:55:29 +0000 | [diff] [blame] | 287 | int el2_unused = 0; |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 288 | |
| 289 | assert(ctx); |
| 290 | |
| 291 | if (security_state == NON_SECURE) { |
| 292 | scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); |
| 293 | if (scr_el3 & SCR_HCE_BIT) { |
| 294 | /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ |
| 295 | sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), |
| 296 | CTX_SCTLR_EL1); |
Ken Kuang | 00eac15 | 2017-08-23 16:03:29 +0800 | [diff] [blame] | 297 | sctlr_elx &= SCTLR_EE_BIT; |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 298 | sctlr_elx |= SCTLR_EL2_RES1; |
| 299 | write_sctlr_el2(sctlr_elx); |
Jeenu Viswambharan | 2a9b882 | 2017-02-21 14:40:44 +0000 | [diff] [blame] | 300 | } else if (EL_IMPLEMENTED(2)) { |
Dimitris Papastamos | 1e6f93e | 2017-11-07 09:55:29 +0000 | [diff] [blame] | 301 | el2_unused = 1; |
| 302 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 303 | /* |
| 304 | * EL2 present but unused, need to disable safely. |
| 305 | * SCTLR_EL2 can be ignored in this case. |
| 306 | * |
| 307 | * Initialise all fields in HCR_EL2, except HCR_EL2.RW, |
| 308 | * to zero so that Non-secure operations do not trap to |
| 309 | * EL2. |
| 310 | * |
| 311 | * HCR_EL2.RW: Set this field to match SCR_EL3.RW |
| 312 | */ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 313 | write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0); |
| 314 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 315 | /* |
| 316 | * Initialise CPTR_EL2 setting all fields rather than |
| 317 | * relying on the hw. All fields have architecturally |
| 318 | * UNKNOWN reset values. |
| 319 | * |
| 320 | * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 |
| 321 | * accesses to the CPACR_EL1 or CPACR from both |
| 322 | * Execution states do not trap to EL2. |
| 323 | * |
| 324 | * CPTR_EL2.TTA: Set to zero so that Non-secure System |
| 325 | * register accesses to the trace registers from both |
| 326 | * Execution states do not trap to EL2. |
| 327 | * |
| 328 | * CPTR_EL2.TFP: Set to zero so that Non-secure accesses |
| 329 | * to SIMD and floating-point functionality from both |
| 330 | * Execution states do not trap to EL2. |
| 331 | */ |
| 332 | write_cptr_el2(CPTR_EL2_RESET_VAL & |
| 333 | ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT |
| 334 | | CPTR_EL2_TFP_BIT)); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 335 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 336 | /* |
| 337 | * Initiliase CNTHCTL_EL2. All fields are |
| 338 | * architecturally UNKNOWN on reset and are set to zero |
| 339 | * except for field(s) listed below. |
| 340 | * |
| 341 | * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to |
| 342 | * Hyp mode of Non-secure EL0 and EL1 accesses to the |
| 343 | * physical timer registers. |
| 344 | * |
| 345 | * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to |
| 346 | * Hyp mode of Non-secure EL0 and EL1 accesses to the |
| 347 | * physical counter registers. |
| 348 | */ |
| 349 | write_cnthctl_el2(CNTHCTL_RESET_VAL | |
| 350 | EL1PCEN_BIT | EL1PCTEN_BIT); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 351 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 352 | /* |
| 353 | * Initialise CNTVOFF_EL2 to zero as it resets to an |
| 354 | * architecturally UNKNOWN value. |
| 355 | */ |
Soby Mathew | feddfcf | 2014-08-29 14:41:58 +0100 | [diff] [blame] | 356 | write_cntvoff_el2(0); |
| 357 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 358 | /* |
| 359 | * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and |
| 360 | * MPIDR_EL1 respectively. |
| 361 | */ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 362 | write_vpidr_el2(read_midr_el1()); |
| 363 | write_vmpidr_el2(read_mpidr_el1()); |
Sandrine Bailleux | 8b0eafe | 2015-11-25 17:00:44 +0000 | [diff] [blame] | 364 | |
| 365 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 366 | * Initialise VTTBR_EL2. All fields are architecturally |
| 367 | * UNKNOWN on reset. |
| 368 | * |
| 369 | * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage |
| 370 | * 2 address translation is disabled, cache maintenance |
| 371 | * operations depend on the VMID. |
| 372 | * |
| 373 | * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address |
| 374 | * translation is disabled. |
Sandrine Bailleux | 8b0eafe | 2015-11-25 17:00:44 +0000 | [diff] [blame] | 375 | */ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 376 | write_vttbr_el2(VTTBR_RESET_VAL & |
| 377 | ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) |
| 378 | | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); |
| 379 | |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 380 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 381 | * Initialise MDCR_EL2, setting all fields rather than |
| 382 | * relying on hw. Some fields are architecturally |
| 383 | * UNKNOWN on reset. |
| 384 | * |
| 385 | * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and |
| 386 | * EL1 System register accesses to the Debug ROM |
| 387 | * registers are not trapped to EL2. |
| 388 | * |
| 389 | * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 |
| 390 | * System register accesses to the powerdown debug |
| 391 | * registers are not trapped to EL2. |
| 392 | * |
| 393 | * MDCR_EL2.TDA: Set to zero so that System register |
| 394 | * accesses to the debug registers do not trap to EL2. |
| 395 | * |
| 396 | * MDCR_EL2.TDE: Set to zero so that debug exceptions |
| 397 | * are not routed to EL2. |
| 398 | * |
| 399 | * MDCR_EL2.HPME: Set to zero to disable EL2 Performance |
| 400 | * Monitors. |
| 401 | * |
| 402 | * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and |
| 403 | * EL1 accesses to all Performance Monitors registers |
| 404 | * are not trapped to EL2. |
| 405 | * |
| 406 | * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 |
| 407 | * and EL1 accesses to the PMCR_EL0 or PMCR are not |
| 408 | * trapped to EL2. |
| 409 | * |
| 410 | * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the |
| 411 | * architecturally-defined reset value. |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 412 | */ |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 413 | mdcr_el2 = ((MDCR_EL2_RESET_VAL | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 414 | ((read_pmcr_el0() & PMCR_EL0_N_BITS) |
| 415 | >> PMCR_EL0_N_SHIFT)) & |
| 416 | ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
| 417 | | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT |
| 418 | | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT |
| 419 | | MDCR_EL2_TPMCR_BIT)); |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 420 | |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 421 | write_mdcr_el2(mdcr_el2); |
| 422 | |
David Cunado | c14b08e | 2016-11-25 00:21:59 +0000 | [diff] [blame] | 423 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 424 | * Initialise HSTR_EL2. All fields are architecturally |
| 425 | * UNKNOWN on reset. |
| 426 | * |
| 427 | * HSTR_EL2.T<n>: Set all these fields to zero so that |
| 428 | * Non-secure EL0 or EL1 accesses to System registers |
| 429 | * do not trap to EL2. |
David Cunado | c14b08e | 2016-11-25 00:21:59 +0000 | [diff] [blame] | 430 | */ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 431 | write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); |
David Cunado | c14b08e | 2016-11-25 00:21:59 +0000 | [diff] [blame] | 432 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 433 | * Initialise CNTHP_CTL_EL2. All fields are |
| 434 | * architecturally UNKNOWN on reset. |
| 435 | * |
| 436 | * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 |
| 437 | * physical timer and prevent timer interrupts. |
David Cunado | c14b08e | 2016-11-25 00:21:59 +0000 | [diff] [blame] | 438 | */ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 439 | write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & |
| 440 | ~(CNTHP_CTL_ENABLE_BIT)); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 441 | } |
Dimitris Papastamos | 1e6f93e | 2017-11-07 09:55:29 +0000 | [diff] [blame] | 442 | enable_extensions_nonsecure(el2_unused); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 443 | } |
| 444 | |
Dimitris Papastamos | a7921b9 | 2017-10-13 15:27:58 +0100 | [diff] [blame] | 445 | cm_el1_sysregs_context_restore(security_state); |
| 446 | cm_set_next_eret_context(security_state); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 447 | } |
| 448 | |
| 449 | /******************************************************************************* |
Soby Mathew | 2ed46e9 | 2014-07-04 16:02:26 +0100 | [diff] [blame] | 450 | * The next four functions are used by runtime services to save and restore |
| 451 | * EL1 context on the 'cpu_context' structure for the specified security |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 452 | * state. |
| 453 | ******************************************************************************/ |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 454 | void cm_el1_sysregs_context_save(uint32_t security_state) |
| 455 | { |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 456 | cpu_context_t *ctx; |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 457 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 458 | ctx = cm_get_context(security_state); |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 459 | assert(ctx); |
| 460 | |
| 461 | el1_sysregs_context_save(get_sysregs_ctx(ctx)); |
Dimitris Papastamos | a7921b9 | 2017-10-13 15:27:58 +0100 | [diff] [blame] | 462 | |
| 463 | #if IMAGE_BL31 |
| 464 | if (security_state == SECURE) |
| 465 | PUBLISH_EVENT(cm_exited_secure_world); |
| 466 | else |
| 467 | PUBLISH_EVENT(cm_exited_normal_world); |
| 468 | #endif |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 469 | } |
| 470 | |
| 471 | void cm_el1_sysregs_context_restore(uint32_t security_state) |
| 472 | { |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 473 | cpu_context_t *ctx; |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 474 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 475 | ctx = cm_get_context(security_state); |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 476 | assert(ctx); |
| 477 | |
| 478 | el1_sysregs_context_restore(get_sysregs_ctx(ctx)); |
Dimitris Papastamos | a7921b9 | 2017-10-13 15:27:58 +0100 | [diff] [blame] | 479 | |
| 480 | #if IMAGE_BL31 |
| 481 | if (security_state == SECURE) |
| 482 | PUBLISH_EVENT(cm_entering_secure_world); |
| 483 | else |
| 484 | PUBLISH_EVENT(cm_entering_normal_world); |
| 485 | #endif |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 486 | } |
| 487 | |
| 488 | /******************************************************************************* |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 489 | * This function populates ELR_EL3 member of 'cpu_context' pertaining to the |
| 490 | * given security state with the given entrypoint |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 491 | ******************************************************************************/ |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 492 | void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 493 | { |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 494 | cpu_context_t *ctx; |
| 495 | el3_state_t *state; |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 496 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 497 | ctx = cm_get_context(security_state); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 498 | assert(ctx); |
| 499 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 500 | /* Populate EL3 state so that ERET jumps to the correct entry */ |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 501 | state = get_el3state_ctx(ctx); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 502 | write_ctx_reg(state, CTX_ELR_EL3, entrypoint); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 503 | } |
| 504 | |
| 505 | /******************************************************************************* |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 506 | * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' |
| 507 | * pertaining to the given security state |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 508 | ******************************************************************************/ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 509 | void cm_set_elr_spsr_el3(uint32_t security_state, |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 510 | uintptr_t entrypoint, uint32_t spsr) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 511 | { |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 512 | cpu_context_t *ctx; |
| 513 | el3_state_t *state; |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 514 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 515 | ctx = cm_get_context(security_state); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 516 | assert(ctx); |
| 517 | |
| 518 | /* Populate EL3 state so that ERET jumps to the correct entry */ |
| 519 | state = get_el3state_ctx(ctx); |
| 520 | write_ctx_reg(state, CTX_ELR_EL3, entrypoint); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 521 | write_ctx_reg(state, CTX_SPSR_EL3, spsr); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 522 | } |
| 523 | |
| 524 | /******************************************************************************* |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 525 | * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' |
| 526 | * pertaining to the given security state using the value and bit position |
| 527 | * specified in the parameters. It preserves all other bits. |
| 528 | ******************************************************************************/ |
| 529 | void cm_write_scr_el3_bit(uint32_t security_state, |
| 530 | uint32_t bit_pos, |
| 531 | uint32_t value) |
| 532 | { |
| 533 | cpu_context_t *ctx; |
| 534 | el3_state_t *state; |
| 535 | uint32_t scr_el3; |
| 536 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 537 | ctx = cm_get_context(security_state); |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 538 | assert(ctx); |
| 539 | |
| 540 | /* Ensure that the bit position is a valid one */ |
| 541 | assert((1 << bit_pos) & SCR_VALID_BIT_MASK); |
| 542 | |
| 543 | /* Ensure that the 'value' is only a bit wide */ |
| 544 | assert(value <= 1); |
| 545 | |
| 546 | /* |
| 547 | * Get the SCR_EL3 value from the cpu context, clear the desired bit |
| 548 | * and set it to its new value. |
| 549 | */ |
| 550 | state = get_el3state_ctx(ctx); |
| 551 | scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); |
| 552 | scr_el3 &= ~(1 << bit_pos); |
| 553 | scr_el3 |= value << bit_pos; |
| 554 | write_ctx_reg(state, CTX_SCR_EL3, scr_el3); |
| 555 | } |
| 556 | |
| 557 | /******************************************************************************* |
| 558 | * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the |
| 559 | * given security state. |
| 560 | ******************************************************************************/ |
| 561 | uint32_t cm_get_scr_el3(uint32_t security_state) |
| 562 | { |
| 563 | cpu_context_t *ctx; |
| 564 | el3_state_t *state; |
| 565 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 566 | ctx = cm_get_context(security_state); |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 567 | assert(ctx); |
| 568 | |
| 569 | /* Populate EL3 state so that ERET jumps to the correct entry */ |
| 570 | state = get_el3state_ctx(ctx); |
| 571 | return read_ctx_reg(state, CTX_SCR_EL3); |
| 572 | } |
| 573 | |
| 574 | /******************************************************************************* |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 575 | * This function is used to program the context that's used for exception |
| 576 | * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for |
| 577 | * the required security state |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 578 | ******************************************************************************/ |
| 579 | void cm_set_next_eret_context(uint32_t security_state) |
| 580 | { |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 581 | cpu_context_t *ctx; |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 582 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 583 | ctx = cm_get_context(security_state); |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 584 | assert(ctx); |
| 585 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 586 | cm_set_next_context(ctx); |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 587 | } |