blob: 8ac1c3e376458719105eefe370eec506205de277 [file] [log] [blame]
Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Firmware Design
2===============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Dan Handley610e7e12018-03-01 18:44:00 +00004Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot
Paul Beesleyf8640672019-04-12 14:19:42 +01005Requirements (TBBR) Platform Design Document (PDD) for Arm reference
6platforms.
7
8The TBB sequence starts when the platform is powered on and runs up
Douglas Raillardd7c21b72017-06-28 15:23:03 +01009to the stage where it hands-off control to firmware running in the normal
10world in DRAM. This is the cold boot path.
11
Paul Beesleyf8640672019-04-12 14:19:42 +010012TF-A also implements the `Power State Coordination Interface PDD`_ as a
Dan Handley610e7e12018-03-01 18:44:00 +000013runtime service. PSCI is the interface from normal world software to firmware
14implementing power management use-cases (for example, secondary CPU boot,
15hotplug and idle). Normal world software can access TF-A runtime services via
16the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be
Paul Beesleyf8640672019-04-12 14:19:42 +010017used as mandated by the SMC Calling Convention (`SMCCC`_).
Douglas Raillardd7c21b72017-06-28 15:23:03 +010018
Dan Handley610e7e12018-03-01 18:44:00 +000019TF-A implements a framework for configuring and managing interrupts generated
20in either security state. The details of the interrupt management framework
Paul Beesleyf8640672019-04-12 14:19:42 +010021and its design can be found in :ref:`Interrupt Management Framework`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022
Dan Handley610e7e12018-03-01 18:44:00 +000023TF-A also implements a library for setting up and managing the translation
Paul Beesleyf8640672019-04-12 14:19:42 +010024tables. The details of this library can be found in
25:ref:`Translation (XLAT) Tables Library`.
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010026
Dan Handley610e7e12018-03-01 18:44:00 +000027TF-A can be built to support either AArch64 or AArch32 execution state.
Zelalem Aweke023b1a42021-10-21 13:59:45 -050028
Harrison Mutai3005be02023-05-12 09:45:14 +010029.. note::
30 The descriptions in this chapter are for the Arm TrustZone architecture.
31 For changes to the firmware design for the `Arm Confidential Compute
32 Architecture (Arm CCA)`_ please refer to the chapter :ref:`Realm Management
33 Extension (RME)`.
Zelalem Aweke023b1a42021-10-21 13:59:45 -050034
Douglas Raillardd7c21b72017-06-28 15:23:03 +010035Cold boot
36---------
37
38The cold boot path starts when the platform is physically turned on. If
39``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the
40primary CPU, and the remaining CPUs are considered secondary CPUs. The primary
41CPU is chosen through platform-specific means. The cold boot path is mainly
42executed by the primary CPU, other than essential CPU initialization executed by
43all CPUs. The secondary CPUs are kept in a safe platform-specific state until
44the primary CPU has performed enough initialization to boot them.
45
Paul Beesleyf8640672019-04-12 14:19:42 +010046Refer to the :ref:`CPU Reset` for more information on the effect of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010047``COLD_BOOT_SINGLE_CPU`` platform build option.
48
Dan Handley610e7e12018-03-01 18:44:00 +000049The cold boot path in this implementation of TF-A depends on the execution
50state. For AArch64, it is divided into five steps (in order of execution):
Douglas Raillardd7c21b72017-06-28 15:23:03 +010051
52- Boot Loader stage 1 (BL1) *AP Trusted ROM*
53- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
54- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software*
55- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional)
56- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
57
58For AArch32, it is divided into four steps (in order of execution):
59
60- Boot Loader stage 1 (BL1) *AP Trusted ROM*
61- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
62- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software*
63- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
64
Dan Handley610e7e12018-03-01 18:44:00 +000065Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a
Douglas Raillardd7c21b72017-06-28 15:23:03 +010066combination of the following types of memory regions. Each bootloader stage uses
67one or more of these memory regions.
68
69- Regions accessible from both non-secure and secure states. For example,
70 non-trusted SRAM, ROM and DRAM.
71- Regions accessible from only the secure state. For example, trusted SRAM and
72 ROM. The FVPs also implement the trusted DRAM which is statically
73 configured. Additionally, the Base FVPs and Juno development platform
74 configure the TrustZone Controller (TZC) to create a region in the DRAM
75 which is accessible only from the secure state.
76
77The sections below provide the following details:
78
Soby Mathewb1bf0442018-02-16 14:52:52 +000079- dynamic configuration of Boot Loader stages
Douglas Raillardd7c21b72017-06-28 15:23:03 +010080- initialization and execution of the first three stages during cold boot
81- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for
82 AArch32) entrypoint requirements for use by alternative Trusted Boot
83 Firmware in place of the provided BL1 and BL2
84
Soby Mathewb1bf0442018-02-16 14:52:52 +000085Dynamic Configuration during cold boot
86~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
87
88Each of the Boot Loader stages may be dynamically configured if required by the
89platform. The Boot Loader stage may optionally specify a firmware
90configuration file and/or hardware configuration file as listed below:
91
Manish V Badarkheece96fd2020-06-13 09:42:28 +010092- FW_CONFIG - The firmware configuration file. Holds properties shared across
93 all BLx images.
94 An example is the "dtb-registry" node, which contains the information about
95 the other device tree configurations (load-address, size, image_id).
Soby Mathewb1bf0442018-02-16 14:52:52 +000096- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader
97 stages and also by the Normal World Rich OS.
98- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1
99 and BL2.
100- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31.
101- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS
102 (BL32).
103- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted
104 firmware (BL33).
105
106The Arm development platforms use the Flattened Device Tree format for the
107dynamic configuration files.
108
109Each Boot Loader stage can pass up to 4 arguments via registers to the next
110stage. BL2 passes the list of the next images to execute to the *EL3 Runtime
111Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other
112arguments are platform defined. The Arm development platforms use the following
113convention:
114
115- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This
116 structure contains the memory layout available to BL2.
117- When dynamic configuration files are present, the firmware configuration for
118 the next Boot Loader stage is populated in the first available argument and
119 the generic hardware configuration is passed the next available argument.
120 For example,
121
Manish V Badarkheece96fd2020-06-13 09:42:28 +0100122 - FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` to BL2.
123 - TB_FW_CONFIG address is retrieved by BL2 from FW_CONFIG device tree.
Soby Mathewb1bf0442018-02-16 14:52:52 +0000124 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to
125 BL2. Note, ``arg1`` is already used for meminfo_t.
126 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1``
127 to BL31. Note, ``arg0`` is used to pass the list of executable images.
128 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is
129 passed in ``arg2`` to BL31.
130 - For other BL3x images, if the firmware configuration file is loaded by
131 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded
132 then its address is passed in ``arg1``.
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +0100133 - In case of the Arm FVP platform, FW_CONFIG address passed in ``arg1`` to
134 BL31/SP_MIN, and the SOC_FW_CONFIG and HW_CONFIG details are retrieved
135 from FW_CONFIG device tree.
Soby Mathewb1bf0442018-02-16 14:52:52 +0000136
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100137BL1
138~~~
139
140This stage begins execution from the platform's reset vector at EL3. The reset
141address is platform dependent but it is usually located in a Trusted ROM area.
142The BL1 data section is copied to trusted SRAM at runtime.
143
Dan Handley610e7e12018-03-01 18:44:00 +0000144On the Arm development platforms, BL1 code starts execution from the reset
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100145vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied
146to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
147
148The functionality implemented by this stage is as follows.
149
150Determination of boot path
151^^^^^^^^^^^^^^^^^^^^^^^^^^
152
153Whenever a CPU is released from reset, BL1 needs to distinguish between a warm
154boot and a cold boot. This is done using platform-specific mechanisms (see the
Paul Beesleyf8640672019-04-12 14:19:42 +0100155``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case
156of a warm boot, a CPU is expected to continue execution from a separate
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100157entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe
158platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in
Paul Beesleyf8640672019-04-12 14:19:42 +0100159the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot
160path as described in the following sections.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
162This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the
Paul Beesleyf8640672019-04-12 14:19:42 +0100163:ref:`CPU Reset` for more information on the effect of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100164``PROGRAMMABLE_RESET_ADDRESS`` platform build option.
165
166Architectural initialization
167^^^^^^^^^^^^^^^^^^^^^^^^^^^^
168
169BL1 performs minimal architectural initialization as follows.
170
171- Exception vectors
172
173 BL1 sets up simple exception vectors for both synchronous and asynchronous
174 exceptions. The default behavior upon receiving an exception is to populate
175 a status code in the general purpose register ``X0/R0`` and call the
Paul Beesleyf8640672019-04-12 14:19:42 +0100176 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The
177 status code is one of:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100178
179 For AArch64:
180
181 ::
182
183 0x0 : Synchronous exception from Current EL with SP_EL0
184 0x1 : IRQ exception from Current EL with SP_EL0
185 0x2 : FIQ exception from Current EL with SP_EL0
186 0x3 : System Error exception from Current EL with SP_EL0
187 0x4 : Synchronous exception from Current EL with SP_ELx
188 0x5 : IRQ exception from Current EL with SP_ELx
189 0x6 : FIQ exception from Current EL with SP_ELx
190 0x7 : System Error exception from Current EL with SP_ELx
191 0x8 : Synchronous exception from Lower EL using aarch64
192 0x9 : IRQ exception from Lower EL using aarch64
193 0xa : FIQ exception from Lower EL using aarch64
194 0xb : System Error exception from Lower EL using aarch64
195 0xc : Synchronous exception from Lower EL using aarch32
196 0xd : IRQ exception from Lower EL using aarch32
197 0xe : FIQ exception from Lower EL using aarch32
198 0xf : System Error exception from Lower EL using aarch32
199
200 For AArch32:
201
202 ::
203
204 0x10 : User mode
205 0x11 : FIQ mode
206 0x12 : IRQ mode
207 0x13 : SVC mode
208 0x16 : Monitor mode
209 0x17 : Abort mode
210 0x1a : Hypervisor mode
211 0x1b : Undefined mode
212 0x1f : System mode
213
Dan Handley610e7e12018-03-01 18:44:00 +0000214 The ``plat_report_exception()`` implementation on the Arm FVP port programs
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100215 the Versatile Express System LED register in the following format to
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000216 indicate the occurrence of an unexpected exception:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100217
218 ::
219
220 SYS_LED[0] - Security state (Secure=0/Non-Secure=1)
221 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0)
222 For AArch32 it is always 0x0
223 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value
224 of the status code
225
226 A write to the LED register reflects in the System LEDs (S6LED0..7) in the
227 CLCD window of the FVP.
228
229 BL1 does not expect to receive any exceptions other than the SMC exception.
230 For the latter, BL1 installs a simple stub. The stub expects to receive a
231 limited set of SMC types (determined by their function IDs in the general
232 purpose register ``X0/R0``):
233
234 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control
235 to EL3 Runtime Software.
Paul Beesleyf8640672019-04-12 14:19:42 +0100236 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)`
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100237 Design Guide are supported for AArch64 only. These SMCs are currently
238 not supported when BL1 is built for AArch32.
239
240 Any other SMC leads to an assertion failure.
241
242- CPU initialization
243
244 BL1 calls the ``reset_handler()`` function which in turn calls the CPU
245 specific reset handler function (see the section: "CPU specific operations
246 framework").
247
248- Control register setup (for AArch64)
249
250 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I``
251 bit. Alignment and stack alignment checking is enabled by setting the
252 ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to
253 little-endian by clearing the ``SCTLR_EL3.EE`` bit.
254
255 - ``SCR_EL3``. The register width of the next lower exception level is set
256 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap
257 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
258 also set to disable instruction fetches from Non-secure memory when in
259 secure state.
260
261 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the
262 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by
263 clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is
264 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit.
265 Instructions that access the registers associated with Floating Point
266 and Advanced SIMD execution are configured to not trap to EL3 by
267 clearing the ``CPTR_EL3.TFP`` bit.
268
269 - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt
270 mask bit.
271
272 - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and
273 ``MDCR_EL3.TPM``, are set so that accesses to the registers they control
274 do not trap to EL3. AArch64 Secure self-hosted debug is disabled by
275 setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to
276 disable AArch32 Secure self-hosted privileged debug from S-EL1.
277
278- Control register setup (for AArch32)
279
280 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit.
281 Alignment checking is enabled by setting the ``SCTLR.A`` bit.
282 Exception endianness is set to little-endian by clearing the
283 ``SCTLR.EE`` bit.
284
285 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from
286 Non-secure memory when in secure state.
287
288 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1,
289 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality
290 is configured not to trap to undefined mode by clearing the
291 ``CPACR.TRCDIS`` bit.
292
293 - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and
294 system register access to implemented trace registers.
295
296 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point
297 functionality from all Exception levels.
298
299 - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing
300 the Asynchronous data abort interrupt mask bit.
301
302 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure
303 self-hosted privileged debug.
304
305Platform initialization
306^^^^^^^^^^^^^^^^^^^^^^^
307
Dan Handley610e7e12018-03-01 18:44:00 +0000308On Arm platforms, BL1 performs the following platform initializations:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100309
310- Enable the Trusted Watchdog.
311- Initialize the console.
312- Configure the Interconnect to enable hardware coherency.
313- Enable the MMU and map the memory it needs to access.
314- Configure any required platform storage to load the next bootloader image
315 (BL2).
Soby Mathewb1bf0442018-02-16 14:52:52 +0000316- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then
317 load it to the platform defined address and make it available to BL2 via
318 ``arg0``.
Soby Mathewd969a7e2018-06-11 16:40:36 +0100319- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U
320 and NS-BL2U firmware update images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100321
322Firmware Update detection and execution
323^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
324
325After performing platform setup, BL1 common code calls
Paul Beesleyf8640672019-04-12 14:19:42 +0100326``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is
327required or to proceed with the normal boot process. If the platform code
328returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described
329in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is
330required and execution passes to the first image in the
331:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor
332of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor
333contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the
334execution state of the next image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100335
336BL2 image load and execution
337^^^^^^^^^^^^^^^^^^^^^^^^^^^^
338
339In the normal boot flow, BL1 execution continues as follows:
340
341#. BL1 prints the following string from the primary CPU to indicate successful
342 execution of the BL1 stage:
343
344 ::
345
346 "Booting Trusted Firmware"
347
Soby Mathewb1bf0442018-02-16 14:52:52 +0000348#. BL1 loads a BL2 raw binary image from platform storage, at a
349 platform-specific base address. Prior to the load, BL1 invokes
350 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or
351 use the image information. If the BL2 image file is not present or if
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100352 there is not enough free trusted SRAM the following error message is
353 printed:
354
355 ::
356
357 "Failed to load BL2 firmware."
358
Soby Mathewb1bf0442018-02-16 14:52:52 +0000359#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended
360 for platforms to take further action after image load. This function must
361 populate the necessary arguments for BL2, which may also include the memory
362 layout. Further description of the memory layout can be found later
363 in this document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100364
365#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at
366 Secure SVC mode (for AArch32), starting from its load address.
367
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100368BL2
369~~~
370
371BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure
372SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific
373base address (more information can be found later in this document).
374The functionality implemented by BL2 is as follows.
375
376Architectural initialization
377^^^^^^^^^^^^^^^^^^^^^^^^^^^^
378
379For AArch64, BL2 performs the minimal architectural initialization required
Dan Handley610e7e12018-03-01 18:44:00 +0000380for subsequent stages of TF-A and normal world software. EL1 and EL0 are given
Peng Fan9632c9c2020-08-21 10:47:17 +0800381access to Floating Point and Advanced SIMD registers by setting the
Dan Handley610e7e12018-03-01 18:44:00 +0000382``CPACR.FPEN`` bits.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100383
384For AArch32, the minimal architectural initialization required for subsequent
Dan Handley610e7e12018-03-01 18:44:00 +0000385stages of TF-A and normal world software is taken care of in BL1 as both BL1
386and BL2 execute at PL1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100387
388Platform initialization
389^^^^^^^^^^^^^^^^^^^^^^^
390
Dan Handley610e7e12018-03-01 18:44:00 +0000391On Arm platforms, BL2 performs the following platform initializations:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100392
393- Initialize the console.
394- Configure any required platform storage to allow loading further bootloader
395 images.
396- Enable the MMU and map the memory it needs to access.
397- Perform platform security setup to allow access to controlled components.
398- Reserve some memory for passing information to the next bootloader image
399 EL3 Runtime Software and populate it.
400- Define the extents of memory available for loading each subsequent
401 bootloader image.
Soby Mathewb1bf0442018-02-16 14:52:52 +0000402- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``,
403 then parse it.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100404
405Image loading in BL2
406^^^^^^^^^^^^^^^^^^^^
407
Roberto Vargas025946a2018-09-24 17:20:48 +0100408BL2 generic code loads the images based on the list of loadable images
409provided by the platform. BL2 passes the list of executable images
410provided by the platform to the next handover BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100411
Soby Mathewb1bf0442018-02-16 14:52:52 +0000412The list of loadable images provided by the platform may also contain
413dynamic configuration files. The files are loaded and can be parsed as
414needed in the ``bl2_plat_handle_post_image_load()`` function. These
415configuration files can be passed to next Boot Loader stages as arguments
416by updating the corresponding entrypoint information in this function.
417
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100418SCP_BL2 (System Control Processor Firmware) image load
419^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100420
421Some systems have a separate System Control Processor (SCP) for power, clock,
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100422reset and system control. BL2 loads the optional SCP_BL2 image from platform
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100423storage into a platform-specific region of secure memory. The subsequent
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100424handling of SCP_BL2 is platform specific. For example, on the Juno Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100425development platform port the image is transferred into SCP's internal memory
426using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100427memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100428for BL2 execution to continue.
429
430EL3 Runtime Software image load
431^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
432
433BL2 loads the EL3 Runtime Software image from platform storage into a platform-
434specific address in trusted SRAM. If there is not enough memory to load the
Roberto Vargas025946a2018-09-24 17:20:48 +0100435image or image is missing it leads to an assertion failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100436
437AArch64 BL32 (Secure-EL1 Payload) image load
438^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
439
440BL2 loads the optional BL32 image from platform storage into a platform-
441specific region of secure memory. The image executes in the secure world. BL2
442relies on BL31 to pass control to the BL32 image, if present. Hence, BL2
443populates a platform-specific area of memory with the entrypoint/load-address
444of the BL32 image. The value of the Saved Processor Status Register (``SPSR``)
445for entry into BL32 is not determined by BL2, it is initialized by the
446Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for
447managing interaction with BL32. This information is passed to BL31.
448
449BL33 (Non-trusted Firmware) image load
450^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
451
452BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from
453platform storage into non-secure memory as defined by the platform.
454
455BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state
456initialization is complete. Hence, BL2 populates a platform-specific area of
457memory with the entrypoint and Saved Program Status Register (``SPSR``) of the
458normal world software image. The entrypoint is the load address of the BL33
459image. The ``SPSR`` is determined as specified in Section 5.13 of the
Paul Beesleyf8640672019-04-12 14:19:42 +0100460`Power State Coordination Interface PDD`_. This information is passed to the
461EL3 Runtime Software.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100462
463AArch64 BL31 (EL3 Runtime Software) execution
464^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
465
466BL2 execution continues as follows:
467
468#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the
469 BL31 entrypoint. The exception is handled by the SMC exception handler
470 installed by BL1.
471
472#. BL1 turns off the MMU and flushes the caches. It clears the
473 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency
474 and invalidates the TLBs.
475
476#. BL1 passes control to BL31 at the specified entrypoint at EL3.
477
Roberto Vargasb1584272017-11-20 13:36:10 +0000478Running BL2 at EL3 execution level
479~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
480
Dan Handley610e7e12018-03-01 18:44:00 +0000481Some platforms have a non-TF-A Boot ROM that expects the next boot stage
482to execute at EL3. On these platforms, TF-A BL1 is a waste of memory
483as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid
Roberto Vargasb1584272017-11-20 13:36:10 +0000484this waste, a special mode enables BL2 to execute at EL3, which allows
Dan Handley610e7e12018-03-01 18:44:00 +0000485a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600486when the build flag RESET_TO_BL2 is enabled.
487The main differences in this mode are:
Roberto Vargasb1584272017-11-20 13:36:10 +0000488
489#. BL2 includes the reset code and the mailbox mechanism to differentiate
490 cold boot and warm boot. It runs at EL3 doing the arch
491 initialization required for EL3.
492
493#. BL2 does not receive the meminfo information from BL1 anymore. This
494 information can be passed by the Boot ROM or be internal to the
495 BL2 image.
496
497#. Since BL2 executes at EL3, BL2 jumps directly to the next image,
498 instead of invoking the RUN_IMAGE SMC call.
499
500
501We assume 3 different types of BootROM support on the platform:
502
503#. The Boot ROM always jumps to the same address, for both cold
504 and warm boot. In this case, we will need to keep a resident part
505 of BL2 whose memory cannot be reclaimed by any other image. The
506 linker script defines the symbols __TEXT_RESIDENT_START__ and
507 __TEXT_RESIDENT_END__ that allows the platform to configure
508 correctly the memory map.
509#. The platform has some mechanism to indicate the jump address to the
510 Boot ROM. Platform code can then program the jump address with
511 psci_warmboot_entrypoint during cold boot.
512#. The platform has some mechanism to program the reset address using
513 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then
514 program the reset address with psci_warmboot_entrypoint during
515 cold boot, bypassing the boot ROM for warm boot.
516
517In the last 2 cases, no part of BL2 needs to remain resident at
518runtime. In the first 2 cases, we expect the Boot ROM to be able to
519differentiate between warm and cold boot, to avoid loading BL2 again
520during warm boot.
521
522This functionality can be tested with FVP loading the image directly
523in memory and changing the address where the system jumps at reset.
524For example:
525
Dimitris Papastamos25836492018-06-11 11:07:58 +0100526 -C cluster0.cpu0.RVBAR=0x4022000
527 --data cluster0.cpu0=bl2.bin@0x4022000
Roberto Vargasb1584272017-11-20 13:36:10 +0000528
529With this configuration, FVP is like a platform of the first case,
530where the Boot ROM jumps always to the same address. For simplification,
531BL32 is loaded in DRAM in this case, to avoid other images reclaiming
532BL2 memory.
533
534
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100535AArch64 BL31
536~~~~~~~~~~~~
537
538The image for this stage is loaded by BL2 and BL1 passes control to BL31 at
539EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and
540loaded at a platform-specific base address (more information can be found later
541in this document). The functionality implemented by BL31 is as follows.
542
543Architectural initialization
544^^^^^^^^^^^^^^^^^^^^^^^^^^^^
545
546Currently, BL31 performs a similar architectural initialization to BL1 as
547far as system register settings are concerned. Since BL1 code resides in ROM,
548architectural initialization in BL31 allows override of any previous
549initialization done by BL1.
550
551BL31 initializes the per-CPU data framework, which provides a cache of
552frequently accessed per-CPU data optimised for fast, concurrent manipulation
553on different CPUs. This buffer includes pointers to per-CPU contexts, crash
554buffer, CPU reset and power down operations, PSCI data, platform data and so on.
555
556It then replaces the exception vectors populated by BL1 with its own. BL31
557exception vectors implement more elaborate support for handling SMCs since this
558is the only mechanism to access the runtime services implemented by BL31 (PSCI
559for example). BL31 checks each SMC for validity as specified by the
Sandrine Bailleuxd9202df2020-04-17 14:06:52 +0200560`SMC Calling Convention`_ before passing control to the required SMC
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100561handler routine.
562
563BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system
564counter, which is provided by the platform.
565
566Platform initialization
567^^^^^^^^^^^^^^^^^^^^^^^
568
569BL31 performs detailed platform initialization, which enables normal world
570software to function correctly.
571
Dan Handley610e7e12018-03-01 18:44:00 +0000572On Arm platforms, this consists of the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100573
574- Initialize the console.
575- Configure the Interconnect to enable hardware coherency.
576- Enable the MMU and map the memory it needs to access.
577- Initialize the generic interrupt controller.
578- Initialize the power controller device.
579- Detect the system topology.
580
581Runtime services initialization
582^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
583
584BL31 is responsible for initializing the runtime services. One of them is PSCI.
585
586As part of the PSCI initializations, BL31 detects the system topology. It also
587initializes the data structures that implement the state machine used to track
588the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or
589``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster
590that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also
591initializes the locks that protect them. BL31 accesses the state of a CPU or
592cluster immediately after reset and before the data cache is enabled in the
593warm boot path. It is not currently possible to use 'exclusive' based spinlocks,
594therefore BL31 uses locks based on Lamport's Bakery algorithm instead.
595
596The runtime service framework and its initialization is described in more
597detail in the "EL3 runtime services framework" section below.
598
599Details about the status of the PSCI implementation are provided in the
600"Power State Coordination Interface" section below.
601
602AArch64 BL32 (Secure-EL1 Payload) image initialization
603^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
604
605If a BL32 image is present then there must be a matching Secure-EL1 Payload
606Dispatcher (SPD) service (see later for details). During initialization
607that service must register a function to carry out initialization of BL32
608once the runtime services are fully initialized. BL31 invokes such a
609registered function to initialize BL32 before running BL33. This initialization
610is not necessary for AArch32 SPs.
611
612Details on BL32 initialization and the SPD's role are described in the
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100613:ref:`firmware_design_sel1_spd` section below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100614
615BL33 (Non-trusted Firmware) execution
616^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
617
618EL3 Runtime Software initializes the EL2 or EL1 processor context for normal-
619world cold boot, ensuring that no secure state information finds its way into
620the non-secure execution state. EL3 Runtime Software uses the entrypoint
621information provided by BL2 to jump to the Non-trusted firmware image (BL33)
622at the highest available Exception Level (EL2 if available, otherwise EL1).
623
624Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only)
625~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
626
627Some platforms have existing implementations of Trusted Boot Firmware that
Dan Handley610e7e12018-03-01 18:44:00 +0000628would like to use TF-A BL31 for the EL3 Runtime Software. To enable this
629firmware architecture it is important to provide a fully documented and stable
630interface between the Trusted Boot Firmware and BL31.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100631
632Future changes to the BL31 interface will be done in a backwards compatible
633way, and this enables these firmware components to be independently enhanced/
634updated to develop and exploit new functionality.
635
636Required CPU state when calling ``bl31_entrypoint()`` during cold boot
637^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
638
639This function must only be called by the primary CPU.
640
641On entry to this function the calling primary CPU must be executing in AArch64
642EL3, little-endian data access, and all interrupt sources masked:
643
644::
645
646 PSTATE.EL = 3
647 PSTATE.RW = 1
648 PSTATE.DAIF = 0xf
649 SCTLR_EL3.EE = 0
650
651X0 and X1 can be used to pass information from the Trusted Boot Firmware to the
652platform code in BL31:
653
654::
655
Dan Handley610e7e12018-03-01 18:44:00 +0000656 X0 : Reserved for common TF-A information
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100657 X1 : Platform specific information
658
659BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry,
660these will be zero filled prior to invoking platform setup code.
661
662Use of the X0 and X1 parameters
663'''''''''''''''''''''''''''''''
664
665The parameters are platform specific and passed from ``bl31_entrypoint()`` to
666``bl31_early_platform_setup()``. The value of these parameters is never directly
667used by the common BL31 code.
668
669The convention is that ``X0`` conveys information regarding the BL31, BL32 and
670BL33 images from the Trusted Boot firmware and ``X1`` can be used for other
Dan Handley610e7e12018-03-01 18:44:00 +0000671platform specific purpose. This convention allows platforms which use TF-A's
672BL1 and BL2 images to transfer additional platform specific information from
673Secure Boot without conflicting with future evolution of TF-A using ``X0`` to
674pass a ``bl31_params`` structure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100675
676BL31 common and SPD initialization code depends on image and entrypoint
677information about BL33 and BL32, which is provided via BL31 platform APIs.
678This information is required until the start of execution of BL33. This
679information can be provided in a platform defined manner, e.g. compiled into
680the platform code in BL31, or provided in a platform defined memory location
681by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the
682Cold boot Initialization parameters. This data may need to be cleaned out of
683the CPU caches if it is provided by an earlier boot stage and then accessed by
684BL31 platform code before the caches are enabled.
685
Dan Handley610e7e12018-03-01 18:44:00 +0000686TF-A's BL2 implementation passes a ``bl31_params`` structure in
687``X0`` and the Arm development platforms interpret this in the BL31 platform
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100688code.
689
690MMU, Data caches & Coherency
691''''''''''''''''''''''''''''
692
693BL31 does not depend on the enabled state of the MMU, data caches or
694interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled
695on entry, these should be enabled during ``bl31_plat_arch_setup()``.
696
697Data structures used in the BL31 cold boot interface
698''''''''''''''''''''''''''''''''''''''''''''''''''''
699
700These structures are designed to support compatibility and independent
701evolution of the structures and the firmware images. For example, a version of
702BL31 that can interpret the BL3x image information from different versions of
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100703BL2, a platform that uses an extended entry_point_info structure to convey
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100704additional register information to BL31, or a ELF image loader that can convey
705more details about the firmware images.
706
707To support these scenarios the structures are versioned and sized, which enables
708BL31 to detect which information is present and respond appropriately. The
709``param_header`` is defined to capture this information:
710
711.. code:: c
712
713 typedef struct param_header {
714 uint8_t type; /* type of the structure */
715 uint8_t version; /* version of this structure */
716 uint16_t size; /* size of this structure in bytes */
717 uint32_t attr; /* attributes: unused bits SBZ */
718 } param_header_t;
719
720The structures using this format are ``entry_point_info``, ``image_info`` and
721``bl31_params``. The code that allocates and populates these structures must set
722the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined
723to simplify this action.
724
725Required CPU state for BL31 Warm boot initialization
726^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
727
Dan Handley610e7e12018-03-01 18:44:00 +0000728When requesting a CPU power-on, or suspending a running CPU, TF-A provides
729the platform power management code with a Warm boot initialization
730entry-point, to be invoked by the CPU immediately after the reset handler.
731On entry to the Warm boot initialization function the calling CPU must be in
732AArch64 EL3, little-endian data access and all interrupt sources masked:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100733
734::
735
736 PSTATE.EL = 3
737 PSTATE.RW = 1
738 PSTATE.DAIF = 0xf
739 SCTLR_EL3.EE = 0
740
741The PSCI implementation will initialize the processor state and ensure that the
742platform power management code is then invoked as required to initialize all
743necessary system, cluster and CPU resources.
744
745AArch32 EL3 Runtime Software entrypoint interface
746~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
747
748To enable this firmware architecture it is important to provide a fully
749documented and stable interface between the Trusted Boot Firmware and the
750AArch32 EL3 Runtime Software.
751
752Future changes to the entrypoint interface will be done in a backwards
753compatible way, and this enables these firmware components to be independently
754enhanced/updated to develop and exploit new functionality.
755
756Required CPU state when entering during cold boot
757^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
758
759This function must only be called by the primary CPU.
760
761On entry to this function the calling primary CPU must be executing in AArch32
762EL3, little-endian data access, and all interrupt sources masked:
763
764::
765
766 PSTATE.AIF = 0x7
767 SCTLR.EE = 0
768
769R0 and R1 are used to pass information from the Trusted Boot Firmware to the
770platform code in AArch32 EL3 Runtime Software:
771
772::
773
Dan Handley610e7e12018-03-01 18:44:00 +0000774 R0 : Reserved for common TF-A information
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100775 R1 : Platform specific information
776
777Use of the R0 and R1 parameters
778'''''''''''''''''''''''''''''''
779
780The parameters are platform specific and the convention is that ``R0`` conveys
781information regarding the BL3x images from the Trusted Boot firmware and ``R1``
782can be used for other platform specific purpose. This convention allows
Dan Handley610e7e12018-03-01 18:44:00 +0000783platforms which use TF-A's BL1 and BL2 images to transfer additional platform
784specific information from Secure Boot without conflicting with future
785evolution of TF-A using ``R0`` to pass a ``bl_params`` structure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100786
787The AArch32 EL3 Runtime Software is responsible for entry into BL33. This
788information can be obtained in a platform defined manner, e.g. compiled into
789the AArch32 EL3 Runtime Software, or provided in a platform defined memory
790location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware
791via the Cold boot Initialization parameters. This data may need to be cleaned
792out of the CPU caches if it is provided by an earlier boot stage and then
793accessed by AArch32 EL3 Runtime Software before the caches are enabled.
794
Dan Handley610e7e12018-03-01 18:44:00 +0000795When using AArch32 EL3 Runtime Software, the Arm development platforms pass a
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100796``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime
797Software platform code.
798
799MMU, Data caches & Coherency
800''''''''''''''''''''''''''''
801
802AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU,
803data caches or interconnect coherency in its entrypoint. They must be explicitly
804enabled if required.
805
806Data structures used in cold boot interface
807'''''''''''''''''''''''''''''''''''''''''''
808
809The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead
810of ``bl31_params``. The ``bl_params`` structure is based on the convention
811described in AArch64 BL31 cold boot interface section.
812
813Required CPU state for warm boot initialization
814^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
815
816When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3
817Runtime Software must ensure execution of a warm boot initialization entrypoint.
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100818If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false,
Dan Handley610e7e12018-03-01 18:44:00 +0000819then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm
820boot entrypoint by arranging for the BL1 platform function,
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100821plat_get_my_entrypoint(), to return a non-zero value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100822
823In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian
824data access and all interrupt sources masked:
825
826::
827
828 PSTATE.AIF = 0x7
829 SCTLR.EE = 0
830
Dan Handley610e7e12018-03-01 18:44:00 +0000831The warm boot entrypoint may be implemented by using TF-A
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100832``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil
Paul Beesleyf8640672019-04-12 14:19:42 +0100833the pre-requisites mentioned in the
834:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100835
836EL3 runtime services framework
837------------------------------
838
839Software executing in the non-secure state and in the secure state at exception
840levels lower than EL3 will request runtime services using the Secure Monitor
841Call (SMC) instruction. These requests will follow the convention described in
842the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function
843identifiers to each SMC request and describes how arguments are passed and
844returned.
845
846The EL3 runtime services framework enables the development of services by
847different providers that can be easily integrated into final product firmware.
848The following sections describe the framework which facilitates the
849registration, initialization and use of runtime services in EL3 Runtime
850Software (BL31).
851
852The design of the runtime services depends heavily on the concepts and
853definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning
854Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling
855conventions. Please refer to that document for more detailed explanation of
856these terms.
857
858The following runtime services are expected to be implemented first. They have
859not all been instantiated in the current implementation.
860
861#. Standard service calls
862
863 This service is for management of the entire system. The Power State
864 Coordination Interface (`PSCI`_) is the first set of standard service calls
Dan Handley610e7e12018-03-01 18:44:00 +0000865 defined by Arm (see PSCI section later).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100866
867#. Secure-EL1 Payload Dispatcher service
868
869 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then
870 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor
871 context between the normal world (EL1/EL2) and trusted world (Secure-EL1).
872 The Secure Monitor will make these world switches in response to SMCs. The
873 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted
874 Application Call OEN ranges.
875
876 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is
877 not defined by the `SMCCC`_ or any other standard. As a result, each
878 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000879 service - within TF-A this service is referred to as the Secure-EL1 Payload
880 Dispatcher (SPD).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100881
Dan Handley610e7e12018-03-01 18:44:00 +0000882 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher
883 (TSPD). Details of SPD design and TSP/TSPD operation are described in the
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100884 :ref:`firmware_design_sel1_spd` section below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100885
886#. CPU implementation service
887
888 This service will provide an interface to CPU implementation specific
889 services for a given platform e.g. access to processor errata workarounds.
890 This service is currently unimplemented.
891
Dan Handley610e7e12018-03-01 18:44:00 +0000892Additional services for Arm Architecture, SiP and OEM calls can be implemented.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100893Each implemented service handles a range of SMC function identifiers as
894described in the `SMCCC`_.
895
896Registration
897~~~~~~~~~~~~
898
899A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying
900the name of the service, the range of OENs covered, the type of service and
901initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``).
Chris Kay33bfc5e2023-02-14 11:30:04 +0000902This structure is allocated in a special ELF section ``.rt_svc_descs``, enabling
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100903the framework to find all service descriptors included into BL31.
904
905The specific service for a SMC Function is selected based on the OEN and call
906type of the Function ID, and the framework uses that information in the service
907descriptor to identify the handler for the SMC Call.
908
909The service descriptors do not include information to identify the precise set
910of SMC function identifiers supported by this service implementation, the
911security state from which such calls are valid nor the capability to support
91264-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately
913to these aspects of a SMC call is the responsibility of the service
914implementation, the framework is focused on integration of services from
915different providers and minimizing the time taken by the framework before the
916service handler is invoked.
917
918Details of the parameters, requirements and behavior of the initialization and
919call handling functions are provided in the following sections.
920
921Initialization
922~~~~~~~~~~~~~~
923
924``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services
925framework running on the primary CPU during cold boot as part of the BL31
926initialization. This happens prior to initializing a Trusted OS and running
927Normal world boot firmware that might in turn use these services.
928Initialization involves validating each of the declared runtime service
929descriptors, calling the service initialization function and populating the
930index used for runtime lookup of the service.
931
932The BL31 linker script collects all of the declared service descriptors into a
933single array and defines symbols that allow the framework to locate and traverse
934the array, and determine its size.
935
936The framework does basic validation of each descriptor to halt firmware
937initialization if service declaration errors are detected. The framework does
938not check descriptors for the following error conditions, and may behave in an
939unpredictable manner under such scenarios:
940
941#. Overlapping OEN ranges
942#. Multiple descriptors for the same range of OENs and ``call_type``
943#. Incorrect range of owning entity numbers for a given ``call_type``
944
945Once validated, the service ``init()`` callback is invoked. This function carries
946out any essential EL3 initialization before servicing requests. The ``init()``
947function is only invoked on the primary CPU during cold boot. If the service
948uses per-CPU data this must either be initialized for all CPUs during this call,
949or be done lazily when a CPU first issues an SMC call to that service. If
950``init()`` returns anything other than ``0``, this is treated as an initialization
951error and the service is ignored: this does not cause the firmware to halt.
952
953The OEN and call type fields present in the SMC Function ID cover a total of
954128 distinct services, but in practice a single descriptor can cover a range of
955OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a
956service handler, the framework uses an array of 128 indices that map every
957distinct OEN/call-type combination either to one of the declared services or to
958indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is
959populated for all of the OENs covered by a service after the service ``init()``
960function has reported success. So a service that fails to initialize will never
961have it's ``handle()`` function invoked.
962
963The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC
964Function ID call type and OEN onto a specific service handler in the
965``rt_svc_descs[]`` array.
966
967|Image 1|
968
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -0500969.. _handling-an-smc:
970
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100971Handling an SMC
972~~~~~~~~~~~~~~~
973
974When the EL3 runtime services framework receives a Secure Monitor Call, the SMC
975Function ID is passed in W0 from the lower exception level (as per the
976`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an
977SMC Function which indicates the SMC64 calling convention: such calls are
978ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF``
979in R0/X0.
980
981Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC
982Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The
983resulting value might indicate a service that has no handler, in this case the
984framework will also report an Unknown SMC Function ID. Otherwise, the value is
985used as a further index into the ``rt_svc_descs[]`` array to locate the required
986service and handler.
987
988The service's ``handle()`` callback is provided with five of the SMC parameters
989directly, the others are saved into memory for retrieval (if needed) by the
990handler. The handler is also provided with an opaque ``handle`` for use with the
991supporting library for parameter retrieval, setting return values and context
Olivier Deprez33dd8452022-10-11 15:38:27 +0200992manipulation. The ``flags`` parameter indicates the security state of the caller
993and the state of the SVE hint bit per the SMCCCv1.3. The framework finally sets
994up the execution stack for the handler, and invokes the services ``handle()``
995function.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100996
Madhukar Pappireddy20be0772019-11-09 23:28:08 -0600997On return from the handler the result registers are populated in X0-X7 as needed
998before restoring the stack and CPU state and returning from the original SMC.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100999
Jeenu Viswambharancbb40d52017-10-18 14:30:53 +01001000Exception Handling Framework
1001----------------------------
1002
johpow017402f072020-07-28 13:07:25 -05001003Please refer to the :ref:`Exception Handling Framework` document.
Jeenu Viswambharancbb40d52017-10-18 14:30:53 +01001004
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001005Power State Coordination Interface
1006----------------------------------
1007
1008TODO: Provide design walkthrough of PSCI implementation.
1009
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001010The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the
1011mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001012`Power State Coordination Interface PDD`_ are implemented. The table lists
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001013the PSCI v1.1 APIs and their support in generic code.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001014
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001015An API implementation might have a dependency on platform code e.g. CPU_SUSPEND
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001016requires the platform to export a part of the implementation. Hence the level
1017of support of the mandatory APIs depends upon the support exported by the
1018platform port as well. The Juno and FVP (all variants) platforms export all the
1019required support.
1020
1021+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001022| PSCI v1.1 API | Supported | Comments |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001023+=============================+=============+===============================+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001024| ``PSCI_VERSION`` | Yes | The version returned is 1.1 |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001025+-----------------------------+-------------+-------------------------------+
1026| ``CPU_SUSPEND`` | Yes\* | |
1027+-----------------------------+-------------+-------------------------------+
1028| ``CPU_OFF`` | Yes\* | |
1029+-----------------------------+-------------+-------------------------------+
1030| ``CPU_ON`` | Yes\* | |
1031+-----------------------------+-------------+-------------------------------+
1032| ``AFFINITY_INFO`` | Yes | |
1033+-----------------------------+-------------+-------------------------------+
1034| ``MIGRATE`` | Yes\*\* | |
1035+-----------------------------+-------------+-------------------------------+
1036| ``MIGRATE_INFO_TYPE`` | Yes\*\* | |
1037+-----------------------------+-------------+-------------------------------+
1038| ``MIGRATE_INFO_CPU`` | Yes\*\* | |
1039+-----------------------------+-------------+-------------------------------+
1040| ``SYSTEM_OFF`` | Yes\* | |
1041+-----------------------------+-------------+-------------------------------+
1042| ``SYSTEM_RESET`` | Yes\* | |
1043+-----------------------------+-------------+-------------------------------+
1044| ``PSCI_FEATURES`` | Yes | |
1045+-----------------------------+-------------+-------------------------------+
1046| ``CPU_FREEZE`` | No | |
1047+-----------------------------+-------------+-------------------------------+
1048| ``CPU_DEFAULT_SUSPEND`` | No | |
1049+-----------------------------+-------------+-------------------------------+
1050| ``NODE_HW_STATE`` | Yes\* | |
1051+-----------------------------+-------------+-------------------------------+
1052| ``SYSTEM_SUSPEND`` | Yes\* | |
1053+-----------------------------+-------------+-------------------------------+
1054| ``PSCI_SET_SUSPEND_MODE`` | No | |
1055+-----------------------------+-------------+-------------------------------+
1056| ``PSCI_STAT_RESIDENCY`` | Yes\* | |
1057+-----------------------------+-------------+-------------------------------+
1058| ``PSCI_STAT_COUNT`` | Yes\* | |
1059+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001060| ``SYSTEM_RESET2`` | Yes\* | |
1061+-----------------------------+-------------+-------------------------------+
1062| ``MEM_PROTECT`` | Yes\* | |
1063+-----------------------------+-------------+-------------------------------+
1064| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | |
1065+-----------------------------+-------------+-------------------------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001066
1067\*Note : These PSCI APIs require platform power management hooks to be
1068registered with the generic PSCI code to be supported.
1069
1070\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher
1071hooks to be registered with the generic PSCI code to be supported.
1072
Dan Handley610e7e12018-03-01 18:44:00 +00001073The PSCI implementation in TF-A is a library which can be integrated with
1074AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to
1075integrating PSCI library with AArch32 EL3 Runtime Software can be found
Paul Beesleyf8640672019-04-12 14:19:42 +01001076at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
1077
1078.. _firmware_design_sel1_spd:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001079
1080Secure-EL1 Payloads and Dispatchers
1081-----------------------------------
1082
1083On a production system that includes a Trusted OS running in Secure-EL1/EL0,
1084the Trusted OS is coupled with a companion runtime service in the BL31
1085firmware. This service is responsible for the initialisation of the Trusted
1086OS and all communications with it. The Trusted OS is the BL32 stage of the
Dan Handley610e7e12018-03-01 18:44:00 +00001087boot flow in TF-A. The firmware will attempt to locate, load and execute a
1088BL32 image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001089
Dan Handley610e7e12018-03-01 18:44:00 +00001090TF-A uses a more general term for the BL32 software that runs at Secure-EL1 -
1091the *Secure-EL1 Payload* - as it is not always a Trusted OS.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001092
Dan Handley610e7e12018-03-01 18:44:00 +00001093TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload
1094Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a
1095production system using the Runtime Services Framework. On such a system, the
1096Test BL32 image and service are replaced by the Trusted OS and its dispatcher
1097service. The TF-A build system expects that the dispatcher will define the
1098build flag ``NEED_BL32`` to enable it to include the BL32 in the build either
1099as a binary or to compile from source depending on whether the ``BL32`` build
1100option is specified or not.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001101
1102The TSP runs in Secure-EL1. It is designed to demonstrate synchronous
1103communication with the normal-world software running in EL1/EL2. Communication
1104is initiated by the normal-world software
1105
1106- either directly through a Fast SMC (as defined in the `SMCCC`_)
1107
1108- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn
1109 informs the TSPD about the requested power management operation. This allows
1110 the TSP to prepare for or respond to the power state change
1111
1112The TSPD service is responsible for.
1113
1114- Initializing the TSP
1115
1116- Routing requests and responses between the secure and the non-secure
1117 states during the two types of communications just described
1118
1119Initializing a BL32 Image
1120~~~~~~~~~~~~~~~~~~~~~~~~~
1121
1122The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing
1123the BL32 image. It needs access to the information passed by BL2 to BL31 to do
1124so. This is provided by:
1125
1126.. code:: c
1127
1128 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t);
1129
1130which returns a reference to the ``entry_point_info`` structure corresponding to
1131the image which will be run in the specified security state. The SPD uses this
1132API to get entry point information for the SECURE image, BL32.
1133
1134In the absence of a BL32 image, BL31 passes control to the normal world
1135bootloader image (BL33). When the BL32 image is present, it is typical
1136that the SPD wants control to be passed to BL32 first and then later to BL33.
1137
1138To do this the SPD has to register a BL32 initialization function during
1139initialization of the SPD service. The BL32 initialization function has this
1140prototype:
1141
1142.. code:: c
1143
1144 int32_t init(void);
1145
1146and is registered using the ``bl31_register_bl32_init()`` function.
1147
Dan Handley610e7e12018-03-01 18:44:00 +00001148TF-A supports two approaches for the SPD to pass control to BL32 before
1149returning through EL3 and running the non-trusted firmware (BL33):
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001150
1151#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to
1152 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in
1153 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by
1154 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``.
1155
1156 When the BL32 has completed initialization at Secure-EL1, it returns to
1157 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On
1158 receipt of this SMC, the SPD service handler should switch the CPU context
1159 from trusted to normal world and use the ``bl31_set_next_image_type()`` and
1160 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to
1161 the normal world firmware BL33. On return from the handler the framework
1162 will exit to EL2 and run BL33.
1163
1164#. The BL32 setup function registers an initialization function using
1165 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to
1166 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32
1167 entrypoint.
Paul Beesleyba3ed402019-03-13 16:20:44 +00001168
1169 .. note::
1170 The Test SPD service included with TF-A provides one implementation
1171 of such a mechanism.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001172
1173 On completion BL32 returns control to BL31 via a SMC, and on receipt the
1174 SPD service handler invokes the synchronous call return mechanism to return
1175 to the BL32 initialization function. On return from this function,
1176 ``bl31_main()`` will set up the return to the normal world firmware BL33 and
1177 continue the boot process in the normal world.
1178
Jeenu Viswambharanb60420a2017-08-24 15:43:44 +01001179Crash Reporting in BL31
1180-----------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001181
1182BL31 implements a scheme for reporting the processor state when an unhandled
1183exception is encountered. The reporting mechanism attempts to preserve all the
1184register contents and report it via a dedicated UART (PL011 console). BL31
1185reports the general purpose, EL3, Secure EL1 and some EL2 state registers.
1186
1187A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via
1188the per-CPU pointer cache. The implementation attempts to minimise the memory
1189required for this feature. The file ``crash_reporting.S`` contains the
1190implementation for crash reporting.
1191
1192The sample crash output is shown below.
1193
1194::
1195
Alexei Fedorov813c9f92020-03-03 13:31:58 +00001196 x0 = 0x000000002a4a0000
1197 x1 = 0x0000000000000001
1198 x2 = 0x0000000000000002
1199 x3 = 0x0000000000000003
1200 x4 = 0x0000000000000004
1201 x5 = 0x0000000000000005
1202 x6 = 0x0000000000000006
1203 x7 = 0x0000000000000007
1204 x8 = 0x0000000000000008
1205 x9 = 0x0000000000000009
1206 x10 = 0x0000000000000010
1207 x11 = 0x0000000000000011
1208 x12 = 0x0000000000000012
1209 x13 = 0x0000000000000013
1210 x14 = 0x0000000000000014
1211 x15 = 0x0000000000000015
1212 x16 = 0x0000000000000016
1213 x17 = 0x0000000000000017
1214 x18 = 0x0000000000000018
1215 x19 = 0x0000000000000019
1216 x20 = 0x0000000000000020
1217 x21 = 0x0000000000000021
1218 x22 = 0x0000000000000022
1219 x23 = 0x0000000000000023
1220 x24 = 0x0000000000000024
1221 x25 = 0x0000000000000025
1222 x26 = 0x0000000000000026
1223 x27 = 0x0000000000000027
1224 x28 = 0x0000000000000028
1225 x29 = 0x0000000000000029
1226 x30 = 0x0000000088000b78
1227 scr_el3 = 0x000000000003073d
1228 sctlr_el3 = 0x00000000b0cd183f
1229 cptr_el3 = 0x0000000000000000
1230 tcr_el3 = 0x000000008080351c
1231 daif = 0x00000000000002c0
1232 mair_el3 = 0x00000000004404ff
1233 spsr_el3 = 0x0000000060000349
1234 elr_el3 = 0x0000000088000114
1235 ttbr0_el3 = 0x0000000004018201
1236 esr_el3 = 0x00000000be000000
1237 far_el3 = 0x0000000000000000
1238 spsr_el1 = 0x0000000000000000
1239 elr_el1 = 0x0000000000000000
1240 spsr_abt = 0x0000000000000000
1241 spsr_und = 0x0000000000000000
1242 spsr_irq = 0x0000000000000000
1243 spsr_fiq = 0x0000000000000000
1244 sctlr_el1 = 0x0000000030d00800
1245 actlr_el1 = 0x0000000000000000
1246 cpacr_el1 = 0x0000000000000000
1247 csselr_el1 = 0x0000000000000000
1248 sp_el1 = 0x0000000000000000
1249 esr_el1 = 0x0000000000000000
1250 ttbr0_el1 = 0x0000000000000000
1251 ttbr1_el1 = 0x0000000000000000
1252 mair_el1 = 0x0000000000000000
1253 amair_el1 = 0x0000000000000000
1254 tcr_el1 = 0x0000000000000000
1255 tpidr_el1 = 0x0000000000000000
1256 tpidr_el0 = 0x0000000000000000
1257 tpidrro_el0 = 0x0000000000000000
1258 par_el1 = 0x0000000000000000
1259 mpidr_el1 = 0x0000000080000000
1260 afsr0_el1 = 0x0000000000000000
1261 afsr1_el1 = 0x0000000000000000
1262 contextidr_el1 = 0x0000000000000000
1263 vbar_el1 = 0x0000000000000000
1264 cntp_ctl_el0 = 0x0000000000000000
1265 cntp_cval_el0 = 0x0000000000000000
1266 cntv_ctl_el0 = 0x0000000000000000
1267 cntv_cval_el0 = 0x0000000000000000
1268 cntkctl_el1 = 0x0000000000000000
1269 sp_el0 = 0x0000000004014940
1270 isr_el1 = 0x0000000000000000
1271 dacr32_el2 = 0x0000000000000000
1272 ifsr32_el2 = 0x0000000000000000
1273 icc_hppir0_el1 = 0x00000000000003ff
1274 icc_hppir1_el1 = 0x00000000000003ff
1275 icc_ctlr_el3 = 0x0000000000080400
1276 gicd_ispendr regs (Offsets 0x200-0x278)
1277 Offset Value
1278 0x200: 0x0000000000000000
1279 0x208: 0x0000000000000000
1280 0x210: 0x0000000000000000
1281 0x218: 0x0000000000000000
1282 0x220: 0x0000000000000000
1283 0x228: 0x0000000000000000
1284 0x230: 0x0000000000000000
1285 0x238: 0x0000000000000000
1286 0x240: 0x0000000000000000
1287 0x248: 0x0000000000000000
1288 0x250: 0x0000000000000000
1289 0x258: 0x0000000000000000
1290 0x260: 0x0000000000000000
1291 0x268: 0x0000000000000000
1292 0x270: 0x0000000000000000
1293 0x278: 0x0000000000000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001294
1295Guidelines for Reset Handlers
1296-----------------------------
1297
Dan Handley610e7e12018-03-01 18:44:00 +00001298TF-A implements a framework that allows CPU and platform ports to perform
1299actions very early after a CPU is released from reset in both the cold and warm
1300boot paths. This is done by calling the ``reset_handler()`` function in both
1301the BL1 and BL31 images. It in turn calls the platform and CPU specific reset
1302handling functions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001303
1304Details for implementing a CPU specific reset handler can be found in
1305Section 8. Details for implementing a platform specific reset handler can be
Paul Beesleyf8640672019-04-12 14:19:42 +01001306found in the :ref:`Porting Guide` (see the ``plat_reset_handler()`` function).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001307
1308When adding functionality to a reset handler, keep in mind that if a different
1309reset handling behavior is required between the first and the subsequent
1310invocations of the reset handling code, this should be detected at runtime.
1311In other words, the reset handler should be able to detect whether an action has
1312already been performed and act as appropriate. Possible courses of actions are,
1313e.g. skip the action the second time, or undo/redo it.
1314
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05001315.. _configuring-secure-interrupts:
1316
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001317Configuring secure interrupts
1318-----------------------------
1319
1320The GIC driver is responsible for performing initial configuration of secure
1321interrupts on the platform. To this end, the platform is expected to provide the
1322GIC driver (either GICv2 or GICv3, as selected by the platform) with the
1323interrupt configuration during the driver initialisation.
1324
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001325Secure interrupt configuration are specified in an array of secure interrupt
1326properties. In this scheme, in both GICv2 and GICv3 driver data structures, the
1327``interrupt_props`` member points to an array of interrupt properties. Each
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00001328element of the array specifies the interrupt number and its attributes
1329(priority, group, configuration). Each element of the array shall be populated
1330by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments:
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001331
Ming Huang1bea7aa2023-02-01 14:03:44 +08001332- 13-bit interrupt number,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001333
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001334- 8-bit interrupt priority,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001335
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001336- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``,
1337 ``INTR_TYPE_NS``),
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001338
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001339- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or
1340 ``GIC_INTR_CFG_EDGE``).
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001341
Paul Beesleyf8640672019-04-12 14:19:42 +01001342.. _firmware_design_cpu_ops_fwk:
1343
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001344CPU specific operations framework
1345---------------------------------
1346
Dan Handley610e7e12018-03-01 18:44:00 +00001347Certain aspects of the Armv8-A architecture are implementation defined,
1348that is, certain behaviours are not architecturally defined, but must be
1349defined and documented by individual processor implementations. TF-A
1350implements a framework which categorises the common implementation defined
1351behaviours and allows a processor to export its implementation of that
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001352behaviour. The categories are:
1353
1354#. Processor specific reset sequence.
1355
1356#. Processor specific power down sequences.
1357
1358#. Processor specific register dumping as a part of crash reporting.
1359
1360#. Errata status reporting.
1361
1362Each of the above categories fulfils a different requirement.
1363
1364#. allows any processor specific initialization before the caches and MMU
1365 are turned on, like implementation of errata workarounds, entry into
1366 the intra-cluster coherency domain etc.
1367
1368#. allows each processor to implement the power down sequence mandated in
1369 its Technical Reference Manual (TRM).
1370
1371#. allows a processor to provide additional information to the developer
1372 in the event of a crash, for example Cortex-A53 has registers which
1373 can expose the data cache contents.
1374
1375#. allows a processor to define a function that inspects and reports the status
1376 of all errata workarounds on that processor.
1377
1378Please note that only 2. is mandated by the TRM.
1379
1380The CPU specific operations framework scales to accommodate a large number of
1381different CPUs during power down and reset handling. The platform can specify
1382any CPU optimization it wants to enable for each CPU. It can also specify
1383the CPU errata workarounds to be applied for each CPU type during reset
1384handling by defining CPU errata compile time macros. Details on these macros
Paul Beesleyf8640672019-04-12 14:19:42 +01001385can be found in the :ref:`Arm CPU Specific Build Macros` document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001386
1387The CPU specific operations framework depends on the ``cpu_ops`` structure which
1388needs to be exported for each type of CPU in the platform. It is defined in
1389``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``,
1390``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and
1391``cpu_reg_dump()``.
1392
1393The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with
1394suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S``
1395exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform
1396configuration, these CPU specific files must be included in the build by
1397the platform makefile. The generic CPU specific operations framework code exists
1398in ``lib/cpus/aarch64/cpu_helpers.S``.
1399
1400CPU specific Reset Handling
1401~~~~~~~~~~~~~~~~~~~~~~~~~~~
1402
1403After a reset, the state of the CPU when it calls generic reset handler is:
1404MMU turned off, both instruction and data caches turned off and not part
1405of any coherency domain.
1406
1407The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow
1408the platform to perform any system initialization required and any system
1409errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads
1410the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops``
1411array and returns it. Note that only the part number and implementer fields
1412in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in
1413the returned ``cpu_ops`` is then invoked which executes the required reset
1414handling for that CPU and also any errata workarounds enabled by the platform.
1415This function must preserve the values of general purpose registers x20 to x29.
1416
1417Refer to Section "Guidelines for Reset Handlers" for general guidelines
1418regarding placement of code in a reset handler.
1419
1420CPU specific power down sequence
1421~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1422
1423During the BL31 initialization sequence, the pointer to the matching ``cpu_ops``
1424entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly
1425retrieved during power down sequences.
1426
1427Various CPU drivers register handlers to perform power down at certain power
1428levels for that specific CPU. The PSCI service, upon receiving a power down
1429request, determines the highest power level at which to execute power down
1430sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to
1431pick the right power down handler for the requested level. The function
1432retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further
1433retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the
1434requested power level is higher than what a CPU driver supports, the handler
1435registered for highest level is invoked.
1436
1437At runtime the platform hooks for power down are invoked by the PSCI service to
1438perform platform specific operations during a power down sequence, for example
1439turning off CCI coherency during a cluster power down.
1440
1441CPU specific register reporting during crash
1442~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1443
1444If the crash reporting is enabled in BL31, when a crash occurs, the crash
1445reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching
1446``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in
1447``cpu_ops`` is invoked, which then returns the CPU specific register values to
1448be reported and a pointer to the ASCII list of register names in a format
1449expected by the crash reporting framework.
1450
Paul Beesleyf8640672019-04-12 14:19:42 +01001451.. _firmware_design_cpu_errata_reporting:
1452
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001453CPU errata status reporting
1454~~~~~~~~~~~~~~~~~~~~~~~~~~~
1455
Dan Handley610e7e12018-03-01 18:44:00 +00001456Errata workarounds for CPUs supported in TF-A are applied during both cold and
1457warm boots, shortly after reset. Individual Errata workarounds are enabled as
1458build options. Some errata workarounds have potential run-time implications;
1459therefore some are enabled by default, others not. Platform ports shall
1460override build options to enable or disable errata as appropriate. The CPU
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001461drivers take care of applying errata workarounds that are enabled and applicable
Paul Beesleyf8640672019-04-12 14:19:42 +01001462to a given CPU. Refer to :ref:`arm_cpu_macros_errata_workarounds` for more
1463information.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001464
1465Functions in CPU drivers that apply errata workaround must follow the
1466conventions listed below.
1467
1468The errata workaround must be authored as two separate functions:
1469
1470- One that checks for errata. This function must determine whether that errata
1471 applies to the current CPU. Typically this involves matching the current
1472 CPUs revision and variant against a value that's known to be affected by the
1473 errata. If the function determines that the errata applies to this CPU, it
1474 must return ``ERRATA_APPLIES``; otherwise, it must return
1475 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and
1476 ``cpu_rev_var_ls`` functions may come in handy for this purpose.
1477
1478For an errata identified as ``E``, the check function must be named
1479``check_errata_E``.
1480
1481This function will be invoked at different times, both from assembly and from
1482C run time. Therefore it must follow AAPCS, and must not use stack.
1483
1484- Another one that applies the errata workaround. This function would call the
1485 check function described above, and applies errata workaround if required.
1486
1487CPU drivers that apply errata workaround can optionally implement an assembly
1488function that report the status of errata workarounds pertaining to that CPU.
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00001489For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001490macro, the errata reporting function, if it exists, must be named
1491``cpux_errata_report``. This function will always be called with MMU enabled; it
1492must follow AAPCS and may use stack.
1493
Dan Handley610e7e12018-03-01 18:44:00 +00001494In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the
1495runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata
1496status reporting function, if one exists, for that type of CPU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001497
1498To report the status of each errata workaround, the function shall use the
1499assembler macro ``report_errata``, passing it:
1500
1501- The build option that enables the errata;
1502
1503- The name of the CPU: this must be the same identifier that CPU driver
1504 registered itself with, using ``declare_cpu_ops``;
1505
1506- And the errata identifier: the identifier must match what's used in the
1507 errata's check function described above.
1508
1509The errata status reporting function will be called once per CPU type/errata
1510combination during the software's active life time.
1511
Dan Handley610e7e12018-03-01 18:44:00 +00001512It's expected that whenever an errata workaround is submitted to TF-A, the
1513errata reporting function is appropriately extended to report its status as
1514well.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001515
1516Reporting the status of errata workaround is for informational purpose only; it
1517has no functional significance.
1518
1519Memory layout of BL images
1520--------------------------
1521
1522Each bootloader image can be divided in 2 parts:
1523
1524- the static contents of the image. These are data actually stored in the
1525 binary on the disk. In the ELF terminology, they are called ``PROGBITS``
1526 sections;
1527
1528- the run-time contents of the image. These are data that don't occupy any
1529 space in the binary on the disk. The ELF binary just contains some
1530 metadata indicating where these data will be stored at run-time and the
1531 corresponding sections need to be allocated and initialized at run-time.
1532 In the ELF terminology, they are called ``NOBITS`` sections.
1533
1534All PROGBITS sections are grouped together at the beginning of the image,
Dan Handley610e7e12018-03-01 18:44:00 +00001535followed by all NOBITS sections. This is true for all TF-A images and it is
1536governed by the linker scripts. This ensures that the raw binary images are
1537as small as possible. If a NOBITS section was inserted in between PROGBITS
1538sections then the resulting binary file would contain zero bytes in place of
1539this NOBITS section, making the image unnecessarily bigger. Smaller images
1540allow faster loading from the FIP to the main memory.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001541
Samuel Holland31a14e12018-10-17 21:40:18 -05001542For BL31, a platform can specify an alternate location for NOBITS sections
1543(other than immediately following PROGBITS sections) by setting
1544``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and
1545``BL31_NOBITS_LIMIT``.
1546
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001547Linker scripts and symbols
1548~~~~~~~~~~~~~~~~~~~~~~~~~~
1549
1550Each bootloader stage image layout is described by its own linker script. The
1551linker scripts export some symbols into the program symbol table. Their values
Dan Handley610e7e12018-03-01 18:44:00 +00001552correspond to particular addresses. TF-A code can refer to these symbols to
1553figure out the image memory layout.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001554
Dan Handley610e7e12018-03-01 18:44:00 +00001555Linker symbols follow the following naming convention in TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001556
1557- ``__<SECTION>_START__``
1558
1559 Start address of a given section named ``<SECTION>``.
1560
1561- ``__<SECTION>_END__``
1562
1563 End address of a given section named ``<SECTION>``. If there is an alignment
1564 constraint on the section's end address then ``__<SECTION>_END__`` corresponds
1565 to the end address of the section's actual contents, rounded up to the right
1566 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the
1567 actual end address of the section's contents.
1568
1569- ``__<SECTION>_UNALIGNED_END__``
1570
1571 End address of a given section named ``<SECTION>`` without any padding or
1572 rounding up due to some alignment constraint.
1573
1574- ``__<SECTION>_SIZE__``
1575
1576 Size (in bytes) of a given section named ``<SECTION>``. If there is an
1577 alignment constraint on the section's end address then ``__<SECTION>_SIZE__``
1578 corresponds to the size of the section's actual contents, rounded up to the
1579 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__``
1580 to know the actual size of the section's contents.
1581
1582- ``__<SECTION>_UNALIGNED_SIZE__``
1583
1584 Size (in bytes) of a given section named ``<SECTION>`` without any padding or
1585 rounding up due to some alignment constraint. In other words,
1586 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``.
1587
Dan Handley610e7e12018-03-01 18:44:00 +00001588Some of the linker symbols are mandatory as TF-A code relies on them to be
1589defined. They are listed in the following subsections. Some of them must be
1590provided for each bootloader stage and some are specific to a given bootloader
1591stage.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001592
1593The linker scripts define some extra, optional symbols. They are not actually
1594used by any code but they help in understanding the bootloader images' memory
1595layout as they are easy to spot in the link map files.
1596
1597Common linker symbols
1598^^^^^^^^^^^^^^^^^^^^^
1599
1600All BL images share the following requirements:
1601
1602- The BSS section must be zero-initialised before executing any C code.
1603- The coherent memory section (if enabled) must be zero-initialised as well.
1604- The MMU setup code needs to know the extents of the coherent and read-only
1605 memory regions to set the right memory attributes. When
1606 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the
1607 read-only memory region is divided between code and data.
1608
1609The following linker symbols are defined for this purpose:
1610
1611- ``__BSS_START__``
1612- ``__BSS_SIZE__``
1613- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary.
1614- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary.
1615- ``__COHERENT_RAM_UNALIGNED_SIZE__``
1616- ``__RO_START__``
1617- ``__RO_END__``
1618- ``__TEXT_START__``
1619- ``__TEXT_END__``
1620- ``__RODATA_START__``
1621- ``__RODATA_END__``
1622
1623BL1's linker symbols
1624^^^^^^^^^^^^^^^^^^^^
1625
1626BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and
1627it is entirely executed in place but it needs some read-write memory for its
1628mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be
1629relocated from ROM to RAM before executing any C code.
1630
1631The following additional linker symbols are defined for BL1:
1632
1633- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code
1634 and ``.data`` section in ROM.
1635- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be
1636 aligned on a 16-byte boundary.
1637- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be
1638 copied over. Must be aligned on a 16-byte boundary.
1639- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM).
1640- ``__BL1_RAM_START__`` Start address of BL1 read-write data.
1641- ``__BL1_RAM_END__`` End address of BL1 read-write data.
1642
1643How to choose the right base addresses for each bootloader stage image
1644~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1645
Dan Handley610e7e12018-03-01 18:44:00 +00001646There is currently no support for dynamic image loading in TF-A. This means
1647that all bootloader images need to be linked against their ultimate runtime
1648locations and the base addresses of each image must be chosen carefully such
1649that images don't overlap each other in an undesired way. As the code grows,
1650the base addresses might need adjustments to cope with the new memory layout.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001651
1652The memory layout is completely specific to the platform and so there is no
1653general recipe for choosing the right base addresses for each bootloader image.
1654However, there are tools to aid in understanding the memory layout. These are
1655the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>``
1656being the stage bootloader. They provide a detailed view of the memory usage of
1657each image. Among other useful information, they provide the end address of
1658each image.
1659
1660- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address.
1661- ``bl2.map`` link map file provides ``__BL2_END__`` address.
1662- ``bl31.map`` link map file provides ``__BL31_END__`` address.
1663- ``bl32.map`` link map file provides ``__BL32_END__`` address.
1664
1665For each bootloader image, the platform code must provide its start address
1666as well as a limit address that it must not overstep. The latter is used in the
1667linker scripts to check that the image doesn't grow past that address. If that
1668happens, the linker will issue a message similar to the following:
1669
1670::
1671
1672 aarch64-none-elf-ld: BLx has exceeded its limit.
1673
1674Additionally, if the platform memory layout implies some image overlaying like
1675on FVP, BL31 and TSP need to know the limit address that their PROGBITS
1676sections must not overstep. The platform code must provide those.
1677
Soby Mathew97b1bff2018-09-27 16:46:41 +01001678TF-A does not provide any mechanism to verify at boot time that the memory
1679to load a new image is free to prevent overwriting a previously loaded image.
1680The platform must specify the memory available in the system for all the
1681relevant BL images to be loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001682
1683For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will
1684return the region defined by the platform where BL1 intends to load BL2. The
1685``load_image()`` function performs bounds check for the image size based on the
1686base and maximum image size provided by the platforms. Platforms must take
1687this behaviour into account when defining the base/size for each of the images.
1688
Dan Handley610e7e12018-03-01 18:44:00 +00001689Memory layout on Arm development platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001690^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1691
Dan Handley610e7e12018-03-01 18:44:00 +00001692The following list describes the memory layout on the Arm development platforms:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001693
1694- A 4KB page of shared memory is used for communication between Trusted
1695 Firmware and the platform's power controller. This is located at the base of
1696 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader
1697 images is reduced by the size of the shared memory.
1698
1699 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno,
1700 this is also used for the MHU payload when passing messages to and from the
1701 SCP.
1702
Soby Mathew492e2452018-06-06 16:03:10 +01001703- Another 4 KB page is reserved for passing memory layout between BL1 and BL2
1704 and also the dynamic firmware configurations.
1705
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001706- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On
1707 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write
1708 data are relocated to the top of Trusted SRAM at runtime.
1709
Soby Mathew492e2452018-06-06 16:03:10 +01001710- BL2 is loaded below BL1 RW
1711
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001712- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN),
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001713 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will
Soby Mathew492e2452018-06-06 16:03:10 +01001714 overwrite BL1 R/W data and BL2. This implies that BL1 global variables
1715 remain valid only until execution reaches the EL3 Runtime Software entry
1716 point during a cold boot.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001717
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001718- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory
Paul Beesleyf2ec7142019-10-04 16:17:46 +00001719 region and transferred to the SCP before being overwritten by EL3 Runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001720 Software.
1721
1722- BL32 (for AArch64) can be loaded in one of the following locations:
1723
1724 - Trusted SRAM
1725 - Trusted DRAM (FVP only)
1726 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone
1727 controller)
1728
Soby Mathew492e2452018-06-06 16:03:10 +01001729 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below
1730 BL31.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001731
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001732The location of the BL32 image will result in different memory maps. This is
1733illustrated for both FVP and Juno in the following diagrams, using the TSP as
1734an example.
1735
Paul Beesleyba3ed402019-03-13 16:20:44 +00001736.. note::
1737 Loading the BL32 image in TZC secured DRAM doesn't change the memory
1738 layout of the other images in Trusted SRAM.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001739
Sathees Balya90950092018-11-15 14:22:30 +00001740CONFIG section in memory layouts shown below contains:
1741
1742::
1743
1744 +--------------------+
1745 |bl2_mem_params_descs|
1746 |--------------------|
1747 | fw_configs |
1748 +--------------------+
1749
1750``bl2_mem_params_descs`` contains parameters passed from BL2 to next the
1751BL image during boot.
1752
Manish V Badarkheece96fd2020-06-13 09:42:28 +01001753``fw_configs`` includes soc_fw_config, tos_fw_config, tb_fw_config and fw_config.
Sathees Balya90950092018-11-15 14:22:30 +00001754
Soby Mathew492e2452018-06-06 16:03:10 +01001755**FVP with TSP in Trusted SRAM with firmware configs :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001756(These diagrams only cover the AArch64 case)
1757
1758::
1759
Soby Mathew492e2452018-06-06 16:03:10 +01001760 DRAM
1761 0xffffffff +----------+
Manish V Badarkhe638ac182023-03-07 10:21:30 +00001762 | EL3 TZC |
1763 0xffe00000 |----------| (secure)
1764 | AP TZC |
1765 0xff000000 +----------+
Soby Mathew492e2452018-06-06 16:03:10 +01001766 : :
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001767 0x82100000 |----------|
Soby Mathew492e2452018-06-06 16:03:10 +01001768 |HW_CONFIG |
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001769 0x82000000 |----------| (non-secure)
Soby Mathew492e2452018-06-06 16:03:10 +01001770 | |
1771 0x80000000 +----------+
1772
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001773 Trusted DRAM
1774 0x08000000 +----------+
1775 |HW_CONFIG |
1776 0x07f00000 |----------|
1777 : :
1778 | |
1779 0x06000000 +----------+
1780
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001781 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001782 0x04040000 +----------+ loaded by BL2 +----------------+
1783 | BL1 (rw) | <<<<<<<<<<<<< | |
1784 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1785 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001786 |----------| <<<<<<<<<<<<< |----------------|
1787 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001788 | | <<<<<<<<<<<<< |----------------|
1789 | | <<<<<<<<<<<<< | BL32 |
Manish V Badarkheece96fd2020-06-13 09:42:28 +01001790 0x04003000 +----------+ +----------------+
Sathees Balya90950092018-11-15 14:22:30 +00001791 | CONFIG |
Soby Mathew492e2452018-06-06 16:03:10 +01001792 0x04001000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001793 | Shared |
1794 0x04000000 +----------+
1795
1796 Trusted ROM
1797 0x04000000 +----------+
1798 | BL1 (ro) |
1799 0x00000000 +----------+
1800
Soby Mathew492e2452018-06-06 16:03:10 +01001801**FVP with TSP in Trusted DRAM with firmware configs (default option):**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001802
1803::
1804
Soby Mathewb1bf0442018-02-16 14:52:52 +00001805 DRAM
1806 0xffffffff +--------------+
Manish V Badarkhe638ac182023-03-07 10:21:30 +00001807 | EL3 TZC |
1808 0xffe00000 |--------------| (secure)
1809 | AP TZC |
1810 0xff000000 +--------------+
Soby Mathewb1bf0442018-02-16 14:52:52 +00001811 : :
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001812 0x82100000 |--------------|
Soby Mathewb1bf0442018-02-16 14:52:52 +00001813 | HW_CONFIG |
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001814 0x82000000 |--------------| (non-secure)
Soby Mathewb1bf0442018-02-16 14:52:52 +00001815 | |
1816 0x80000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001817
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001818 Trusted DRAM
Soby Mathewb1bf0442018-02-16 14:52:52 +00001819 0x08000000 +--------------+
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001820 | HW_CONFIG |
1821 0x07f00000 |--------------|
1822 : :
1823 | BL32 |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001824 0x06000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001825
Soby Mathewb1bf0442018-02-16 14:52:52 +00001826 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001827 0x04040000 +--------------+ loaded by BL2 +----------------+
1828 | BL1 (rw) | <<<<<<<<<<<<< | |
1829 |--------------| <<<<<<<<<<<<< | BL31 NOBITS |
1830 | BL2 | <<<<<<<<<<<<< | |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001831 |--------------| <<<<<<<<<<<<< |----------------|
1832 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001833 | | +----------------+
Manish V Badarkheece96fd2020-06-13 09:42:28 +01001834 0x04003000 +--------------+
Sathees Balya90950092018-11-15 14:22:30 +00001835 | CONFIG |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001836 0x04001000 +--------------+
1837 | Shared |
1838 0x04000000 +--------------+
1839
1840 Trusted ROM
1841 0x04000000 +--------------+
1842 | BL1 (ro) |
1843 0x00000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001844
Soby Mathew492e2452018-06-06 16:03:10 +01001845**FVP with TSP in TZC-Secured DRAM with firmware configs :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001846
1847::
1848
1849 DRAM
1850 0xffffffff +----------+
Manish V Badarkhe638ac182023-03-07 10:21:30 +00001851 | EL3 TZC |
1852 0xffe00000 |----------| (secure)
1853 | AP TZC |
1854 | (BL32) |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001855 0xff000000 +----------+
1856 | |
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001857 0x82100000 |----------|
Soby Mathew492e2452018-06-06 16:03:10 +01001858 |HW_CONFIG |
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001859 0x82000000 |----------| (non-secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001860 | |
1861 0x80000000 +----------+
1862
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001863 Trusted DRAM
1864 0x08000000 +----------+
1865 |HW_CONFIG |
1866 0x7f000000 |----------|
1867 : :
1868 | |
1869 0x06000000 +----------+
1870
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001871 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001872 0x04040000 +----------+ loaded by BL2 +----------------+
1873 | BL1 (rw) | <<<<<<<<<<<<< | |
1874 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1875 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001876 |----------| <<<<<<<<<<<<< |----------------|
1877 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001878 | | +----------------+
Manish V Badarkheece96fd2020-06-13 09:42:28 +01001879 0x04003000 +----------+
Sathees Balya90950092018-11-15 14:22:30 +00001880 | CONFIG |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001881 0x04001000 +----------+
1882 | Shared |
1883 0x04000000 +----------+
1884
1885 Trusted ROM
1886 0x04000000 +----------+
1887 | BL1 (ro) |
1888 0x00000000 +----------+
1889
Soby Mathew492e2452018-06-06 16:03:10 +01001890**Juno with BL32 in Trusted SRAM :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001891
1892::
1893
Manish V Badarkhe638ac182023-03-07 10:21:30 +00001894 DRAM
1895 0xFFFFFFFF +----------+
1896 | SCP TZC |
1897 0xFFE00000 |----------|
1898 | EL3 TZC |
1899 0xFFC00000 |----------| (secure)
1900 | AP TZC |
1901 0xFF000000 +----------+
1902 | |
1903 : : (non-secure)
1904 | |
1905 0x80000000 +----------+
1906
1907
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001908 Flash0
1909 0x0C000000 +----------+
1910 : :
1911 0x0BED0000 |----------|
1912 | BL1 (ro) |
1913 0x0BEC0000 |----------|
1914 : :
1915 0x08000000 +----------+ BL31 is loaded
1916 after SCP_BL2 has
1917 Trusted SRAM been sent to SCP
Soby Mathew492e2452018-06-06 16:03:10 +01001918 0x04040000 +----------+ loaded by BL2 +----------------+
1919 | BL1 (rw) | <<<<<<<<<<<<< | |
1920 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1921 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001922 |----------| <<<<<<<<<<<<< |----------------|
1923 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Chris Kayf8fa4652020-03-12 13:50:26 +00001924 | | <<<<<<<<<<<<< |----------------|
Soby Mathew492e2452018-06-06 16:03:10 +01001925 | | <<<<<<<<<<<<< | BL32 |
1926 | | +----------------+
1927 | |
1928 0x04001000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001929 | MHU |
1930 0x04000000 +----------+
1931
Soby Mathew492e2452018-06-06 16:03:10 +01001932**Juno with BL32 in TZC-secured DRAM :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001933
1934::
1935
1936 DRAM
Manish V Badarkhe638ac182023-03-07 10:21:30 +00001937 0xFFFFFFFF +----------+
1938 | SCP TZC |
1939 0xFFE00000 |----------|
1940 | EL3 TZC |
1941 0xFFC00000 |----------| (secure)
1942 | AP TZC |
1943 | (BL32) |
1944 0xFF000000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001945 | |
1946 : : (non-secure)
1947 | |
1948 0x80000000 +----------+
1949
1950 Flash0
1951 0x0C000000 +----------+
1952 : :
1953 0x0BED0000 |----------|
1954 | BL1 (ro) |
1955 0x0BEC0000 |----------|
1956 : :
1957 0x08000000 +----------+ BL31 is loaded
1958 after SCP_BL2 has
1959 Trusted SRAM been sent to SCP
Soby Mathew492e2452018-06-06 16:03:10 +01001960 0x04040000 +----------+ loaded by BL2 +----------------+
1961 | BL1 (rw) | <<<<<<<<<<<<< | |
1962 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1963 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001964 |----------| <<<<<<<<<<<<< |----------------|
1965 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Chris Kayf8fa4652020-03-12 13:50:26 +00001966 | | +----------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001967 0x04001000 +----------+
1968 | MHU |
1969 0x04000000 +----------+
1970
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001971.. _firmware_design_fip:
Sathees Balya17d8eed2019-01-30 15:56:44 +00001972
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001973Firmware Image Package (FIP)
1974----------------------------
1975
1976Using a Firmware Image Package (FIP) allows for packing bootloader images (and
Dan Handley610e7e12018-03-01 18:44:00 +00001977potentially other payloads) into a single archive that can be loaded by TF-A
1978from non-volatile platform storage. A driver to load images from a FIP has
1979been added to the storage layer and allows a package to be read from supported
1980platform storage. A tool to create Firmware Image Packages is also provided
1981and described below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001982
1983Firmware Image Package layout
1984~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1985
1986The FIP layout consists of a table of contents (ToC) followed by payload data.
1987The ToC itself has a header followed by one or more table entries. The ToC is
Jett Zhou75566102017-11-24 16:03:58 +08001988terminated by an end marker entry, and since the size of the ToC is 0 bytes,
1989the offset equals the total size of the FIP file. All ToC entries describe some
1990payload data that has been appended to the end of the binary package. With the
1991information provided in the ToC entry the corresponding payload data can be
1992retrieved.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001993
1994::
1995
1996 ------------------
1997 | ToC Header |
1998 |----------------|
1999 | ToC Entry 0 |
2000 |----------------|
2001 | ToC Entry 1 |
2002 |----------------|
2003 | ToC End Marker |
2004 |----------------|
2005 | |
2006 | Data 0 |
2007 | |
2008 |----------------|
2009 | |
2010 | Data 1 |
2011 | |
2012 ------------------
2013
2014The ToC header and entry formats are described in the header file
2015``include/tools_share/firmware_image_package.h``. This file is used by both the
Dan Handley610e7e12018-03-01 18:44:00 +00002016tool and TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002017
2018The ToC header has the following fields:
2019
2020::
2021
2022 `name`: The name of the ToC. This is currently used to validate the header.
2023 `serial_number`: A non-zero number provided by the creation tool
2024 `flags`: Flags associated with this data.
2025 Bits 0-31: Reserved
2026 Bits 32-47: Platform defined
2027 Bits 48-63: Reserved
2028
2029A ToC entry has the following fields:
2030
2031::
2032
2033 `uuid`: All files are referred to by a pre-defined Universally Unique
2034 IDentifier [UUID] . The UUIDs are defined in
2035 `include/tools_share/firmware_image_package.h`. The platform translates
2036 the requested image name into the corresponding UUID when accessing the
2037 package.
2038 `offset_address`: The offset address at which the corresponding payload data
2039 can be found. The offset is calculated from the ToC base address.
2040 `size`: The size of the corresponding payload data in bytes.
Etienne Carriere7421bf12017-08-23 15:43:33 +02002041 `flags`: Flags associated with this entry. None are yet defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002042
2043Firmware Image Package creation tool
2044~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2045
Dan Handley610e7e12018-03-01 18:44:00 +00002046The FIP creation tool can be used to pack specified images into a binary
2047package that can be loaded by TF-A from platform storage. The tool currently
2048only supports packing bootloader images. Additional image definitions can be
2049added to the tool as required.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002050
2051The tool can be found in ``tools/fiptool``.
2052
2053Loading from a Firmware Image Package (FIP)
2054~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2055
2056The Firmware Image Package (FIP) driver can load images from a binary package on
Dan Handley610e7e12018-03-01 18:44:00 +00002057non-volatile platform storage. For the Arm development platforms, this is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002058currently NOR FLASH.
2059
2060Bootloader images are loaded according to the platform policy as specified by
Dan Handley610e7e12018-03-01 18:44:00 +00002061the function ``plat_get_image_source()``. For the Arm development platforms, this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002062means the platform will attempt to load images from a Firmware Image Package
2063located at the start of NOR FLASH0.
2064
Dan Handley610e7e12018-03-01 18:44:00 +00002065The Arm development platforms' policy is to only allow loading of a known set of
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002066images. The platform policy can be modified to allow additional images.
2067
Dan Handley610e7e12018-03-01 18:44:00 +00002068Use of coherent memory in TF-A
2069------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002070
2071There might be loss of coherency when physical memory with mismatched
2072shareability, cacheability and memory attributes is accessed by multiple CPUs
Dan Handley610e7e12018-03-01 18:44:00 +00002073(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs
2074in TF-A during power up/down sequences when coherency, MMU and caches are
2075turned on/off incrementally.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002076
Dan Handley610e7e12018-03-01 18:44:00 +00002077TF-A defines coherent memory as a region of memory with Device nGnRE attributes
2078in the translation tables. The translation granule size in TF-A is 4KB. This
2079is the smallest possible size of the coherent memory region.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002080
2081By default, all data structures which are susceptible to accesses with
2082mismatched attributes from various CPUs are allocated in a coherent memory
Paul Beesleyf8640672019-04-12 14:19:42 +01002083region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory
2084region accesses are Outer Shareable, non-cacheable and they can be accessed with
2085the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of
2086at least an extra page of memory, TF-A is able to work around coherency issues
2087due to mismatched memory attributes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002088
2089The alternative to the above approach is to allocate the susceptible data
2090structures in Normal WriteBack WriteAllocate Inner shareable memory. This
2091approach requires the data structures to be designed so that it is possible to
2092work around the issue of mismatched memory attributes by performing software
2093cache maintenance on them.
2094
Dan Handley610e7e12018-03-01 18:44:00 +00002095Disabling the use of coherent memory in TF-A
2096~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002097
2098It might be desirable to avoid the cost of allocating coherent memory on
Dan Handley610e7e12018-03-01 18:44:00 +00002099platforms which are memory constrained. TF-A enables inclusion of coherent
2100memory in firmware images through the build flag ``USE_COHERENT_MEM``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002101This flag is enabled by default. It can be disabled to choose the second
2102approach described above.
2103
2104The below sections analyze the data structures allocated in the coherent memory
2105region and the changes required to allocate them in normal memory.
2106
2107Coherent memory usage in PSCI implementation
2108~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2109
2110The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain
2111tree information for state management of power domains. By default, this data
Dan Handley610e7e12018-03-01 18:44:00 +00002112structure is allocated in the coherent memory region in TF-A because it can be
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002113accessed by multiple CPUs, either with caches enabled or disabled.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002114
2115.. code:: c
2116
2117 typedef struct non_cpu_pwr_domain_node {
2118 /*
2119 * Index of the first CPU power domain node level 0 which has this node
2120 * as its parent.
2121 */
2122 unsigned int cpu_start_idx;
2123
2124 /*
2125 * Number of CPU power domains which are siblings of the domain indexed
2126 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
2127 * -> cpu_start_idx + ncpus' have this node as their parent.
2128 */
2129 unsigned int ncpus;
2130
2131 /*
2132 * Index of the parent power domain node.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002133 */
2134 unsigned int parent_node;
2135
2136 plat_local_state_t local_state;
2137
2138 unsigned char level;
2139
2140 /* For indexing the psci_lock array*/
2141 unsigned char lock_index;
2142 } non_cpu_pd_node_t;
2143
2144In order to move this data structure to normal memory, the use of each of its
2145fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node``
2146``level`` and ``lock_index`` are only written once during cold boot. Hence removing
2147them from coherent memory involves only doing a clean and invalidate of the
2148cache lines after these fields are written.
2149
2150The field ``local_state`` can be concurrently accessed by multiple CPUs in
2151different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002152mutual exclusion to this field and a clean and invalidate is needed after it
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002153is written.
2154
2155Bakery lock data
2156~~~~~~~~~~~~~~~~
2157
2158The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory
2159and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is
2160defined as follows:
2161
2162.. code:: c
2163
2164 typedef struct bakery_lock {
2165 /*
2166 * The lock_data is a bit-field of 2 members:
2167 * Bit[0] : choosing. This field is set when the CPU is
2168 * choosing its bakery number.
2169 * Bits[1 - 15] : number. This is the bakery number allocated.
2170 */
2171 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS];
2172 } bakery_lock_t;
2173
2174It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU
2175fields can be read by all CPUs but only written to by the owning CPU.
2176
2177Depending upon the data cache line size, the per-CPU fields of the
2178``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line.
2179These per-CPU fields can be read and written during lock contention by multiple
2180CPUs with mismatched memory attributes. Since these fields are a part of the
2181lock implementation, they do not have access to any other locking primitive to
2182safeguard against the resulting coherency issues. As a result, simple software
2183cache maintenance is not enough to allocate them in coherent memory. Consider
2184the following example.
2185
2186CPU0 updates its per-CPU field with data cache enabled. This write updates a
2187local cache line which contains a copy of the fields for other CPUs as well. Now
2188CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache
2189disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of
2190its field in any other cache line in the system. This operation will invalidate
2191the update made by CPU0 as well.
2192
2193To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure
2194has been redesigned. The changes utilise the characteristic of Lamport's Bakery
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002195algorithm mentioned earlier. The bakery_lock structure only allocates the memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002196for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks
Chris Kay33bfc5e2023-02-14 11:30:04 +00002197needed for a CPU into a section ``.bakery_lock``. The linker allocates the memory
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002198for other cores by using the total size allocated for the bakery_lock section
2199and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002200perform software cache maintenance on the lock data structure without running
2201into coherency issues associated with mismatched attributes.
2202
2203The bakery lock data structure ``bakery_info_t`` is defined for use when
2204``USE_COHERENT_MEM`` is disabled as follows:
2205
2206.. code:: c
2207
2208 typedef struct bakery_info {
2209 /*
2210 * The lock_data is a bit-field of 2 members:
2211 * Bit[0] : choosing. This field is set when the CPU is
2212 * choosing its bakery number.
2213 * Bits[1 - 15] : number. This is the bakery number allocated.
2214 */
2215 volatile uint16_t lock_data;
2216 } bakery_info_t;
2217
2218The ``bakery_info_t`` represents a single per-CPU field of one lock and
2219the combination of corresponding ``bakery_info_t`` structures for all CPUs in the
2220system represents the complete bakery lock. The view in memory for a system
2221with n bakery locks are:
2222
2223::
2224
Chris Kay33bfc5e2023-02-14 11:30:04 +00002225 .bakery_lock section start
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002226 |----------------|
2227 | `bakery_info_t`| <-- Lock_0 per-CPU field
2228 | Lock_0 | for CPU0
2229 |----------------|
2230 | `bakery_info_t`| <-- Lock_1 per-CPU field
2231 | Lock_1 | for CPU0
2232 |----------------|
2233 | .... |
2234 |----------------|
2235 | `bakery_info_t`| <-- Lock_N per-CPU field
2236 | Lock_N | for CPU0
2237 ------------------
2238 | XXXXX |
2239 | Padding to |
2240 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate
2241 | Granule | continuous memory for remaining CPUs.
2242 ------------------
2243 | `bakery_info_t`| <-- Lock_0 per-CPU field
2244 | Lock_0 | for CPU1
2245 |----------------|
2246 | `bakery_info_t`| <-- Lock_1 per-CPU field
2247 | Lock_1 | for CPU1
2248 |----------------|
2249 | .... |
2250 |----------------|
2251 | `bakery_info_t`| <-- Lock_N per-CPU field
2252 | Lock_N | for CPU1
2253 ------------------
2254 | XXXXX |
2255 | Padding to |
2256 | next Cache WB |
2257 | Granule |
2258 ------------------
2259
2260Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002261operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
Chris Kay33bfc5e2023-02-14 11:30:04 +00002262``.bakery_lock`` section need to be fetched and appropriate cache operations need
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002263to be performed for each access.
2264
Dan Handley610e7e12018-03-01 18:44:00 +00002265On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002266driver (``arm_lock``).
2267
2268Non Functional Impact of removing coherent memory
2269~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2270
2271Removal of the coherent memory region leads to the additional software overhead
2272of performing cache maintenance for the affected data structures. However, since
2273the memory where the data structures are allocated is cacheable, the overhead is
2274mostly mitigated by an increase in performance.
2275
2276There is however a performance impact for bakery locks, due to:
2277
2278- Additional cache maintenance operations, and
2279- Multiple cache line reads for each lock operation, since the bakery locks
2280 for each CPU are distributed across different cache lines.
2281
2282The implementation has been optimized to minimize this additional overhead.
2283Measurements indicate that when bakery locks are allocated in Normal memory, the
2284minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas
2285in Device memory the same is 2 micro seconds. The measurements were done on the
Dan Handley610e7e12018-03-01 18:44:00 +00002286Juno Arm development platform.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002287
2288As mentioned earlier, almost a page of memory can be saved by disabling
2289``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide
2290whether coherent memory should be used. If a platform disables
2291``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can
2292optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the
Paul Beesleyf8640672019-04-12 14:19:42 +01002293:ref:`Porting Guide`). Refer to the reference platform code for examples.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002294
2295Isolating code and read-only data on separate memory pages
2296----------------------------------------------------------
2297
Dan Handley610e7e12018-03-01 18:44:00 +00002298In the Armv8-A VMSA, translation table entries include fields that define the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002299properties of the target memory region, such as its access permissions. The
2300smallest unit of memory that can be addressed by a translation table entry is
2301a memory page. Therefore, if software needs to set different permissions on two
2302memory regions then it needs to map them using different memory pages.
2303
2304The default memory layout for each BL image is as follows:
2305
2306::
2307
2308 | ... |
2309 +-------------------+
2310 | Read-write data |
2311 +-------------------+ Page boundary
2312 | <Padding> |
2313 +-------------------+
2314 | Exception vectors |
2315 +-------------------+ 2 KB boundary
2316 | <Padding> |
2317 +-------------------+
2318 | Read-only data |
2319 +-------------------+
2320 | Code |
2321 +-------------------+ BLx_BASE
2322
Paul Beesleyba3ed402019-03-13 16:20:44 +00002323.. note::
2324 The 2KB alignment for the exception vectors is an architectural
2325 requirement.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002326
2327The read-write data start on a new memory page so that they can be mapped with
2328read-write permissions, whereas the code and read-only data below are configured
2329as read-only.
2330
2331However, the read-only data are not aligned on a page boundary. They are
2332contiguous to the code. Therefore, the end of the code section and the beginning
2333of the read-only data one might share a memory page. This forces both to be
2334mapped with the same memory attributes. As the code needs to be executable, this
2335means that the read-only data stored on the same memory page as the code are
2336executable as well. This could potentially be exploited as part of a security
2337attack.
2338
2339TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and
2340read-only data on separate memory pages. This in turn allows independent control
2341of the access permissions for the code and read-only data. In this case,
2342platform code gets a finer-grained view of the image layout and can
2343appropriately map the code region as executable and the read-only data as
2344execute-never.
2345
2346This has an impact on memory footprint, as padding bytes need to be introduced
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002347between the code and read-only data to ensure the segregation of the two. To
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002348limit the memory cost, this flag also changes the memory layout such that the
2349code and exception vectors are now contiguous, like so:
2350
2351::
2352
2353 | ... |
2354 +-------------------+
2355 | Read-write data |
2356 +-------------------+ Page boundary
2357 | <Padding> |
2358 +-------------------+
2359 | Read-only data |
2360 +-------------------+ Page boundary
2361 | <Padding> |
2362 +-------------------+
2363 | Exception vectors |
2364 +-------------------+ 2 KB boundary
2365 | <Padding> |
2366 +-------------------+
2367 | Code |
2368 +-------------------+ BLx_BASE
2369
2370With this more condensed memory layout, the separation of read-only data will
2371add zero or one page to the memory footprint of each BL image. Each platform
2372should consider the trade-off between memory footprint and security.
2373
Dan Handley610e7e12018-03-01 18:44:00 +00002374This build flag is disabled by default, minimising memory footprint. On Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002375platforms, it is enabled.
2376
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002377Publish and Subscribe Framework
2378-------------------------------
2379
2380The Publish and Subscribe Framework allows EL3 components to define and publish
2381events, to which other EL3 components can subscribe.
2382
2383The following macros are provided by the framework:
2384
2385- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument,
2386 the event name, which must be a valid C identifier. All calls to
2387 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file
2388 ``pubsub_events.h``.
2389
2390- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating
2391 subscribed handlers and calling them in turn. The handlers will be passed the
2392 parameter ``arg``. The expected use-case is to broadcast an event.
2393
2394- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value
2395 ``NULL`` is passed to subscribed handlers.
2396
2397- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to
2398 subscribe to ``event``. The handler will be executed whenever the ``event``
2399 is published.
2400
2401- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers
2402 subscribed for ``event``. ``subscriber`` must be a local variable of type
2403 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during
2404 iteration. This macro can be used for those patterns that none of the
2405 ``PUBLISH_EVENT_*()`` macros cover.
2406
2407Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will
2408result in build error. Subscribing to an undefined event however won't.
2409
2410Subscribed handlers must be of type ``pubsub_cb_t``, with following function
2411signature:
2412
Paul Beesley493e3492019-03-13 15:11:04 +00002413.. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002414
2415 typedef void* (*pubsub_cb_t)(const void *arg);
2416
2417There may be arbitrary number of handlers registered to the same event. The
2418order in which subscribed handlers are notified when that event is published is
2419not defined. Subscribed handlers may be executed in any order; handlers should
2420not assume any relative ordering amongst them.
2421
2422Publishing an event on a PE will result in subscribed handlers executing on that
2423PE only; it won't cause handlers to execute on a different PE.
2424
2425Note that publishing an event on a PE blocks until all the subscribed handlers
2426finish executing on the PE.
2427
Dan Handley610e7e12018-03-01 18:44:00 +00002428TF-A generic code publishes and subscribes to some events within. Platform
2429ports are discouraged from subscribing to them. These events may be withdrawn,
2430renamed, or have their semantics altered in the future. Platforms may however
2431register, publish, and subscribe to platform-specific events.
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01002432
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002433Publish and Subscribe Example
2434~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2435
2436A publisher that wants to publish event ``foo`` would:
2437
2438- Define the event ``foo`` in the ``pubsub_events.h``.
2439
Paul Beesley493e3492019-03-13 15:11:04 +00002440 .. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002441
2442 REGISTER_PUBSUB_EVENT(foo);
2443
2444- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to
2445 publish the event at the appropriate path and time of execution.
2446
2447A subscriber that wants to subscribe to event ``foo`` published above would
2448implement:
2449
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002450.. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002451
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002452 void *foo_handler(const void *arg)
2453 {
2454 void *result;
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002455
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002456 /* Do handling ... */
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002457
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002458 return result;
2459 }
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002460
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002461 SUBSCRIBE_TO_EVENT(foo, foo_handler);
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002462
Daniel Boulby468f0d72018-09-18 11:45:51 +01002463
2464Reclaiming the BL31 initialization code
2465~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2466
2467A significant amount of the code used for the initialization of BL31 is never
2468needed again after boot time. In order to reduce the runtime memory
2469footprint, the memory used for this code can be reclaimed after initialization
2470has finished and be used for runtime data.
2471
2472The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code
2473with a ``.text.init.*`` attribute which can be filtered and placed suitably
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002474within the BL image for later reclamation by the platform. The platform can
2475specify the filter and the memory region for this init section in BL31 via the
Daniel Boulby468f0d72018-09-18 11:45:51 +01002476plat.ld.S linker script. For example, on the FVP, this section is placed
2477overlapping the secondary CPU stacks so that after the cold boot is done, this
2478memory can be reclaimed for the stacks. The init memory section is initially
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002479mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has
Daniel Boulby468f0d72018-09-18 11:45:51 +01002480completed, the FVP changes the attributes of this section to ``RW``,
2481``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes
2482are changed within the ``bl31_plat_runtime_setup`` platform hook. The init
2483section section can be reclaimed for any data which is accessed after cold
2484boot initialization and it is upto the platform to make the decision.
2485
Paul Beesleyf8640672019-04-12 14:19:42 +01002486.. _firmware_design_pmf:
2487
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002488Performance Measurement Framework
2489---------------------------------
2490
2491The Performance Measurement Framework (PMF) facilitates collection of
Dan Handley610e7e12018-03-01 18:44:00 +00002492timestamps by registered services and provides interfaces to retrieve them
2493from within TF-A. A platform can choose to expose appropriate SMCs to
2494retrieve these collected timestamps.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002495
2496By default, the global physical counter is used for the timestamp
2497value and is read via ``CNTPCT_EL0``. The framework allows to retrieve
2498timestamps captured by other CPUs.
2499
2500Timestamp identifier format
2501~~~~~~~~~~~~~~~~~~~~~~~~~~~
2502
2503A PMF timestamp is uniquely identified across the system via the
2504timestamp ID or ``tid``. The ``tid`` is composed as follows:
2505
2506::
2507
2508 Bits 0-7: The local timestamp identifier.
2509 Bits 8-9: Reserved.
2510 Bits 10-15: The service identifier.
2511 Bits 16-31: Reserved.
2512
2513#. The service identifier. Each PMF service is identified by a
2514 service name and a service identifier. Both the service name and
2515 identifier are unique within the system as a whole.
2516
2517#. The local timestamp identifier. This identifier is unique within a given
2518 service.
2519
2520Registering a PMF service
2521~~~~~~~~~~~~~~~~~~~~~~~~~
2522
2523To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h``
2524is used. The arguments required are the service name, the service ID,
2525the total number of local timestamps to be captured and a set of flags.
2526
2527The ``flags`` field can be specified as a bitwise-OR of the following values:
2528
2529::
2530
2531 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval.
2532 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console.
2533
2534The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured
2535timestamps in a PMF specific linker section at build time.
2536Additionally, it defines necessary functions to capture and
2537retrieve a particular timestamp for the given service at runtime.
2538
Dan Handley610e7e12018-03-01 18:44:00 +00002539The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps
2540from within TF-A. In order to retrieve timestamps from outside of TF-A, the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002541``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro
2542accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()``
2543macro but additionally supports retrieving timestamps using SMCs.
2544
2545Capturing a timestamp
2546~~~~~~~~~~~~~~~~~~~~~
2547
2548PMF timestamps are stored in a per-service timestamp region. On a
2549system with multiple CPUs, each timestamp is captured and stored
2550in a per-CPU cache line aligned memory region.
2551
2552Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be
2553used to capture a timestamp at the location where it is used. The macro
2554takes the service name, a local timestamp identifier and a flag as arguments.
2555
2556The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which
2557instructs PMF to do cache maintenance following the capture. Cache
2558maintenance is required if any of the service's timestamps are captured
2559with data cache disabled.
2560
2561To capture a timestamp in assembly code, the caller should use
2562``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to
2563calculate the address of where the timestamp would be stored. The
2564caller should then read ``CNTPCT_EL0`` register to obtain the timestamp
2565and store it at the determined address for later retrieval.
2566
2567Retrieving a timestamp
2568~~~~~~~~~~~~~~~~~~~~~~
2569
Dan Handley610e7e12018-03-01 18:44:00 +00002570From within TF-A, timestamps for individual CPUs can be retrieved using either
2571``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros.
2572These macros accept the CPU's MPIDR value, or its ordinal position
2573respectively.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002574
Dan Handley610e7e12018-03-01 18:44:00 +00002575From outside TF-A, timestamps for individual CPUs can be retrieved by calling
2576into ``pmf_smc_handler()``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002577
Paul Beesley493e3492019-03-13 15:11:04 +00002578::
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002579
2580 Interface : pmf_smc_handler()
2581 Argument : unsigned int smc_fid, u_register_t x1,
2582 u_register_t x2, u_register_t x3,
2583 u_register_t x4, void *cookie,
2584 void *handle, u_register_t flags
2585 Return : uintptr_t
2586
2587 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32`
2588 when the caller of the SMC is running in AArch32 mode
2589 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode.
2590 x1: Timestamp identifier.
2591 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved.
2592 This can be the `mpidr` of a different core to the one initiating
2593 the SMC. In that case, service specific cache maintenance may be
2594 required to ensure the updated copy of the timestamp is returned.
2595 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If
2596 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a
2597 cache invalidate before reading the timestamp. This ensures
2598 an updated copy is returned.
2599
2600The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused
2601in this implementation.
2602
2603PMF code structure
2604~~~~~~~~~~~~~~~~~~
2605
2606#. ``pmf_main.c`` consists of core functions that implement service registration,
2607 initialization, storing, dumping and retrieving timestamps.
2608
2609#. ``pmf_smc.c`` contains the SMC handling for registered PMF services.
2610
2611#. ``pmf.h`` contains the public interface to Performance Measurement Framework.
2612
2613#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in
2614 assembly code.
2615
2616#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``.
2617
Dan Handley610e7e12018-03-01 18:44:00 +00002618Armv8-A Architecture Extensions
2619-------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002620
Dan Handley610e7e12018-03-01 18:44:00 +00002621TF-A makes use of Armv8-A Architecture Extensions where applicable. This
2622section lists the usage of Architecture Extensions, and build flags
2623controlling them.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002624
Manish Pandeyacdaac22023-05-12 14:51:39 +01002625Build options
2626~~~~~~~~~~~~~
2627
2628``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR``
2629
2630These build options serve dual purpose
2631
2632- Determine the architecture extension support in TF-A build: All the mandatory
2633 architectural features up to ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` are included
2634 and unconditionally enabled by TF-A build system.
2635
2636- Passed to compiler via "-march" option to generate binary target : Tell the
2637 compiler to emit instructions upto ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR``
2638
2639The build system requires that the platform provides a valid numeric value based on
2640CPU architecture extension, otherwise it defaults to base Armv8.0-A architecture.
2641Subsequent Arm Architecture versions also support extensions which were introduced
2642in previous versions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002643
Manish Pandeyacdaac22023-05-12 14:51:39 +01002644**TO-DO** : Its planned to decouple the two functionalities and introduce a new macro
2645for compiler usage. The requirement for this decoupling arises becasue TF-A code
2646always provides support for the latest and greatest architecture features but this
2647is not the case for the target compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002648
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01002649.. seealso:: :ref:`Build Options`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002650
2651For details on the Architecture Extension and available features, please refer
2652to the respective Architecture Extension Supplement.
2653
Dan Handley610e7e12018-03-01 18:44:00 +00002654Armv8.1-A
2655~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002656
2657This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when
2658``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1.
2659
Soby Mathewad042012019-09-25 14:03:41 +01002660- By default, a load-/store-exclusive instruction pair is used to implement
2661 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the
2662 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction.
2663 Notice this instruction is only available in AArch64 execution state, so
2664 the option is only available to AArch64 builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002665
Dan Handley610e7e12018-03-01 18:44:00 +00002666Armv8.2-A
2667~~~~~~~~~
Isla Mitchellc4a1a072017-08-07 11:20:13 +01002668
Antonio Nino Diaz633703a2019-02-19 13:14:06 +00002669- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the
2670 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple
Sandrine Bailleuxfee6e262018-01-29 14:48:15 +01002671 Processing Elements in the same Inner Shareable domain use the same
2672 translation table entries for a given stage of translation for a particular
2673 translation regime.
Isla Mitchellc4a1a072017-08-07 11:20:13 +01002674
Jeenu Viswambharancbad6612018-08-15 14:29:29 +01002675Armv8.3-A
2676~~~~~~~~~
2677
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00002678- Pointer authentication features of Armv8.3-A are unconditionally enabled in
2679 the Non-secure world so that lower ELs are allowed to use them without
2680 causing a trap to EL3.
2681
2682 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS``
2683 must be set to 1. This will add all pointer authentication system registers
2684 to the context that is saved when doing a world switch.
Jeenu Viswambharancbad6612018-08-15 14:29:29 +01002685
Alexei Fedorov2831d582019-03-13 11:05:07 +00002686 The TF-A itself has support for pointer authentication at runtime
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002687 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002688 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1,
2689 BL2, BL31, and the TSP if it is used.
2690
Alexei Fedorov2831d582019-03-13 11:05:07 +00002691 Note that Pointer Authentication is enabled for Non-secure world irrespective
2692 of the value of these build flags if the CPU supports it.
2693
Alexei Fedorovb567e5d2019-03-11 16:51:47 +00002694 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of
2695 enabling PAuth is lower because the compiler will use the optimized
2696 PAuth instructions rather than the backwards-compatible ones.
2697
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002698Armv8.5-A
2699~~~~~~~~~
2700
2701- Branch Target Identification feature is selected by ``BRANCH_PROTECTION``
Manish Pandey34a305e2021-10-21 21:53:49 +01002702 option set to 1. This option defaults to 0.
Justin Chadwell55c73512019-07-18 16:16:32 +01002703
2704- Memory Tagging Extension feature is unconditionally enabled for both worlds
2705 (at EL0 and S-EL0) if it is only supported at EL0. If instead it is
2706 implemented at all ELs, it is unconditionally enabled for only the normal
2707 world. To enable it for the secure world as well, the build option
2708 ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement
2709 MTE support at all, it is always disabled, no matter what build options
2710 are used.
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002711
Dan Handley610e7e12018-03-01 18:44:00 +00002712Armv7-A
2713~~~~~~~
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002714
2715This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7.
2716
Dan Handley610e7e12018-03-01 18:44:00 +00002717There are several Armv7-A extensions available. Obviously the TrustZone
2718extension is mandatory to support the TF-A bootloader and runtime services.
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002719
Dan Handley610e7e12018-03-01 18:44:00 +00002720Platform implementing an Armv7-A system can to define from its target
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002721Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002722``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002723Cortex-A15 target.
2724
2725Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support.
Paul Beesleyf2ec7142019-10-04 16:17:46 +00002726Note that using neon at runtime has constraints on non secure world context.
Dan Handley610e7e12018-03-01 18:44:00 +00002727TF-A does not yet provide VFP context management.
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002728
2729Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set
2730the toolchain target architecture directive.
2731
2732Platform may choose to not define straight the toolchain target architecture
2733directive by defining ``MARCH32_DIRECTIVE``.
2734I.e:
2735
Paul Beesley493e3492019-03-13 15:11:04 +00002736.. code:: make
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002737
2738 MARCH32_DIRECTIVE := -mach=armv7-a
2739
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002740Code Structure
2741--------------
2742
Dan Handley610e7e12018-03-01 18:44:00 +00002743TF-A code is logically divided between the three boot loader stages mentioned
2744in the previous sections. The code is also divided into the following
2745categories (present as directories in the source code):
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002746
2747- **Platform specific.** Choice of architecture specific code depends upon
2748 the platform.
2749- **Common code.** This is platform and architecture agnostic code.
2750- **Library code.** This code comprises of functionality commonly used by all
2751 other code. The PSCI implementation and other EL3 runtime frameworks reside
2752 as Library components.
2753- **Stage specific.** Code specific to a boot stage.
2754- **Drivers.**
2755- **Services.** EL3 runtime services (eg: SPD). Specific SPD services
2756 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``).
2757
2758Each boot loader stage uses code from one or more of the above mentioned
2759categories. Based upon the above, the code layout looks like this:
2760
2761::
2762
2763 Directory Used by BL1? Used by BL2? Used by BL31?
2764 bl1 Yes No No
2765 bl2 No Yes No
2766 bl31 No No Yes
2767 plat Yes Yes Yes
2768 drivers Yes No Yes
2769 common Yes Yes Yes
2770 lib Yes Yes Yes
2771 services No No Yes
2772
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002773The build system provides a non configurable build option IMAGE_BLx for each
2774boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be
Dan Handley610e7e12018-03-01 18:44:00 +00002775defined by the build system. This enables TF-A to compile certain code only
2776for specific boot loader stages
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002777
2778All assembler files have the ``.S`` extension. The linker source files for each
2779boot stage have the extension ``.ld.S``. These are processed by GCC to create the
2780linker scripts which have the extension ``.ld``.
2781
2782FDTs provide a description of the hardware platform and are used by the Linux
2783kernel at boot time. These can be found in the ``fdts`` directory.
2784
Paul Beesleyf8640672019-04-12 14:19:42 +01002785.. rubric:: References
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002786
Paul Beesleyf8640672019-04-12 14:19:42 +01002787- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_
2788
2789- `Power State Coordination Interface PDD`_
2790
Sandrine Bailleuxd9202df2020-04-17 14:06:52 +02002791- `SMC Calling Convention`_
Paul Beesleyf8640672019-04-12 14:19:42 +01002792
2793- :ref:`Interrupt Management Framework`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002794
2795--------------
2796
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -06002797*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002798
Paul Beesleyf8640672019-04-12 14:19:42 +01002799.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
laurenw-arm03e7e612020-04-16 10:02:17 -05002800.. _SMCCC: https://developer.arm.com/docs/den0028/latest
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002801.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2802.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
Petre-Ionut Tudor620a7022019-09-27 15:13:21 +01002803.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest
laurenw-arm03e7e612020-04-16 10:02:17 -05002804.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
Sandrine Bailleux30918422019-04-24 10:41:24 +02002805.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
Zelalem Aweke023b1a42021-10-21 13:59:45 -05002806.. _Arm Confidential Compute Architecture (Arm CCA): https://www.arm.com/why-arm/architecture/security-features/arm-confidential-compute-architecture
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002807
Paul Beesley814f8c02019-03-13 15:49:27 +00002808.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png