Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Zelalem | 87675d4 | 2020-02-03 14:56:42 -0600 | [diff] [blame] | 2 | * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 7 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 9 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | |
| 11 | #include <arch_helpers.h> |
| 12 | #include <lib/psci/psci.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 13 | #include <plat/arm/common/plat_arm.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 14 | #include <plat/common/platform.h> |
| 15 | |
Dimitris Papastamos | d7a3651 | 2018-06-18 13:01:06 +0100 | [diff] [blame] | 16 | /* Allow ARM Standard platforms to override these functions */ |
Dimitris Papastamos | d7a3651 | 2018-06-18 13:01:06 +0100 | [diff] [blame] | 17 | #pragma weak plat_arm_program_trusted_mailbox |
Soby Mathew | 0b4c5a3 | 2016-10-21 17:51:22 +0100 | [diff] [blame] | 18 | |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 19 | #if !ARM_RECOM_STATE_ID_ENC |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 20 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 21 | * ARM standard platform handler called to check the validity of the power state |
| 22 | * parameter. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 23 | ******************************************************************************/ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 24 | int arm_validate_power_state(unsigned int power_state, |
| 25 | psci_power_state_t *req_state) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 26 | { |
Antonio Nino Diaz | fec756f | 2018-07-18 16:24:16 +0100 | [diff] [blame] | 27 | unsigned int pstate = psci_get_pstate_type(power_state); |
| 28 | unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state); |
| 29 | unsigned int i; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 30 | |
Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 31 | assert(req_state != NULL); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 32 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 33 | if (pwr_lvl > PLAT_MAX_PWR_LVL) |
| 34 | return PSCI_E_INVALID_PARAMS; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 35 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 36 | /* Sanity check the requested state */ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 37 | if (pstate == PSTATE_TYPE_STANDBY) { |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 38 | /* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 39 | * It's possible to enter standby only on power level 0 |
| 40 | * Ignore any other power level. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 41 | */ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 42 | if (pwr_lvl != ARM_PWR_LVL0) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 43 | return PSCI_E_INVALID_PARAMS; |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 44 | |
| 45 | req_state->pwr_domain_state[ARM_PWR_LVL0] = |
| 46 | ARM_LOCAL_STATE_RET; |
| 47 | } else { |
| 48 | for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++) |
| 49 | req_state->pwr_domain_state[i] = |
| 50 | ARM_LOCAL_STATE_OFF; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 51 | } |
| 52 | |
| 53 | /* |
| 54 | * We expect the 'state id' to be zero. |
| 55 | */ |
Antonio Nino Diaz | fec756f | 2018-07-18 16:24:16 +0100 | [diff] [blame] | 56 | if (psci_get_pstate_id(power_state) != 0U) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 57 | return PSCI_E_INVALID_PARAMS; |
| 58 | |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 59 | return PSCI_E_SUCCESS; |
| 60 | } |
| 61 | |
| 62 | #else |
| 63 | /******************************************************************************* |
| 64 | * ARM standard platform handler called to check the validity of the power |
| 65 | * state parameter. The power state parameter has to be a composite power |
| 66 | * state. |
| 67 | ******************************************************************************/ |
| 68 | int arm_validate_power_state(unsigned int power_state, |
| 69 | psci_power_state_t *req_state) |
| 70 | { |
| 71 | unsigned int state_id; |
| 72 | int i; |
| 73 | |
Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 74 | assert(req_state != NULL); |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 75 | |
| 76 | /* |
| 77 | * Currently we are using a linear search for finding the matching |
| 78 | * entry in the idle power state array. This can be made a binary |
| 79 | * search if the number of entries justify the additional complexity. |
| 80 | */ |
| 81 | for (i = 0; !!arm_pm_idle_states[i]; i++) { |
| 82 | if (power_state == arm_pm_idle_states[i]) |
| 83 | break; |
| 84 | } |
| 85 | |
| 86 | /* Return error if entry not found in the idle state array */ |
| 87 | if (!arm_pm_idle_states[i]) |
| 88 | return PSCI_E_INVALID_PARAMS; |
| 89 | |
| 90 | i = 0; |
| 91 | state_id = psci_get_pstate_id(power_state); |
| 92 | |
| 93 | /* Parse the State ID and populate the state info parameter */ |
| 94 | while (state_id) { |
| 95 | req_state->pwr_domain_state[i++] = state_id & |
| 96 | ARM_LOCAL_PSTATE_MASK; |
| 97 | state_id >>= ARM_LOCAL_PSTATE_WIDTH; |
| 98 | } |
| 99 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 100 | return PSCI_E_SUCCESS; |
| 101 | } |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 102 | #endif /* __ARM_RECOM_STATE_ID_ENC__ */ |
Soby Mathew | 0d9e852 | 2015-07-15 13:36:24 +0100 | [diff] [blame] | 103 | |
| 104 | /******************************************************************************* |
| 105 | * ARM standard platform handler called to check the validity of the non secure |
Jeenu Viswambharan | 59424d8 | 2017-09-19 09:27:18 +0100 | [diff] [blame] | 106 | * entrypoint. Returns 0 if the entrypoint is valid, or -1 otherwise. |
Soby Mathew | 0d9e852 | 2015-07-15 13:36:24 +0100 | [diff] [blame] | 107 | ******************************************************************************/ |
| 108 | int arm_validate_ns_entrypoint(uintptr_t entrypoint) |
| 109 | { |
| 110 | /* |
| 111 | * Check if the non secure entrypoint lies within the non |
| 112 | * secure DRAM. |
| 113 | */ |
| 114 | if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < |
Jeenu Viswambharan | 59424d8 | 2017-09-19 09:27:18 +0100 | [diff] [blame] | 115 | (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { |
| 116 | return 0; |
| 117 | } |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 118 | #ifdef __aarch64__ |
Soby Mathew | 0d9e852 | 2015-07-15 13:36:24 +0100 | [diff] [blame] | 119 | if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < |
Jeenu Viswambharan | 59424d8 | 2017-09-19 09:27:18 +0100 | [diff] [blame] | 120 | (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { |
| 121 | return 0; |
| 122 | } |
dp-arm | 84fc295 | 2017-05-03 12:14:10 +0100 | [diff] [blame] | 123 | #endif |
Soby Mathew | 0d9e852 | 2015-07-15 13:36:24 +0100 | [diff] [blame] | 124 | |
Jeenu Viswambharan | 59424d8 | 2017-09-19 09:27:18 +0100 | [diff] [blame] | 125 | return -1; |
| 126 | } |
| 127 | |
| 128 | int arm_validate_psci_entrypoint(uintptr_t entrypoint) |
| 129 | { |
Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 130 | return (arm_validate_ns_entrypoint(entrypoint) == 0) ? PSCI_E_SUCCESS : |
Jeenu Viswambharan | 59424d8 | 2017-09-19 09:27:18 +0100 | [diff] [blame] | 131 | PSCI_E_INVALID_ADDRESS; |
Soby Mathew | 0d9e852 | 2015-07-15 13:36:24 +0100 | [diff] [blame] | 132 | } |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 133 | |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 134 | /****************************************************************************** |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 135 | * Helper function to save the platform state before a system suspend. Save the |
| 136 | * state of the system components which are not in the Always ON power domain. |
| 137 | *****************************************************************************/ |
| 138 | void arm_system_pwr_domain_save(void) |
| 139 | { |
| 140 | /* Assert system power domain is available on the platform */ |
| 141 | assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); |
| 142 | |
| 143 | plat_arm_gic_save(); |
| 144 | |
| 145 | /* |
Antonio Nino Diaz | 23ede6a | 2018-06-19 09:29:36 +0100 | [diff] [blame] | 146 | * Unregister console now so that it is not registered for a second |
| 147 | * time during resume. |
| 148 | */ |
| 149 | arm_console_runtime_end(); |
| 150 | |
| 151 | /* |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 152 | * All the other peripheral which are configured by ARM TF are |
| 153 | * re-initialized on resume from system suspend. Hence we |
| 154 | * don't save their state here. |
| 155 | */ |
| 156 | } |
| 157 | |
| 158 | /****************************************************************************** |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 159 | * Helper function to resume the platform from system suspend. Reinitialize |
| 160 | * the system components which are not in the Always ON power domain. |
| 161 | * TODO: Unify the platform setup when waking up from cold boot and system |
| 162 | * resume in arm_bl31_platform_setup(). |
| 163 | *****************************************************************************/ |
| 164 | void arm_system_pwr_domain_resume(void) |
| 165 | { |
Antonio Nino Diaz | 23ede6a | 2018-06-19 09:29:36 +0100 | [diff] [blame] | 166 | /* Initialize the console */ |
| 167 | arm_console_runtime_init(); |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 168 | |
| 169 | /* Assert system power domain is available on the platform */ |
| 170 | assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); |
| 171 | |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 172 | plat_arm_gic_resume(); |
| 173 | |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 174 | plat_arm_security_setup(); |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 175 | arm_configure_sys_timer(); |
| 176 | } |
| 177 | |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 178 | /******************************************************************************* |
Dimitris Papastamos | d7a3651 | 2018-06-18 13:01:06 +0100 | [diff] [blame] | 179 | * ARM platform function to program the mailbox for a cpu before it is released |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 180 | * from reset. This function assumes that the Trusted mail box base is within |
| 181 | * the ARM_SHARED_RAM region |
| 182 | ******************************************************************************/ |
Dimitris Papastamos | d7a3651 | 2018-06-18 13:01:06 +0100 | [diff] [blame] | 183 | void plat_arm_program_trusted_mailbox(uintptr_t address) |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 184 | { |
| 185 | uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE; |
| 186 | |
| 187 | *mailbox = address; |
| 188 | |
| 189 | /* |
| 190 | * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within |
| 191 | * ARM_SHARED_RAM region. |
| 192 | */ |
| 193 | assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) && |
| 194 | ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \ |
| 195 | (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE))); |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | /******************************************************************************* |
| 199 | * The ARM Standard platform definition of platform porting API |
| 200 | * `plat_setup_psci_ops`. |
| 201 | ******************************************************************************/ |
Daniel Boulby | f45a4bb | 2018-09-18 13:26:03 +0100 | [diff] [blame] | 202 | int __init plat_setup_psci_ops(uintptr_t sec_entrypoint, |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 203 | const plat_psci_ops_t **psci_ops) |
| 204 | { |
Soby Mathew | 0b4c5a3 | 2016-10-21 17:51:22 +0100 | [diff] [blame] | 205 | *psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops); |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 206 | |
| 207 | /* Setup mailbox with entry point. */ |
Dimitris Papastamos | d7a3651 | 2018-06-18 13:01:06 +0100 | [diff] [blame] | 208 | plat_arm_program_trusted_mailbox(sec_entrypoint); |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 209 | return 0; |
| 210 | } |