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Achin Gupta7aea9082014-02-01 07:51:28 +00001/*
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta7aea9082014-02-01 07:51:28 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta7aea9082014-02-01 07:51:28 +00005 */
6
Dimitris Papastamose08005a2017-10-12 13:02:29 +01007#include <amu.h>
Achin Gupta27b895e2014-05-04 18:38:28 +01008#include <arch.h>
Achin Gupta7aea9082014-02-01 07:51:28 +00009#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010010#include <assert.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000011#include <bl_common.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010012#include <context.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000013#include <context_mgmt.h>
Achin Gupta191e86e2014-05-09 10:03:15 +010014#include <interrupt_mgmt.h>
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +010015#include <mpam.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010016#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010017#include <platform_def.h>
Dimitris Papastamosa7921b92017-10-13 15:27:58 +010018#include <pubsub_events.h>
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000019#include <smccc_helpers.h>
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010020#include <spe.h>
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +010021#include <stdbool.h>
Andrew Thoelke4e126072014-06-04 21:10:52 +010022#include <string.h>
David Cunadoce88eee2017-10-20 11:30:57 +010023#include <sve.h>
Douglas Raillarda8954fc2017-01-26 15:54:44 +000024#include <utils.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000025
Achin Gupta7aea9082014-02-01 07:51:28 +000026
27/*******************************************************************************
28 * Context management library initialisation routine. This library is used by
29 * runtime services to share pointers to 'cpu_context' structures for the secure
30 * and non-secure states. Management of the structures and their associated
31 * memory is not done by the context management library e.g. the PSCI service
32 * manages the cpu context used for entry from and exit to the non-secure state.
33 * The Secure payload dispatcher service manages the context(s) corresponding to
34 * the secure state. It also uses this library to get access to the non-secure
35 * state cpu context pointers.
36 * Lastly, this library provides the api to make SP_EL3 point to the cpu context
37 * which will used for programming an entry into a lower EL. The same context
38 * will used to save state upon exception entry from that EL.
39 ******************************************************************************/
Daniel Boulby5753e492018-09-20 14:12:46 +010040void __init cm_init(void)
Achin Gupta7aea9082014-02-01 07:51:28 +000041{
42 /*
43 * The context management library has only global data to intialize, but
44 * that will be done when the BSS is zeroed out
45 */
46}
47
48/*******************************************************************************
Soby Mathewb0082d22015-04-09 13:40:55 +010049 * The following function initializes the cpu_context 'ctx' for
Andrew Thoelke4e126072014-06-04 21:10:52 +010050 * first use, and sets the initial entrypoint state as specified by the
51 * entry_point_info structure.
52 *
53 * The security state to initialize is determined by the SECURE attribute
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +010054 * of the entry_point_info.
Andrew Thoelke4e126072014-06-04 21:10:52 +010055 *
56 * The EE and ST attributes are used to configure the endianess and secure
Soby Mathewb0082d22015-04-09 13:40:55 +010057 * timer availability for the new execution context.
Andrew Thoelke4e126072014-06-04 21:10:52 +010058 *
59 * To prepare the register state for entry call cm_prepare_el3_exit() and
60 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
61 * cm_e1_sysreg_context_restore().
62 ******************************************************************************/
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +010063void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
Andrew Thoelke4e126072014-06-04 21:10:52 +010064{
Soby Mathewb0082d22015-04-09 13:40:55 +010065 unsigned int security_state;
David Cunado4168f2f2017-10-02 17:41:39 +010066 uint32_t scr_el3, pmcr_el0;
Andrew Thoelke4e126072014-06-04 21:10:52 +010067 el3_state_t *state;
68 gp_regs_t *gp_regs;
Varun Wadekarb6dd0b32018-05-08 10:52:36 -070069 unsigned long sctlr_elx, actlr_elx;
Andrew Thoelke4e126072014-06-04 21:10:52 +010070
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +000071 assert(ctx != NULL);
Andrew Thoelke4e126072014-06-04 21:10:52 +010072
Soby Mathewb0082d22015-04-09 13:40:55 +010073 security_state = GET_SECURITY_STATE(ep->h.attr);
74
Andrew Thoelke4e126072014-06-04 21:10:52 +010075 /* Clear any residual register values from the context */
Douglas Raillarda8954fc2017-01-26 15:54:44 +000076 zeromem(ctx, sizeof(*ctx));
Andrew Thoelke4e126072014-06-04 21:10:52 +010077
78 /*
David Cunadofee86532017-04-13 22:38:29 +010079 * SCR_EL3 was initialised during reset sequence in macro
80 * el3_arch_init_common. This code modifies the SCR_EL3 fields that
81 * affect the next EL.
82 *
83 * The following fields are initially set to zero and then updated to
84 * the required value depending on the state of the SPSR_EL3 and the
85 * Security state and entrypoint attributes of the next EL.
Andrew Thoelke4e126072014-06-04 21:10:52 +010086 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +000087 scr_el3 = (uint32_t)read_scr();
Andrew Thoelke4e126072014-06-04 21:10:52 +010088 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
89 SCR_ST_BIT | SCR_HCE_BIT);
David Cunadofee86532017-04-13 22:38:29 +010090 /*
91 * SCR_NS: Set the security state of the next EL.
92 */
Andrew Thoelke4e126072014-06-04 21:10:52 +010093 if (security_state != SECURE)
94 scr_el3 |= SCR_NS_BIT;
David Cunadofee86532017-04-13 22:38:29 +010095 /*
96 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
97 * Exception level as specified by SPSR.
98 */
Andrew Thoelke4e126072014-06-04 21:10:52 +010099 if (GET_RW(ep->spsr) == MODE_RW_64)
100 scr_el3 |= SCR_RW_BIT;
David Cunadofee86532017-04-13 22:38:29 +0100101 /*
102 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
103 * Secure timer registers to EL3, from AArch64 state only, if specified
104 * by the entrypoint attributes.
105 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000106 if (EP_GET_ST(ep->h.attr) != 0U)
Andrew Thoelke4e126072014-06-04 21:10:52 +0100107 scr_el3 |= SCR_ST_BIT;
108
Julius Wernerc51a2ec2018-08-28 14:45:43 -0700109#if !HANDLE_EA_EL3_FIRST
David Cunadofee86532017-04-13 22:38:29 +0100110 /*
111 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External
112 * to EL3 when executing at a lower EL. When executing at EL3, External
113 * Aborts are taken to EL3.
114 */
Gerald Lejeune632d6df2016-03-22 09:29:23 +0100115 scr_el3 &= ~SCR_EA_BIT;
116#endif
117
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000118#if FAULT_INJECTION_SUPPORT
119 /* Enable fault injection from lower ELs */
120 scr_el3 |= SCR_FIEN_BIT;
121#endif
122
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900123#ifdef IMAGE_BL31
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100124 /*
David Cunadofee86532017-04-13 22:38:29 +0100125 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ rounting as
126 * indicated by the interrupt routing model for BL31.
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100127 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100128 scr_el3 |= get_scr_el3_from_routing_model(security_state);
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100129#endif
Andrew Thoelke4e126072014-06-04 21:10:52 +0100130
131 /*
David Cunadofee86532017-04-13 22:38:29 +0100132 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
133 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
134 * next mode is Hyp.
135 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000136 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
137 || ((GET_RW(ep->spsr) != MODE_RW_64)
138 && (GET_M32(ep->spsr) == MODE32_hyp))) {
David Cunadofee86532017-04-13 22:38:29 +0100139 scr_el3 |= SCR_HCE_BIT;
140 }
141
142 /*
143 * Initialise SCTLR_EL1 to the reset value corresponding to the target
144 * execution state setting all fields rather than relying of the hw.
145 * Some fields have architecturally UNKNOWN reset values and these are
146 * set to zero.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100147 *
David Cunadofee86532017-04-13 22:38:29 +0100148 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100149 *
David Cunadofee86532017-04-13 22:38:29 +0100150 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
151 * required by PSCI specification)
Andrew Thoelke4e126072014-06-04 21:10:52 +0100152 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000153 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U;
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200154 if (GET_RW(ep->spsr) == MODE_RW_64)
155 sctlr_elx |= SCTLR_EL1_RES1;
Soby Mathewa993c422016-09-29 14:15:57 +0100156 else {
Soby Mathewa993c422016-09-29 14:15:57 +0100157 /*
David Cunadofee86532017-04-13 22:38:29 +0100158 * If the target execution state is AArch32 then the following
159 * fields need to be set.
160 *
161 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
162 * instructions are not trapped to EL1.
163 *
164 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
165 * instructions are not trapped to EL1.
166 *
167 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
168 * CP15DMB, CP15DSB, and CP15ISB instructions.
Soby Mathewa993c422016-09-29 14:15:57 +0100169 */
David Cunadofee86532017-04-13 22:38:29 +0100170 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
171 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
Soby Mathewa993c422016-09-29 14:15:57 +0100172 }
173
David Cunadofee86532017-04-13 22:38:29 +0100174 /*
175 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
David Cunado4168f2f2017-10-02 17:41:39 +0100176 * and other EL2 registers are set up by cm_preapre_ns_entry() as they
David Cunadofee86532017-04-13 22:38:29 +0100177 * are not part of the stored cpu_context.
178 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100179 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
180
Varun Wadekarb6dd0b32018-05-08 10:52:36 -0700181 /*
182 * Base the context ACTLR_EL1 on the current value, as it is
183 * implementation defined. The context restore process will write
184 * the value from the context to the actual register and can cause
185 * problems for processor cores that don't expect certain bits to
186 * be zero.
187 */
188 actlr_elx = read_actlr_el1();
189 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
190
David Cunado4168f2f2017-10-02 17:41:39 +0100191 if (security_state == SECURE) {
192 /*
193 * Initialise PMCR_EL0 for secure context only, setting all
194 * fields rather than relying on hw. Some fields are
195 * architecturally UNKNOWN on reset.
196 *
197 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that
198 * is recorded in PMOVSCLR_EL0[31], occurs on the increment
199 * that changes PMCCNTR_EL0[63] from 1 to 0.
200 *
201 * PMCR_EL0.DP: Set to one so that the cycle counter,
202 * PMCCNTR_EL0 does not count when event counting is prohibited.
203 *
204 * PMCR_EL0.X: Set to zero to disable export of events.
205 *
206 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0
207 * counts on every clock cycle.
208 */
209 pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT
210 | PMCR_EL0_DP_BIT)
211 & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT));
212 write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0);
213 }
214
Andrew Thoelke4e126072014-06-04 21:10:52 +0100215 /* Populate EL3 state so that we've the right context before doing ERET */
216 state = get_el3state_ctx(ctx);
217 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
218 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
219 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
220
221 /*
222 * Store the X0-X7 value from the entrypoint into the context
223 * Use memcpy as we are in control of the layout of the structures
224 */
225 gp_regs = get_gpregs_ctx(ctx);
226 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
227}
228
229/*******************************************************************************
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000230 * Enable architecture extensions on first entry to Non-secure world.
231 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
232 * it is zero.
233 ******************************************************************************/
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100234static void enable_extensions_nonsecure(bool el2_unused)
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000235{
236#if IMAGE_BL31
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100237#if ENABLE_SPE_FOR_LOWER_ELS
238 spe_enable(el2_unused);
239#endif
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100240
241#if ENABLE_AMU
242 amu_enable(el2_unused);
243#endif
David Cunadoce88eee2017-10-20 11:30:57 +0100244
245#if ENABLE_SVE_FOR_NS
246 sve_enable(el2_unused);
247#endif
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100248
249#if ENABLE_MPAM_FOR_LOWER_ELS
250 mpam_enable(el2_unused);
251#endif
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000252#endif
253}
254
255/*******************************************************************************
Soby Mathewb0082d22015-04-09 13:40:55 +0100256 * The following function initializes the cpu_context for a CPU specified by
257 * its `cpu_idx` for first use, and sets the initial entrypoint state as
258 * specified by the entry_point_info structure.
259 ******************************************************************************/
260void cm_init_context_by_index(unsigned int cpu_idx,
261 const entry_point_info_t *ep)
262{
263 cpu_context_t *ctx;
264 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100265 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100266}
267
268/*******************************************************************************
269 * The following function initializes the cpu_context for the current CPU
270 * for first use, and sets the initial entrypoint state as specified by the
271 * entry_point_info structure.
272 ******************************************************************************/
273void cm_init_my_context(const entry_point_info_t *ep)
274{
275 cpu_context_t *ctx;
276 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100277 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100278}
279
280/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100281 * Prepare the CPU system registers for first entry into secure or normal world
282 *
283 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
284 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
285 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
286 * For all entries, the EL1 registers are initialized from the cpu_context
287 ******************************************************************************/
288void cm_prepare_el3_exit(uint32_t security_state)
289{
dp-armee3457b2017-05-23 09:32:49 +0100290 uint32_t sctlr_elx, scr_el3, mdcr_el2;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100291 cpu_context_t *ctx = cm_get_context(security_state);
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100292 bool el2_unused = false;
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000293 uint64_t hcr_el2 = 0U;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100294
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000295 assert(ctx != NULL);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100296
297 if (security_state == NON_SECURE) {
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000298 scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx),
299 CTX_SCR_EL3);
300 if ((scr_el3 & SCR_HCE_BIT) != 0U) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100301 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000302 sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx),
303 CTX_SCTLR_EL1);
Ken Kuang00eac152017-08-23 16:03:29 +0800304 sctlr_elx &= SCTLR_EE_BIT;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100305 sctlr_elx |= SCTLR_EL2_RES1;
306 write_sctlr_el2(sctlr_elx);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000307 } else if (el_implemented(2) != EL_IMPL_NONE) {
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100308 el2_unused = true;
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000309
David Cunadofee86532017-04-13 22:38:29 +0100310 /*
311 * EL2 present but unused, need to disable safely.
312 * SCTLR_EL2 can be ignored in this case.
313 *
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100314 * Set EL2 register width appropriately: Set HCR_EL2
315 * field to match SCR_EL3.RW.
David Cunadofee86532017-04-13 22:38:29 +0100316 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000317 if ((scr_el3 & SCR_RW_BIT) != 0U)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100318 hcr_el2 |= HCR_RW_BIT;
319
320 /*
321 * For Armv8.3 pointer authentication feature, disable
322 * traps to EL2 when accessing key registers or using
323 * pointer authentication instructions from lower ELs.
324 */
325 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
326
327 write_hcr_el2(hcr_el2);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100328
David Cunadofee86532017-04-13 22:38:29 +0100329 /*
330 * Initialise CPTR_EL2 setting all fields rather than
331 * relying on the hw. All fields have architecturally
332 * UNKNOWN reset values.
333 *
334 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1
335 * accesses to the CPACR_EL1 or CPACR from both
336 * Execution states do not trap to EL2.
337 *
338 * CPTR_EL2.TTA: Set to zero so that Non-secure System
339 * register accesses to the trace registers from both
340 * Execution states do not trap to EL2.
341 *
342 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses
343 * to SIMD and floating-point functionality from both
344 * Execution states do not trap to EL2.
345 */
346 write_cptr_el2(CPTR_EL2_RESET_VAL &
347 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT
348 | CPTR_EL2_TFP_BIT));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100349
David Cunadofee86532017-04-13 22:38:29 +0100350 /*
351 * Initiliase CNTHCTL_EL2. All fields are
352 * architecturally UNKNOWN on reset and are set to zero
353 * except for field(s) listed below.
354 *
355 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to
356 * Hyp mode of Non-secure EL0 and EL1 accesses to the
357 * physical timer registers.
358 *
359 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to
360 * Hyp mode of Non-secure EL0 and EL1 accesses to the
361 * physical counter registers.
362 */
363 write_cnthctl_el2(CNTHCTL_RESET_VAL |
364 EL1PCEN_BIT | EL1PCTEN_BIT);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100365
David Cunadofee86532017-04-13 22:38:29 +0100366 /*
367 * Initialise CNTVOFF_EL2 to zero as it resets to an
368 * architecturally UNKNOWN value.
369 */
Soby Mathewfeddfcf2014-08-29 14:41:58 +0100370 write_cntvoff_el2(0);
371
David Cunadofee86532017-04-13 22:38:29 +0100372 /*
373 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and
374 * MPIDR_EL1 respectively.
375 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100376 write_vpidr_el2(read_midr_el1());
377 write_vmpidr_el2(read_mpidr_el1());
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000378
379 /*
David Cunadofee86532017-04-13 22:38:29 +0100380 * Initialise VTTBR_EL2. All fields are architecturally
381 * UNKNOWN on reset.
382 *
383 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage
384 * 2 address translation is disabled, cache maintenance
385 * operations depend on the VMID.
386 *
387 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address
388 * translation is disabled.
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000389 */
David Cunadofee86532017-04-13 22:38:29 +0100390 write_vttbr_el2(VTTBR_RESET_VAL &
391 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
392 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
393
David Cunado5f55e282016-10-31 17:37:34 +0000394 /*
David Cunadofee86532017-04-13 22:38:29 +0100395 * Initialise MDCR_EL2, setting all fields rather than
396 * relying on hw. Some fields are architecturally
397 * UNKNOWN on reset.
398 *
399 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
400 * EL1 System register accesses to the Debug ROM
401 * registers are not trapped to EL2.
402 *
403 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1
404 * System register accesses to the powerdown debug
405 * registers are not trapped to EL2.
406 *
407 * MDCR_EL2.TDA: Set to zero so that System register
408 * accesses to the debug registers do not trap to EL2.
409 *
410 * MDCR_EL2.TDE: Set to zero so that debug exceptions
411 * are not routed to EL2.
412 *
413 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance
414 * Monitors.
415 *
416 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and
417 * EL1 accesses to all Performance Monitors registers
418 * are not trapped to EL2.
419 *
420 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0
421 * and EL1 accesses to the PMCR_EL0 or PMCR are not
422 * trapped to EL2.
423 *
424 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the
425 * architecturally-defined reset value.
David Cunado5f55e282016-10-31 17:37:34 +0000426 */
dp-armee3457b2017-05-23 09:32:49 +0100427 mdcr_el2 = ((MDCR_EL2_RESET_VAL |
David Cunadofee86532017-04-13 22:38:29 +0100428 ((read_pmcr_el0() & PMCR_EL0_N_BITS)
429 >> PMCR_EL0_N_SHIFT)) &
430 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT
431 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT
432 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT
433 | MDCR_EL2_TPMCR_BIT));
dp-armee3457b2017-05-23 09:32:49 +0100434
dp-armee3457b2017-05-23 09:32:49 +0100435 write_mdcr_el2(mdcr_el2);
436
David Cunadoc14b08e2016-11-25 00:21:59 +0000437 /*
David Cunadofee86532017-04-13 22:38:29 +0100438 * Initialise HSTR_EL2. All fields are architecturally
439 * UNKNOWN on reset.
440 *
441 * HSTR_EL2.T<n>: Set all these fields to zero so that
442 * Non-secure EL0 or EL1 accesses to System registers
443 * do not trap to EL2.
David Cunadoc14b08e2016-11-25 00:21:59 +0000444 */
David Cunadofee86532017-04-13 22:38:29 +0100445 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
David Cunadoc14b08e2016-11-25 00:21:59 +0000446 /*
David Cunadofee86532017-04-13 22:38:29 +0100447 * Initialise CNTHP_CTL_EL2. All fields are
448 * architecturally UNKNOWN on reset.
449 *
450 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2
451 * physical timer and prevent timer interrupts.
David Cunadoc14b08e2016-11-25 00:21:59 +0000452 */
David Cunadofee86532017-04-13 22:38:29 +0100453 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL &
454 ~(CNTHP_CTL_ENABLE_BIT));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100455 }
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000456 enable_extensions_nonsecure(el2_unused);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100457 }
458
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100459 cm_el1_sysregs_context_restore(security_state);
460 cm_set_next_eret_context(security_state);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100461}
462
463/*******************************************************************************
Soby Mathew2ed46e92014-07-04 16:02:26 +0100464 * The next four functions are used by runtime services to save and restore
465 * EL1 context on the 'cpu_context' structure for the specified security
Achin Gupta7aea9082014-02-01 07:51:28 +0000466 * state.
467 ******************************************************************************/
Achin Gupta7aea9082014-02-01 07:51:28 +0000468void cm_el1_sysregs_context_save(uint32_t security_state)
469{
Dan Handleye2712bc2014-04-10 15:37:22 +0100470 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +0000471
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100472 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000473 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +0000474
475 el1_sysregs_context_save(get_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100476
477#if IMAGE_BL31
478 if (security_state == SECURE)
479 PUBLISH_EVENT(cm_exited_secure_world);
480 else
481 PUBLISH_EVENT(cm_exited_normal_world);
482#endif
Achin Gupta7aea9082014-02-01 07:51:28 +0000483}
484
485void cm_el1_sysregs_context_restore(uint32_t security_state)
486{
Dan Handleye2712bc2014-04-10 15:37:22 +0100487 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +0000488
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100489 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000490 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +0000491
492 el1_sysregs_context_restore(get_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100493
494#if IMAGE_BL31
495 if (security_state == SECURE)
496 PUBLISH_EVENT(cm_entering_secure_world);
497 else
498 PUBLISH_EVENT(cm_entering_normal_world);
499#endif
Achin Gupta7aea9082014-02-01 07:51:28 +0000500}
501
502/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100503 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
504 * given security state with the given entrypoint
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000505 ******************************************************************************/
Soby Mathewa0fedc42016-06-16 14:52:04 +0100506void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000507{
Dan Handleye2712bc2014-04-10 15:37:22 +0100508 cpu_context_t *ctx;
509 el3_state_t *state;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000510
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100511 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000512 assert(ctx != NULL);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000513
Andrew Thoelke4e126072014-06-04 21:10:52 +0100514 /* Populate EL3 state so that ERET jumps to the correct entry */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000515 state = get_el3state_ctx(ctx);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000516 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000517}
518
519/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100520 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
521 * pertaining to the given security state
Achin Gupta607084e2014-02-09 18:24:19 +0000522 ******************************************************************************/
Andrew Thoelke4e126072014-06-04 21:10:52 +0100523void cm_set_elr_spsr_el3(uint32_t security_state,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100524 uintptr_t entrypoint, uint32_t spsr)
Achin Gupta607084e2014-02-09 18:24:19 +0000525{
Dan Handleye2712bc2014-04-10 15:37:22 +0100526 cpu_context_t *ctx;
527 el3_state_t *state;
Achin Gupta607084e2014-02-09 18:24:19 +0000528
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100529 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000530 assert(ctx != NULL);
Achin Gupta607084e2014-02-09 18:24:19 +0000531
532 /* Populate EL3 state so that ERET jumps to the correct entry */
533 state = get_el3state_ctx(ctx);
534 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100535 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
Achin Gupta607084e2014-02-09 18:24:19 +0000536}
537
538/*******************************************************************************
Achin Gupta27b895e2014-05-04 18:38:28 +0100539 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
540 * pertaining to the given security state using the value and bit position
541 * specified in the parameters. It preserves all other bits.
542 ******************************************************************************/
543void cm_write_scr_el3_bit(uint32_t security_state,
544 uint32_t bit_pos,
545 uint32_t value)
546{
547 cpu_context_t *ctx;
548 el3_state_t *state;
549 uint32_t scr_el3;
550
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100551 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000552 assert(ctx != NULL);
Achin Gupta27b895e2014-05-04 18:38:28 +0100553
554 /* Ensure that the bit position is a valid one */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000555 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
Achin Gupta27b895e2014-05-04 18:38:28 +0100556
557 /* Ensure that the 'value' is only a bit wide */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000558 assert(value <= 1U);
Achin Gupta27b895e2014-05-04 18:38:28 +0100559
560 /*
561 * Get the SCR_EL3 value from the cpu context, clear the desired bit
562 * and set it to its new value.
563 */
564 state = get_el3state_ctx(ctx);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000565 scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
566 scr_el3 &= ~(1U << bit_pos);
Achin Gupta27b895e2014-05-04 18:38:28 +0100567 scr_el3 |= value << bit_pos;
568 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
569}
570
571/*******************************************************************************
572 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
573 * given security state.
574 ******************************************************************************/
575uint32_t cm_get_scr_el3(uint32_t security_state)
576{
577 cpu_context_t *ctx;
578 el3_state_t *state;
579
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100580 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000581 assert(ctx != NULL);
Achin Gupta27b895e2014-05-04 18:38:28 +0100582
583 /* Populate EL3 state so that ERET jumps to the correct entry */
584 state = get_el3state_ctx(ctx);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000585 return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
Achin Gupta27b895e2014-05-04 18:38:28 +0100586}
587
588/*******************************************************************************
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000589 * This function is used to program the context that's used for exception
590 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
591 * the required security state
Achin Gupta7aea9082014-02-01 07:51:28 +0000592 ******************************************************************************/
593void cm_set_next_eret_context(uint32_t security_state)
594{
Dan Handleye2712bc2014-04-10 15:37:22 +0100595 cpu_context_t *ctx;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000596
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100597 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000598 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +0000599
Andrew Thoelke4e126072014-06-04 21:10:52 +0100600 cm_set_next_context(ctx);
Achin Gupta7aea9082014-02-01 07:51:28 +0000601}