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Harry Liebel43ef4f12013-10-22 17:29:14 +01001/*
Alexei Fedorovcb8fef62021-04-12 12:49:54 +01002 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
Harry Liebel43ef4f12013-10-22 17:29:14 +01003 *
Achin Gupta69387312016-09-26 10:22:56 +01004 * SPDX-License-Identifier: BSD-3-Clause
Harry Liebel43ef4f12013-10-22 17:29:14 +01005 */
6
Alexei Fedorov4348f492020-05-13 21:13:57 +01007/* Configuration: 1 cluster with up to 4 CPUs */
8
Harry Liebel43ef4f12013-10-22 17:29:14 +01009/dts-v1/;
10
Alexei Fedorov4348f492020-05-13 21:13:57 +010011#define AFF
12#define CLUSTER_COUNT 1
13
14#include "fvp-defs.dtsi"
Alexei Fedorovcb8fef62021-04-12 12:49:54 +010015#include <dt-bindings/interrupt-controller/arm-gic.h>
Alexei Fedorov4348f492020-05-13 21:13:57 +010016
Harry Liebel43ef4f12013-10-22 17:29:14 +010017/memreserve/ 0x80000000 0x00010000;
18
19/ {
20};
21
22/ {
Harry Liebelcef93392014-04-01 19:27:38 +010023 model = "FVP Foundation";
Harry Liebel43ef4f12013-10-22 17:29:14 +010024 compatible = "arm,fvp-base", "arm,vexpress";
25 interrupt-parent = <&gic>;
26 #address-cells = <2>;
27 #size-cells = <2>;
28
29 chosen { };
30
31 aliases {
32 serial0 = &v2m_serial0;
33 serial1 = &v2m_serial1;
34 serial2 = &v2m_serial2;
35 serial3 = &v2m_serial3;
36 };
37
38 psci {
Soby Mathew1df077b2015-01-15 11:49:58 +000039 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
Harry Liebel43ef4f12013-10-22 17:29:14 +010040 method = "smc";
41 cpu_suspend = <0xc4000001>;
42 cpu_off = <0x84000002>;
43 cpu_on = <0xc4000003>;
Soby Mathewe0f55df2016-10-05 15:38:01 +010044 sys_poweroff = <0x84000008>;
45 sys_reset = <0x84000009>;
Madhukar Pappireddy26b945c2019-12-27 12:02:34 -060046 max-pwr-lvl = <2>;
Harry Liebel43ef4f12013-10-22 17:29:14 +010047 };
48
49 cpus {
50 #address-cells = <2>;
51 #size-cells = <0>;
52
Alexei Fedorov4348f492020-05-13 21:13:57 +010053 CPU_MAP
Achin Gupta5ab4fe42014-08-20 17:33:09 +010054
55 idle-states {
56 entry-method = "arm,psci";
57
58 CPU_SLEEP_0: cpu-sleep-0 {
59 compatible = "arm,idle-state";
Juan Castillo3414f542015-04-16 14:17:49 +010060 local-timer-stop;
61 arm,psci-suspend-param = <0x0010000>;
Achin Gupta5ab4fe42014-08-20 17:33:09 +010062 entry-latency-us = <40>;
63 exit-latency-us = <100>;
64 min-residency-us = <150>;
65 };
66
67 CLUSTER_SLEEP_0: cluster-sleep-0 {
68 compatible = "arm,idle-state";
Juan Castillo3414f542015-04-16 14:17:49 +010069 local-timer-stop;
70 arm,psci-suspend-param = <0x1010000>;
Achin Gupta5ab4fe42014-08-20 17:33:09 +010071 entry-latency-us = <500>;
72 exit-latency-us = <1000>;
73 min-residency-us = <2500>;
74 };
75 };
76
Alexei Fedorov4348f492020-05-13 21:13:57 +010077 CPUS
Antonio Nino Diaz430147a2016-02-22 16:44:41 +000078
79 L2_0: l2-cache0 {
80 compatible = "cache";
Harry Liebel43ef4f12013-10-22 17:29:14 +010081 };
82 };
83
84 memory@80000000 {
85 device_type = "memory";
Juan Castillo7055ca42014-05-16 15:33:15 +010086 reg = <0x00000000 0x80000000 0 0x7F000000>,
Harry Liebel43ef4f12013-10-22 17:29:14 +010087 <0x00000008 0x80000000 0 0x80000000>;
88 };
89
Harry Liebel34988592013-11-11 13:24:47 +000090 gic: interrupt-controller@2f000000 {
Harry Liebel43ef4f12013-10-22 17:29:14 +010091 compatible = "arm,gic-v3";
92 #interrupt-cells = <3>;
Harry Liebel34988592013-11-11 13:24:47 +000093 #address-cells = <2>;
94 #size-cells = <2>;
95 ranges;
Harry Liebel43ef4f12013-10-22 17:29:14 +010096 interrupt-controller;
97 reg = <0x0 0x2f000000 0 0x10000>, // GICD
98 <0x0 0x2f100000 0 0x200000>, // GICR
99 <0x0 0x2c000000 0 0x2000>, // GICC
100 <0x0 0x2c010000 0 0x2000>, // GICH
Harry Liebel34988592013-11-11 13:24:47 +0000101 <0x0 0x2c02f000 0 0x2000>; // GICV
Harry Liebel43ef4f12013-10-22 17:29:14 +0100102 interrupts = <1 9 4>;
Harry Liebel34988592013-11-11 13:24:47 +0000103
104 its: its@2f020000 {
105 compatible = "arm,gic-v3-its";
106 msi-controller;
107 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
108 };
Harry Liebel43ef4f12013-10-22 17:29:14 +0100109 };
110
111 timer {
112 compatible = "arm,armv8-timer";
Alexei Fedorovcb8fef62021-04-12 12:49:54 +0100113 interrupts = <GIC_PPI 13
114 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 14
116 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 11
118 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 10
120 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
Harry Liebel43ef4f12013-10-22 17:29:14 +0100121 clock-frequency = <100000000>;
122 };
123
124 timer@2a810000 {
125 compatible = "arm,armv7-timer-mem";
126 reg = <0x0 0x2a810000 0x0 0x10000>;
127 clock-frequency = <100000000>;
128 #address-cells = <2>;
129 #size-cells = <2>;
130 ranges;
Harry Liebelcef93392014-04-01 19:27:38 +0100131 frame@2a830000 {
132 frame-number = <1>;
133 interrupts = <0 26 4>;
134 reg = <0x0 0x2a830000 0x0 0x10000>;
Harry Liebel43ef4f12013-10-22 17:29:14 +0100135 };
136 };
137
138 pmu {
139 compatible = "arm,armv8-pmuv3";
140 interrupts = <0 60 4>,
141 <0 61 4>,
142 <0 62 4>,
143 <0 63 4>;
144 };
145
146 smb {
147 compatible = "simple-bus";
148
149 #address-cells = <2>;
150 #size-cells = <1>;
151 ranges = <0 0 0 0x08000000 0x04000000>,
152 <1 0 0 0x14000000 0x04000000>,
153 <2 0 0 0x18000000 0x04000000>,
154 <3 0 0 0x1c000000 0x04000000>,
155 <4 0 0 0x0c000000 0x04000000>,
156 <5 0 0 0x10000000 0x04000000>;
157
Balint Dobszay5ce2c322020-01-10 17:16:27 +0100158 #include "fvp-foundation-motherboard.dtsi"
Harry Liebel43ef4f12013-10-22 17:29:14 +0100159 };
160};