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Harry Liebel43ef4f12013-10-22 17:29:14 +01001/*
Achin Gupta69387312016-09-26 10:22:56 +01002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Harry Liebel43ef4f12013-10-22 17:29:14 +01003 *
Achin Gupta69387312016-09-26 10:22:56 +01004 * SPDX-License-Identifier: BSD-3-Clause
Harry Liebel43ef4f12013-10-22 17:29:14 +01005 */
6
7/dts-v1/;
8
9/memreserve/ 0x80000000 0x00010000;
10
11/ {
12};
13
14/ {
Harry Liebelcef93392014-04-01 19:27:38 +010015 model = "FVP Foundation";
Harry Liebel43ef4f12013-10-22 17:29:14 +010016 compatible = "arm,fvp-base", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen { };
22
23 aliases {
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
28 };
29
30 psci {
Soby Mathew1df077b2015-01-15 11:49:58 +000031 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
Harry Liebel43ef4f12013-10-22 17:29:14 +010032 method = "smc";
33 cpu_suspend = <0xc4000001>;
34 cpu_off = <0x84000002>;
35 cpu_on = <0xc4000003>;
Soby Mathewe0f55df2016-10-05 15:38:01 +010036 sys_poweroff = <0x84000008>;
37 sys_reset = <0x84000009>;
Harry Liebel43ef4f12013-10-22 17:29:14 +010038 };
39
40 cpus {
41 #address-cells = <2>;
42 #size-cells = <0>;
43
Achin Gupta5ab4fe42014-08-20 17:33:09 +010044 cpu-map {
45 cluster0 {
46 core0 {
47 cpu = <&CPU0>;
48 };
49 core1 {
50 cpu = <&CPU1>;
51 };
52 core2 {
53 cpu = <&CPU2>;
54 };
55 core3 {
56 cpu = <&CPU3>;
57 };
58 };
59 };
60
61 idle-states {
62 entry-method = "arm,psci";
63
64 CPU_SLEEP_0: cpu-sleep-0 {
65 compatible = "arm,idle-state";
Juan Castillo3414f542015-04-16 14:17:49 +010066 local-timer-stop;
67 arm,psci-suspend-param = <0x0010000>;
Achin Gupta5ab4fe42014-08-20 17:33:09 +010068 entry-latency-us = <40>;
69 exit-latency-us = <100>;
70 min-residency-us = <150>;
71 };
72
73 CLUSTER_SLEEP_0: cluster-sleep-0 {
74 compatible = "arm,idle-state";
Juan Castillo3414f542015-04-16 14:17:49 +010075 local-timer-stop;
76 arm,psci-suspend-param = <0x1010000>;
Achin Gupta5ab4fe42014-08-20 17:33:09 +010077 entry-latency-us = <500>;
78 exit-latency-us = <1000>;
79 min-residency-us = <2500>;
80 };
81 };
82
83 CPU0:cpu@0 {
Harry Liebel43ef4f12013-10-22 17:29:14 +010084 device_type = "cpu";
85 compatible = "arm,armv8";
86 reg = <0x0 0x0>;
87 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +010088 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +000089 next-level-cache = <&L2_0>;
Harry Liebel43ef4f12013-10-22 17:29:14 +010090 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +010091
92 CPU1:cpu@1 {
Harry Liebel43ef4f12013-10-22 17:29:14 +010093 device_type = "cpu";
94 compatible = "arm,armv8";
95 reg = <0x0 0x1>;
96 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +010097 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +000098 next-level-cache = <&L2_0>;
Harry Liebel43ef4f12013-10-22 17:29:14 +010099 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100100
101 CPU2:cpu@2 {
Harry Liebel43ef4f12013-10-22 17:29:14 +0100102 device_type = "cpu";
103 compatible = "arm,armv8";
104 reg = <0x0 0x2>;
105 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100106 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000107 next-level-cache = <&L2_0>;
Harry Liebel43ef4f12013-10-22 17:29:14 +0100108 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100109
110 CPU3:cpu@3 {
Harry Liebel43ef4f12013-10-22 17:29:14 +0100111 device_type = "cpu";
112 compatible = "arm,armv8";
113 reg = <0x0 0x3>;
114 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100115 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000116 next-level-cache = <&L2_0>;
117 };
118
119 L2_0: l2-cache0 {
120 compatible = "cache";
Harry Liebel43ef4f12013-10-22 17:29:14 +0100121 };
122 };
123
124 memory@80000000 {
125 device_type = "memory";
Juan Castillo7055ca42014-05-16 15:33:15 +0100126 reg = <0x00000000 0x80000000 0 0x7F000000>,
Harry Liebel43ef4f12013-10-22 17:29:14 +0100127 <0x00000008 0x80000000 0 0x80000000>;
128 };
129
Harry Liebel34988592013-11-11 13:24:47 +0000130 gic: interrupt-controller@2f000000 {
Harry Liebel43ef4f12013-10-22 17:29:14 +0100131 compatible = "arm,gic-v3";
132 #interrupt-cells = <3>;
Harry Liebel34988592013-11-11 13:24:47 +0000133 #address-cells = <2>;
134 #size-cells = <2>;
135 ranges;
Harry Liebel43ef4f12013-10-22 17:29:14 +0100136 interrupt-controller;
137 reg = <0x0 0x2f000000 0 0x10000>, // GICD
138 <0x0 0x2f100000 0 0x200000>, // GICR
139 <0x0 0x2c000000 0 0x2000>, // GICC
140 <0x0 0x2c010000 0 0x2000>, // GICH
Harry Liebel34988592013-11-11 13:24:47 +0000141 <0x0 0x2c02f000 0 0x2000>; // GICV
Harry Liebel43ef4f12013-10-22 17:29:14 +0100142 interrupts = <1 9 4>;
Harry Liebel34988592013-11-11 13:24:47 +0000143
144 its: its@2f020000 {
145 compatible = "arm,gic-v3-its";
146 msi-controller;
147 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
148 };
Harry Liebel43ef4f12013-10-22 17:29:14 +0100149 };
150
151 timer {
152 compatible = "arm,armv8-timer";
153 interrupts = <1 13 0xff01>,
154 <1 14 0xff01>,
155 <1 11 0xff01>,
156 <1 10 0xff01>;
157 clock-frequency = <100000000>;
158 };
159
160 timer@2a810000 {
161 compatible = "arm,armv7-timer-mem";
162 reg = <0x0 0x2a810000 0x0 0x10000>;
163 clock-frequency = <100000000>;
164 #address-cells = <2>;
165 #size-cells = <2>;
166 ranges;
Harry Liebelcef93392014-04-01 19:27:38 +0100167 frame@2a830000 {
168 frame-number = <1>;
169 interrupts = <0 26 4>;
170 reg = <0x0 0x2a830000 0x0 0x10000>;
Harry Liebel43ef4f12013-10-22 17:29:14 +0100171 };
172 };
173
174 pmu {
175 compatible = "arm,armv8-pmuv3";
176 interrupts = <0 60 4>,
177 <0 61 4>,
178 <0 62 4>,
179 <0 63 4>;
180 };
181
182 smb {
183 compatible = "simple-bus";
184
185 #address-cells = <2>;
186 #size-cells = <1>;
187 ranges = <0 0 0 0x08000000 0x04000000>,
188 <1 0 0 0x14000000 0x04000000>,
189 <2 0 0 0x18000000 0x04000000>,
190 <3 0 0 0x1c000000 0x04000000>,
191 <4 0 0 0x0c000000 0x04000000>,
192 <5 0 0 0x10000000 0x04000000>;
193
Soby Mathewe0f55df2016-10-05 15:38:01 +0100194 /include/ "fvp-foundation-motherboard.dtsi"
Harry Liebel43ef4f12013-10-22 17:29:14 +0100195 };
196};