blob: fb90aa060d47319df1c34a246edf19dbb101366c [file] [log] [blame]
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
Tanmay Shahfdae9e82022-08-26 15:06:00 -07003 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05305 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef VERSAL_DEF_H
10#define VERSAL_DEF_H
11
Manish V Badarkhe55861512020-03-27 13:25:51 +000012#include <plat/arm/common/smccc_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <plat/common/common_def.h>
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053014
Tanmay Shahfdae9e82022-08-26 15:06:00 -070015/* number of interrupt handlers. increase as required */
16#define MAX_INTR_EL3 2
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053017/* List all consoles */
18#define VERSAL_CONSOLE_ID_pl011 1
19#define VERSAL_CONSOLE_ID_pl011_0 1
20#define VERSAL_CONSOLE_ID_pl011_1 2
21#define VERSAL_CONSOLE_ID_dcc 3
22
23#define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
24
25/* List all supported platforms */
26#define VERSAL_PLATFORM_ID_versal_virt 1
Venkatesh Yadav Abbarapu9c3b77b2022-04-13 09:04:53 +053027#define VERSAL_PLATFORM_ID_spp_itr6 2
28#define VERSAL_PLATFORM_ID_emu_itr6 3
Siva Durga Prasad Paladugu2f4cc712019-05-03 16:35:25 +053029#define VERSAL_PLATFORM_ID_silicon 4
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053030
31#define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM)
32
33/* Firmware Image Package */
34#define VERSAL_PRIMARY_CPU 0
35
36/*******************************************************************************
37 * memory map related constants
38 ******************************************************************************/
39#define DEVICE0_BASE 0xFF000000
40#define DEVICE0_SIZE 0x00E00000
41#define DEVICE1_BASE 0xF9000000
42#define DEVICE1_SIZE 0x00800000
43
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053044/*******************************************************************************
45 * IRQ constants
46 ******************************************************************************/
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -070047#define VERSAL_IRQ_SEC_PHY_TIMER U(29)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053048
49/*******************************************************************************
Tejas Patel54d13192019-02-27 18:44:55 +053050 * CCI-400 related constants
51 ******************************************************************************/
52#define PLAT_ARM_CCI_BASE 0xFD000000
Michal Simek467e16e2023-04-14 08:39:49 +020053#define PLAT_ARM_CCI_SIZE 0x00100000
Tejas Patel54d13192019-02-27 18:44:55 +053054#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
55#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5
56
57/*******************************************************************************
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053058 * UART related constants
59 ******************************************************************************/
60#define VERSAL_UART0_BASE 0xFF000000
61#define VERSAL_UART1_BASE 0xFF010000
62
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070063#if VERSAL_CONSOLE_IS(pl011) || VERSAL_CONSOLE_IS(dcc)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053064# define VERSAL_UART_BASE VERSAL_UART0_BASE
65#elif VERSAL_CONSOLE_IS(pl011_1)
66# define VERSAL_UART_BASE VERSAL_UART1_BASE
67#else
68# error "invalid VERSAL_CONSOLE"
69#endif
70
71#define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE
72#define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK
73#define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE
74
75/*******************************************************************************
76 * Platform related constants
77 ******************************************************************************/
78#if VERSAL_PLATFORM_IS(versal_virt)
79# define PLATFORM_NAME "Versal Virt"
80# define VERSAL_UART_CLOCK 25000000
81# define VERSAL_UART_BAUDRATE 115200
Siva Durga Prasad Paladugu10161e52019-04-27 11:23:20 +053082# define VERSAL_CPU_CLOCK 2720000
Siva Durga Prasad Paladugu2f4cc712019-05-03 16:35:25 +053083#elif VERSAL_PLATFORM_IS(silicon)
84# define PLATFORM_NAME "Versal Silicon"
85# define VERSAL_UART_CLOCK 100000000
86# define VERSAL_UART_BAUDRATE 115200
87# define VERSAL_CPU_CLOCK 100000000
Venkatesh Yadav Abbarapu9c3b77b2022-04-13 09:04:53 +053088#elif VERSAL_PLATFORM_IS(spp_itr6)
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +053089# define PLATFORM_NAME "SPP ITR6"
90# define VERSAL_UART_CLOCK 25000000
91# define VERSAL_UART_BAUDRATE 115200
92# define VERSAL_CPU_CLOCK 2720000
Venkatesh Yadav Abbarapu9c3b77b2022-04-13 09:04:53 +053093#elif VERSAL_PLATFORM_IS(emu_itr6)
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +053094# define PLATFORM_NAME "EMU ITR6"
95# define VERSAL_UART_CLOCK 212000
96# define VERSAL_UART_BAUDRATE 9600
97# define VERSAL_CPU_CLOCK 212000
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053098#endif
99
100/* Access control register defines */
101#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
102#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
103
104/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
105#define CRF_BASE 0xFD1A0000
106#define CRF_SIZE 0x00600000
107
108/* CRF registers and bitfields */
109#define CRF_RST_APU (CRF_BASE + 0X00000300)
110
111#define CRF_RST_APU_ACPU_RESET (1 << 0)
112#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10)
113
114/* APU registers and bitfields */
Abhyuday Godhasaraedc38ae2021-08-04 23:58:46 -0700115#define FPD_APU_BASE 0xFD5C0000U
116#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U)
117#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U)
118#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U)
119#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530120
Abhyuday Godhasaraedc38ae2021-08-04 23:58:46 -0700121#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U
122#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U
123#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530124
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700125/* PMC registers and bitfields */
Abhyuday Godhasaraedc38ae2021-08-04 23:58:46 -0700126#define PMC_GLOBAL_BASE 0xF1110000U
127#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U)
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700128
Tejas Patel354fe572018-12-14 00:55:37 -0800129/* IPI registers and bitfields */
Michal Simek32e44682023-02-09 13:33:43 +0100130#define PMC_REG_BASE U(0xFF320000)
131#define PMC_IPI_TRIG_BIT (1U << 1U)
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700132#define IPI0_REG_BASE U(0xFF330000)
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700133#define IPI0_TRIG_BIT (1U << 2U)
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700134#define IPI1_REG_BASE U(0xFF340000)
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700135#define IPI1_TRIG_BIT (1U << 3U)
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700136#define IPI2_REG_BASE U(0xFF350000)
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700137#define IPI2_TRIG_BIT (1U << 4U)
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700138#define IPI3_REG_BASE U(0xFF360000)
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700139#define IPI3_TRIG_BIT (1U << 5U)
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700140#define IPI4_REG_BASE U(0xFF370000)
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700141#define IPI4_TRIG_BIT (1U << 5U)
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700142#define IPI5_REG_BASE U(0xFF380000)
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700143#define IPI5_TRIG_BIT (1U << 6U)
Tejas Patel354fe572018-12-14 00:55:37 -0800144
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530145#endif /* VERSAL_DEF_H */