fix(plat/xilinx/versal): resolve misra R7.2
MISRA Violation: MISRA-C:2012 R.7.2
- A "u" or "U" suffix shall be applied to all integer constants that are
represented in an unsigned type
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iaf6db75e42913ddceccb803426287d0c47d7f31d
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index e8f9a82..3319ac2 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -127,18 +127,18 @@
#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U)
/* IPI registers and bitfields */
-#define IPI0_REG_BASE 0xFF330000
+#define IPI0_REG_BASE U(0xFF330000)
#define IPI0_TRIG_BIT (1 << 2)
#define PMC_IPI_TRIG_BIT (1 << 1)
-#define IPI1_REG_BASE 0xFF340000
+#define IPI1_REG_BASE U(0xFF340000)
#define IPI1_TRIG_BIT (1 << 3)
-#define IPI2_REG_BASE 0xFF350000
+#define IPI2_REG_BASE U(0xFF350000)
#define IPI2_TRIG_BIT (1 << 4)
-#define IPI3_REG_BASE 0xFF360000
+#define IPI3_REG_BASE U(0xFF360000)
#define IPI3_TRIG_BIT (1 << 5)
-#define IPI4_REG_BASE 0xFF370000
+#define IPI4_REG_BASE U(0xFF370000)
#define IPI4_TRIG_BIT (1 << 5)
-#define IPI5_REG_BASE 0xFF380000
+#define IPI5_REG_BASE U(0xFF380000)
#define IPI5_TRIG_BIT (1 << 6)
#endif /* VERSAL_DEF_H */