commit 17a12ced7ef8cecc61f53f664e04e86d0087dd0b
author Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Fri Nov 27 08:42:14 2020 -0700
committer Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Wed Mar 31 22:00:21 2021 -0600
tree 2c0a92c425925f37d38e2a8f2f693f778f186032
parent 34fbf1fcd3cfcd13dd4b1980aec6e08a6e5d40d1

plat:xilinx:versal: Add JTAG DCC support

As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I77994ce387caf0d695986df3d01d414a920978d0

plat/xilinx/versal/include/versal_def.h

diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index 810e5d8..001fb04 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -67,7 +67,7 @@
 #define VERSAL_UART0_BASE		0xFF000000
 #define VERSAL_UART1_BASE		0xFF010000
 
-#if VERSAL_CONSOLE_IS(pl011)
+#if VERSAL_CONSOLE_IS(pl011) || VERSAL_CONSOLE_IS(dcc)
 # define VERSAL_UART_BASE	VERSAL_UART0_BASE
 #elif VERSAL_CONSOLE_IS(pl011_1)
 # define VERSAL_UART_BASE	VERSAL_UART1_BASE