blob: 337bad9fc438a5d6187a52c7776faf66b7419c37 [file] [log] [blame]
Etienne Carrierea1249e02017-11-05 22:56:19 +01001/*
Govindraj Rajaeee28e72023-08-01 15:52:40 -05002 * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
Etienne Carrierea1249e02017-11-05 22:56:19 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef CORTEX_A9_H
8#define CORTEX_A9_H
Etienne Carrierea1249e02017-11-05 22:56:19 +01009
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000010#include <lib/utils_def.h>
11
Etienne Carrierea1249e02017-11-05 22:56:19 +010012/*******************************************************************************
13 * Cortex-A9 midr with version/revision set to 0
14 ******************************************************************************/
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000015#define CORTEX_A9_MIDR U(0x410FC090)
Etienne Carrierea1249e02017-11-05 22:56:19 +010016
17/*******************************************************************************
18 * CPU Auxiliary Control register specific definitions.
19 ******************************************************************************/
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000020#define CORTEX_A9_ACTLR_SMP_BIT (U(1) << 6)
21#define CORTEX_A9_ACTLR_FLZW_BIT (U(1) << 3)
Etienne Carrierea1249e02017-11-05 22:56:19 +010022
23/*******************************************************************************
24 * CPU Power Control Register
25 ******************************************************************************/
26#define PCR p15, 0, c15, c0, 0
27
Julius Werner53456fc2019-07-09 13:49:11 -070028#ifndef __ASSEMBLER__
Etienne Carrierea1249e02017-11-05 22:56:19 +010029#include <arch_helpers.h>
30DEFINE_COPROCR_RW_FUNCS(pcr, PCR)
31#endif
32
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000033#endif /* CORTEX_A9_H */