| Etienne Carriere | a1249e0 | 2017-11-05 22:56:19 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __CORTEX_A9_H__ |
| 8 | #define __CORTEX_A9_H__ |
| 9 | |
| 10 | /******************************************************************************* |
| 11 | * Cortex-A9 midr with version/revision set to 0 |
| 12 | ******************************************************************************/ |
| 13 | #define CORTEX_A9_MIDR 0x410FC090 |
| 14 | |
| 15 | /******************************************************************************* |
| 16 | * CPU Auxiliary Control register specific definitions. |
| 17 | ******************************************************************************/ |
| 18 | #define CORTEX_A9_ACTLR_SMP_BIT (1 << 6) |
| 19 | #define CORTEX_A9_ACTLR_FLZW_BIT (1 << 3) |
| 20 | |
| 21 | /******************************************************************************* |
| 22 | * CPU Power Control Register |
| 23 | ******************************************************************************/ |
| 24 | #define PCR p15, 0, c15, c0, 0 |
| 25 | |
| 26 | #ifndef __ASSEMBLY__ |
| 27 | #include <arch_helpers.h> |
| 28 | DEFINE_COPROCR_RW_FUNCS(pcr, PCR) |
| 29 | #endif |
| 30 | |
| 31 | #endif /* __CORTEX_A9_H__ */ |