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git01.mediatek.com / filogic / atf / c6a11f687ddeed5c8fb91406db7f2a1ef52fc250 / . / plat / nvidia / tegra / include / t210 / tegra_def.h
blob: efa2d50109d3609cd68d9b3adfd31e4930f10199 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]1/*
Steven Kao4d160ac2016-12-23 16:05:13 +0800[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]5 */
6
7#ifndef __TEGRA_DEF_H__
8#define __TEGRA_DEF_H__
9
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]10/*******************************************************************************
Varun Wadekar81b13832015-07-03 16:31:28 +0530[diff] [blame]11 * Power down state IDs
12 ******************************************************************************/
13#define PSTATE_ID_CORE_POWERDN 7
14#define PSTATE_ID_CLUSTER_IDLE 16
15#define PSTATE_ID_CLUSTER_POWERDN 17
16#define PSTATE_ID_SOC_POWERDN 27
17
18/*******************************************************************************
19 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
20 * call as the `state-id` field in the 'power state' parameter.
21 ******************************************************************************/
22#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN
23
24/*******************************************************************************
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]25 * Platform power states (used by PSCI framework)
26 *
27 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
28 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
29 ******************************************************************************/
30#define PLAT_MAX_RET_STATE 1
31#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
32
33/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]34 * GIC memory map
35 ******************************************************************************/
36#define TEGRA_GICD_BASE 0x50041000
37#define TEGRA_GICC_BASE 0x50042000
38
39/*******************************************************************************
Varun Wadekarbc787442015-07-27 13:00:50 +0530[diff] [blame]40 * Tegra Memory Select Switch Controller constants
41 ******************************************************************************/
42#define TEGRA_MSELECT_BASE 0x50060000
43
44#define MSELECT_CONFIG 0x0
45#define ENABLE_WRAP_INCR_MASTER2_BIT (1 << 29)
46#define ENABLE_WRAP_INCR_MASTER1_BIT (1 << 28)
47#define ENABLE_WRAP_INCR_MASTER0_BIT (1 << 27)
48#define UNSUPPORTED_TX_ERR_MASTER2_BIT (1 << 25)
49#define UNSUPPORTED_TX_ERR_MASTER1_BIT (1 << 24)
50#define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \
51 UNSUPPORTED_TX_ERR_MASTER1_BIT)
52#define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \
53 ENABLE_WRAP_INCR_MASTER1_BIT | \
54 ENABLE_WRAP_INCR_MASTER0_BIT)
55
56/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]57 * Tegra micro-seconds timer constants
58 ******************************************************************************/
59#define TEGRA_TMRUS_BASE 0x60005010
Steven Kao4d160ac2016-12-23 16:05:13 +0800[diff] [blame]60#define TEGRA_TMRUS_SIZE 0x1000
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]61
62/*******************************************************************************
63 * Tegra Clock and Reset Controller constants
64 ******************************************************************************/
65#define TEGRA_CAR_RESET_BASE 0x60006000
66
67/*******************************************************************************
68 * Tegra Flow Controller constants
69 ******************************************************************************/
70#define TEGRA_FLOWCTRL_BASE 0x60007000
71
72/*******************************************************************************
73 * Tegra Secure Boot Controller constants
74 ******************************************************************************/
75#define TEGRA_SB_BASE 0x6000C200
76
77/*******************************************************************************
78 * Tegra Exception Vectors constants
79 ******************************************************************************/
80#define TEGRA_EVP_BASE 0x6000F000
81
82/*******************************************************************************
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]83 * Tegra Miscellaneous register constants
84 ******************************************************************************/
85#define TEGRA_MISC_BASE 0x70000000
86#define HARDWARE_REVISION_OFFSET 0x804
87
88/*******************************************************************************
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]89 * Tegra UART controller base addresses
90 ******************************************************************************/
91#define TEGRA_UARTA_BASE 0x70006000
92#define TEGRA_UARTB_BASE 0x70006040
93#define TEGRA_UARTC_BASE 0x70006200
94#define TEGRA_UARTD_BASE 0x70006300
95#define TEGRA_UARTE_BASE 0x70006400
96
97/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]98 * Tegra Power Mgmt Controller constants
99 ******************************************************************************/
100#define TEGRA_PMC_BASE 0x7000E400
101
102/*******************************************************************************
103 * Tegra Memory Controller constants
104 ******************************************************************************/
105#define TEGRA_MC_BASE 0x70019000
106
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]107/* TZDRAM carveout configuration registers */
108#define MC_SECURITY_CFG0_0 0x70
109#define MC_SECURITY_CFG1_0 0x74
110#define MC_SECURITY_CFG3_0 0x9BC
111
112/* Video Memory carveout configuration registers */
113#define MC_VIDEO_PROTECT_BASE_HI 0x978
114#define MC_VIDEO_PROTECT_BASE_LO 0x648
115#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
116
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]117/*******************************************************************************
118 * Tegra TZRAM constants
119 ******************************************************************************/
120#define TEGRA_TZRAM_BASE 0x7C010000
121#define TEGRA_TZRAM_SIZE 0x10000
122
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]123#endif /* __TEGRA_DEF_H__ */