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Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Firmware Design
2===============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Dan Handley610e7e12018-03-01 18:44:00 +00004Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot
Paul Beesleyf8640672019-04-12 14:19:42 +01005Requirements (TBBR) Platform Design Document (PDD) for Arm reference
6platforms.
7
8The TBB sequence starts when the platform is powered on and runs up
Douglas Raillardd7c21b72017-06-28 15:23:03 +01009to the stage where it hands-off control to firmware running in the normal
10world in DRAM. This is the cold boot path.
11
Paul Beesleyf8640672019-04-12 14:19:42 +010012TF-A also implements the `Power State Coordination Interface PDD`_ as a
Dan Handley610e7e12018-03-01 18:44:00 +000013runtime service. PSCI is the interface from normal world software to firmware
14implementing power management use-cases (for example, secondary CPU boot,
15hotplug and idle). Normal world software can access TF-A runtime services via
16the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be
Paul Beesleyf8640672019-04-12 14:19:42 +010017used as mandated by the SMC Calling Convention (`SMCCC`_).
Douglas Raillardd7c21b72017-06-28 15:23:03 +010018
Dan Handley610e7e12018-03-01 18:44:00 +000019TF-A implements a framework for configuring and managing interrupts generated
20in either security state. The details of the interrupt management framework
Paul Beesleyf8640672019-04-12 14:19:42 +010021and its design can be found in :ref:`Interrupt Management Framework`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022
Dan Handley610e7e12018-03-01 18:44:00 +000023TF-A also implements a library for setting up and managing the translation
Paul Beesleyf8640672019-04-12 14:19:42 +010024tables. The details of this library can be found in
25:ref:`Translation (XLAT) Tables Library`.
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010026
Dan Handley610e7e12018-03-01 18:44:00 +000027TF-A can be built to support either AArch64 or AArch32 execution state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010028
29Cold boot
30---------
31
32The cold boot path starts when the platform is physically turned on. If
33``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the
34primary CPU, and the remaining CPUs are considered secondary CPUs. The primary
35CPU is chosen through platform-specific means. The cold boot path is mainly
36executed by the primary CPU, other than essential CPU initialization executed by
37all CPUs. The secondary CPUs are kept in a safe platform-specific state until
38the primary CPU has performed enough initialization to boot them.
39
Paul Beesleyf8640672019-04-12 14:19:42 +010040Refer to the :ref:`CPU Reset` for more information on the effect of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010041``COLD_BOOT_SINGLE_CPU`` platform build option.
42
Dan Handley610e7e12018-03-01 18:44:00 +000043The cold boot path in this implementation of TF-A depends on the execution
44state. For AArch64, it is divided into five steps (in order of execution):
Douglas Raillardd7c21b72017-06-28 15:23:03 +010045
46- Boot Loader stage 1 (BL1) *AP Trusted ROM*
47- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
48- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software*
49- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional)
50- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
51
52For AArch32, it is divided into four steps (in order of execution):
53
54- Boot Loader stage 1 (BL1) *AP Trusted ROM*
55- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
56- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software*
57- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
58
Dan Handley610e7e12018-03-01 18:44:00 +000059Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a
Douglas Raillardd7c21b72017-06-28 15:23:03 +010060combination of the following types of memory regions. Each bootloader stage uses
61one or more of these memory regions.
62
63- Regions accessible from both non-secure and secure states. For example,
64 non-trusted SRAM, ROM and DRAM.
65- Regions accessible from only the secure state. For example, trusted SRAM and
66 ROM. The FVPs also implement the trusted DRAM which is statically
67 configured. Additionally, the Base FVPs and Juno development platform
68 configure the TrustZone Controller (TZC) to create a region in the DRAM
69 which is accessible only from the secure state.
70
71The sections below provide the following details:
72
Soby Mathewb1bf0442018-02-16 14:52:52 +000073- dynamic configuration of Boot Loader stages
Douglas Raillardd7c21b72017-06-28 15:23:03 +010074- initialization and execution of the first three stages during cold boot
75- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for
76 AArch32) entrypoint requirements for use by alternative Trusted Boot
77 Firmware in place of the provided BL1 and BL2
78
Soby Mathewb1bf0442018-02-16 14:52:52 +000079Dynamic Configuration during cold boot
80~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
81
82Each of the Boot Loader stages may be dynamically configured if required by the
83platform. The Boot Loader stage may optionally specify a firmware
84configuration file and/or hardware configuration file as listed below:
85
86- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader
87 stages and also by the Normal World Rich OS.
88- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1
89 and BL2.
90- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31.
91- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS
92 (BL32).
93- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted
94 firmware (BL33).
95
96The Arm development platforms use the Flattened Device Tree format for the
97dynamic configuration files.
98
99Each Boot Loader stage can pass up to 4 arguments via registers to the next
100stage. BL2 passes the list of the next images to execute to the *EL3 Runtime
101Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other
102arguments are platform defined. The Arm development platforms use the following
103convention:
104
105- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This
106 structure contains the memory layout available to BL2.
107- When dynamic configuration files are present, the firmware configuration for
108 the next Boot Loader stage is populated in the first available argument and
109 the generic hardware configuration is passed the next available argument.
110 For example,
111
112 - If TB_FW_CONFIG is loaded by BL1, then its address is passed in ``arg0``
113 to BL2.
114 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to
115 BL2. Note, ``arg1`` is already used for meminfo_t.
116 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1``
117 to BL31. Note, ``arg0`` is used to pass the list of executable images.
118 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is
119 passed in ``arg2`` to BL31.
120 - For other BL3x images, if the firmware configuration file is loaded by
121 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded
122 then its address is passed in ``arg1``.
123
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100124BL1
125~~~
126
127This stage begins execution from the platform's reset vector at EL3. The reset
128address is platform dependent but it is usually located in a Trusted ROM area.
129The BL1 data section is copied to trusted SRAM at runtime.
130
Dan Handley610e7e12018-03-01 18:44:00 +0000131On the Arm development platforms, BL1 code starts execution from the reset
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100132vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied
133to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
134
135The functionality implemented by this stage is as follows.
136
137Determination of boot path
138^^^^^^^^^^^^^^^^^^^^^^^^^^
139
140Whenever a CPU is released from reset, BL1 needs to distinguish between a warm
141boot and a cold boot. This is done using platform-specific mechanisms (see the
Paul Beesleyf8640672019-04-12 14:19:42 +0100142``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case
143of a warm boot, a CPU is expected to continue execution from a separate
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100144entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe
145platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in
Paul Beesleyf8640672019-04-12 14:19:42 +0100146the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot
147path as described in the following sections.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100148
149This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the
Paul Beesleyf8640672019-04-12 14:19:42 +0100150:ref:`CPU Reset` for more information on the effect of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100151``PROGRAMMABLE_RESET_ADDRESS`` platform build option.
152
153Architectural initialization
154^^^^^^^^^^^^^^^^^^^^^^^^^^^^
155
156BL1 performs minimal architectural initialization as follows.
157
158- Exception vectors
159
160 BL1 sets up simple exception vectors for both synchronous and asynchronous
161 exceptions. The default behavior upon receiving an exception is to populate
162 a status code in the general purpose register ``X0/R0`` and call the
Paul Beesleyf8640672019-04-12 14:19:42 +0100163 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The
164 status code is one of:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100165
166 For AArch64:
167
168 ::
169
170 0x0 : Synchronous exception from Current EL with SP_EL0
171 0x1 : IRQ exception from Current EL with SP_EL0
172 0x2 : FIQ exception from Current EL with SP_EL0
173 0x3 : System Error exception from Current EL with SP_EL0
174 0x4 : Synchronous exception from Current EL with SP_ELx
175 0x5 : IRQ exception from Current EL with SP_ELx
176 0x6 : FIQ exception from Current EL with SP_ELx
177 0x7 : System Error exception from Current EL with SP_ELx
178 0x8 : Synchronous exception from Lower EL using aarch64
179 0x9 : IRQ exception from Lower EL using aarch64
180 0xa : FIQ exception from Lower EL using aarch64
181 0xb : System Error exception from Lower EL using aarch64
182 0xc : Synchronous exception from Lower EL using aarch32
183 0xd : IRQ exception from Lower EL using aarch32
184 0xe : FIQ exception from Lower EL using aarch32
185 0xf : System Error exception from Lower EL using aarch32
186
187 For AArch32:
188
189 ::
190
191 0x10 : User mode
192 0x11 : FIQ mode
193 0x12 : IRQ mode
194 0x13 : SVC mode
195 0x16 : Monitor mode
196 0x17 : Abort mode
197 0x1a : Hypervisor mode
198 0x1b : Undefined mode
199 0x1f : System mode
200
Dan Handley610e7e12018-03-01 18:44:00 +0000201 The ``plat_report_exception()`` implementation on the Arm FVP port programs
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100202 the Versatile Express System LED register in the following format to
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000203 indicate the occurrence of an unexpected exception:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100204
205 ::
206
207 SYS_LED[0] - Security state (Secure=0/Non-Secure=1)
208 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0)
209 For AArch32 it is always 0x0
210 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value
211 of the status code
212
213 A write to the LED register reflects in the System LEDs (S6LED0..7) in the
214 CLCD window of the FVP.
215
216 BL1 does not expect to receive any exceptions other than the SMC exception.
217 For the latter, BL1 installs a simple stub. The stub expects to receive a
218 limited set of SMC types (determined by their function IDs in the general
219 purpose register ``X0/R0``):
220
221 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control
222 to EL3 Runtime Software.
Paul Beesleyf8640672019-04-12 14:19:42 +0100223 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)`
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100224 Design Guide are supported for AArch64 only. These SMCs are currently
225 not supported when BL1 is built for AArch32.
226
227 Any other SMC leads to an assertion failure.
228
229- CPU initialization
230
231 BL1 calls the ``reset_handler()`` function which in turn calls the CPU
232 specific reset handler function (see the section: "CPU specific operations
233 framework").
234
235- Control register setup (for AArch64)
236
237 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I``
238 bit. Alignment and stack alignment checking is enabled by setting the
239 ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to
240 little-endian by clearing the ``SCTLR_EL3.EE`` bit.
241
242 - ``SCR_EL3``. The register width of the next lower exception level is set
243 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap
244 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
245 also set to disable instruction fetches from Non-secure memory when in
246 secure state.
247
248 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the
249 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by
250 clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is
251 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit.
252 Instructions that access the registers associated with Floating Point
253 and Advanced SIMD execution are configured to not trap to EL3 by
254 clearing the ``CPTR_EL3.TFP`` bit.
255
256 - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt
257 mask bit.
258
259 - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and
260 ``MDCR_EL3.TPM``, are set so that accesses to the registers they control
261 do not trap to EL3. AArch64 Secure self-hosted debug is disabled by
262 setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to
263 disable AArch32 Secure self-hosted privileged debug from S-EL1.
264
265- Control register setup (for AArch32)
266
267 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit.
268 Alignment checking is enabled by setting the ``SCTLR.A`` bit.
269 Exception endianness is set to little-endian by clearing the
270 ``SCTLR.EE`` bit.
271
272 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from
273 Non-secure memory when in secure state.
274
275 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1,
276 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality
277 is configured not to trap to undefined mode by clearing the
278 ``CPACR.TRCDIS`` bit.
279
280 - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and
281 system register access to implemented trace registers.
282
283 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point
284 functionality from all Exception levels.
285
286 - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing
287 the Asynchronous data abort interrupt mask bit.
288
289 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure
290 self-hosted privileged debug.
291
292Platform initialization
293^^^^^^^^^^^^^^^^^^^^^^^
294
Dan Handley610e7e12018-03-01 18:44:00 +0000295On Arm platforms, BL1 performs the following platform initializations:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100296
297- Enable the Trusted Watchdog.
298- Initialize the console.
299- Configure the Interconnect to enable hardware coherency.
300- Enable the MMU and map the memory it needs to access.
301- Configure any required platform storage to load the next bootloader image
302 (BL2).
Soby Mathewb1bf0442018-02-16 14:52:52 +0000303- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then
304 load it to the platform defined address and make it available to BL2 via
305 ``arg0``.
Soby Mathewd969a7e2018-06-11 16:40:36 +0100306- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U
307 and NS-BL2U firmware update images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100308
309Firmware Update detection and execution
310^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
311
312After performing platform setup, BL1 common code calls
Paul Beesleyf8640672019-04-12 14:19:42 +0100313``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is
314required or to proceed with the normal boot process. If the platform code
315returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described
316in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is
317required and execution passes to the first image in the
318:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor
319of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor
320contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the
321execution state of the next image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100322
323BL2 image load and execution
324^^^^^^^^^^^^^^^^^^^^^^^^^^^^
325
326In the normal boot flow, BL1 execution continues as follows:
327
328#. BL1 prints the following string from the primary CPU to indicate successful
329 execution of the BL1 stage:
330
331 ::
332
333 "Booting Trusted Firmware"
334
Soby Mathewb1bf0442018-02-16 14:52:52 +0000335#. BL1 loads a BL2 raw binary image from platform storage, at a
336 platform-specific base address. Prior to the load, BL1 invokes
337 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or
338 use the image information. If the BL2 image file is not present or if
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100339 there is not enough free trusted SRAM the following error message is
340 printed:
341
342 ::
343
344 "Failed to load BL2 firmware."
345
Soby Mathewb1bf0442018-02-16 14:52:52 +0000346#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended
347 for platforms to take further action after image load. This function must
348 populate the necessary arguments for BL2, which may also include the memory
349 layout. Further description of the memory layout can be found later
350 in this document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100351
352#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at
353 Secure SVC mode (for AArch32), starting from its load address.
354
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100355BL2
356~~~
357
358BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure
359SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific
360base address (more information can be found later in this document).
361The functionality implemented by BL2 is as follows.
362
363Architectural initialization
364^^^^^^^^^^^^^^^^^^^^^^^^^^^^
365
366For AArch64, BL2 performs the minimal architectural initialization required
Dan Handley610e7e12018-03-01 18:44:00 +0000367for subsequent stages of TF-A and normal world software. EL1 and EL0 are given
368access to Floating Point and Advanced SIMD registers by clearing the
369``CPACR.FPEN`` bits.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100370
371For AArch32, the minimal architectural initialization required for subsequent
Dan Handley610e7e12018-03-01 18:44:00 +0000372stages of TF-A and normal world software is taken care of in BL1 as both BL1
373and BL2 execute at PL1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100374
375Platform initialization
376^^^^^^^^^^^^^^^^^^^^^^^
377
Dan Handley610e7e12018-03-01 18:44:00 +0000378On Arm platforms, BL2 performs the following platform initializations:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100379
380- Initialize the console.
381- Configure any required platform storage to allow loading further bootloader
382 images.
383- Enable the MMU and map the memory it needs to access.
384- Perform platform security setup to allow access to controlled components.
385- Reserve some memory for passing information to the next bootloader image
386 EL3 Runtime Software and populate it.
387- Define the extents of memory available for loading each subsequent
388 bootloader image.
Soby Mathewb1bf0442018-02-16 14:52:52 +0000389- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``,
390 then parse it.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100391
392Image loading in BL2
393^^^^^^^^^^^^^^^^^^^^
394
Roberto Vargas025946a2018-09-24 17:20:48 +0100395BL2 generic code loads the images based on the list of loadable images
396provided by the platform. BL2 passes the list of executable images
397provided by the platform to the next handover BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100398
Soby Mathewb1bf0442018-02-16 14:52:52 +0000399The list of loadable images provided by the platform may also contain
400dynamic configuration files. The files are loaded and can be parsed as
401needed in the ``bl2_plat_handle_post_image_load()`` function. These
402configuration files can be passed to next Boot Loader stages as arguments
403by updating the corresponding entrypoint information in this function.
404
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100405SCP_BL2 (System Control Processor Firmware) image load
406^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100407
408Some systems have a separate System Control Processor (SCP) for power, clock,
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100409reset and system control. BL2 loads the optional SCP_BL2 image from platform
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100410storage into a platform-specific region of secure memory. The subsequent
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100411handling of SCP_BL2 is platform specific. For example, on the Juno Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100412development platform port the image is transferred into SCP's internal memory
413using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100414memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100415for BL2 execution to continue.
416
417EL3 Runtime Software image load
418^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
419
420BL2 loads the EL3 Runtime Software image from platform storage into a platform-
421specific address in trusted SRAM. If there is not enough memory to load the
Roberto Vargas025946a2018-09-24 17:20:48 +0100422image or image is missing it leads to an assertion failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100423
424AArch64 BL32 (Secure-EL1 Payload) image load
425^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
426
427BL2 loads the optional BL32 image from platform storage into a platform-
428specific region of secure memory. The image executes in the secure world. BL2
429relies on BL31 to pass control to the BL32 image, if present. Hence, BL2
430populates a platform-specific area of memory with the entrypoint/load-address
431of the BL32 image. The value of the Saved Processor Status Register (``SPSR``)
432for entry into BL32 is not determined by BL2, it is initialized by the
433Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for
434managing interaction with BL32. This information is passed to BL31.
435
436BL33 (Non-trusted Firmware) image load
437^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
438
439BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from
440platform storage into non-secure memory as defined by the platform.
441
442BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state
443initialization is complete. Hence, BL2 populates a platform-specific area of
444memory with the entrypoint and Saved Program Status Register (``SPSR``) of the
445normal world software image. The entrypoint is the load address of the BL33
446image. The ``SPSR`` is determined as specified in Section 5.13 of the
Paul Beesleyf8640672019-04-12 14:19:42 +0100447`Power State Coordination Interface PDD`_. This information is passed to the
448EL3 Runtime Software.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100449
450AArch64 BL31 (EL3 Runtime Software) execution
451^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
452
453BL2 execution continues as follows:
454
455#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the
456 BL31 entrypoint. The exception is handled by the SMC exception handler
457 installed by BL1.
458
459#. BL1 turns off the MMU and flushes the caches. It clears the
460 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency
461 and invalidates the TLBs.
462
463#. BL1 passes control to BL31 at the specified entrypoint at EL3.
464
Roberto Vargasb1584272017-11-20 13:36:10 +0000465Running BL2 at EL3 execution level
466~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
467
Dan Handley610e7e12018-03-01 18:44:00 +0000468Some platforms have a non-TF-A Boot ROM that expects the next boot stage
469to execute at EL3. On these platforms, TF-A BL1 is a waste of memory
470as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid
Roberto Vargasb1584272017-11-20 13:36:10 +0000471this waste, a special mode enables BL2 to execute at EL3, which allows
Dan Handley610e7e12018-03-01 18:44:00 +0000472a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected
Roberto Vargasb1584272017-11-20 13:36:10 +0000473when the build flag BL2_AT_EL3 is enabled. The main differences in this
474mode are:
475
476#. BL2 includes the reset code and the mailbox mechanism to differentiate
477 cold boot and warm boot. It runs at EL3 doing the arch
478 initialization required for EL3.
479
480#. BL2 does not receive the meminfo information from BL1 anymore. This
481 information can be passed by the Boot ROM or be internal to the
482 BL2 image.
483
484#. Since BL2 executes at EL3, BL2 jumps directly to the next image,
485 instead of invoking the RUN_IMAGE SMC call.
486
487
488We assume 3 different types of BootROM support on the platform:
489
490#. The Boot ROM always jumps to the same address, for both cold
491 and warm boot. In this case, we will need to keep a resident part
492 of BL2 whose memory cannot be reclaimed by any other image. The
493 linker script defines the symbols __TEXT_RESIDENT_START__ and
494 __TEXT_RESIDENT_END__ that allows the platform to configure
495 correctly the memory map.
496#. The platform has some mechanism to indicate the jump address to the
497 Boot ROM. Platform code can then program the jump address with
498 psci_warmboot_entrypoint during cold boot.
499#. The platform has some mechanism to program the reset address using
500 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then
501 program the reset address with psci_warmboot_entrypoint during
502 cold boot, bypassing the boot ROM for warm boot.
503
504In the last 2 cases, no part of BL2 needs to remain resident at
505runtime. In the first 2 cases, we expect the Boot ROM to be able to
506differentiate between warm and cold boot, to avoid loading BL2 again
507during warm boot.
508
509This functionality can be tested with FVP loading the image directly
510in memory and changing the address where the system jumps at reset.
511For example:
512
Dimitris Papastamos25836492018-06-11 11:07:58 +0100513 -C cluster0.cpu0.RVBAR=0x4022000
514 --data cluster0.cpu0=bl2.bin@0x4022000
Roberto Vargasb1584272017-11-20 13:36:10 +0000515
516With this configuration, FVP is like a platform of the first case,
517where the Boot ROM jumps always to the same address. For simplification,
518BL32 is loaded in DRAM in this case, to avoid other images reclaiming
519BL2 memory.
520
521
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100522AArch64 BL31
523~~~~~~~~~~~~
524
525The image for this stage is loaded by BL2 and BL1 passes control to BL31 at
526EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and
527loaded at a platform-specific base address (more information can be found later
528in this document). The functionality implemented by BL31 is as follows.
529
530Architectural initialization
531^^^^^^^^^^^^^^^^^^^^^^^^^^^^
532
533Currently, BL31 performs a similar architectural initialization to BL1 as
534far as system register settings are concerned. Since BL1 code resides in ROM,
535architectural initialization in BL31 allows override of any previous
536initialization done by BL1.
537
538BL31 initializes the per-CPU data framework, which provides a cache of
539frequently accessed per-CPU data optimised for fast, concurrent manipulation
540on different CPUs. This buffer includes pointers to per-CPU contexts, crash
541buffer, CPU reset and power down operations, PSCI data, platform data and so on.
542
543It then replaces the exception vectors populated by BL1 with its own. BL31
544exception vectors implement more elaborate support for handling SMCs since this
545is the only mechanism to access the runtime services implemented by BL31 (PSCI
546for example). BL31 checks each SMC for validity as specified by the
Paul Beesleyf8640672019-04-12 14:19:42 +0100547`SMC Calling Convention PDD`_ before passing control to the required SMC
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100548handler routine.
549
550BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system
551counter, which is provided by the platform.
552
553Platform initialization
554^^^^^^^^^^^^^^^^^^^^^^^
555
556BL31 performs detailed platform initialization, which enables normal world
557software to function correctly.
558
Dan Handley610e7e12018-03-01 18:44:00 +0000559On Arm platforms, this consists of the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100560
561- Initialize the console.
562- Configure the Interconnect to enable hardware coherency.
563- Enable the MMU and map the memory it needs to access.
564- Initialize the generic interrupt controller.
565- Initialize the power controller device.
566- Detect the system topology.
567
568Runtime services initialization
569^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
570
571BL31 is responsible for initializing the runtime services. One of them is PSCI.
572
573As part of the PSCI initializations, BL31 detects the system topology. It also
574initializes the data structures that implement the state machine used to track
575the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or
576``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster
577that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also
578initializes the locks that protect them. BL31 accesses the state of a CPU or
579cluster immediately after reset and before the data cache is enabled in the
580warm boot path. It is not currently possible to use 'exclusive' based spinlocks,
581therefore BL31 uses locks based on Lamport's Bakery algorithm instead.
582
583The runtime service framework and its initialization is described in more
584detail in the "EL3 runtime services framework" section below.
585
586Details about the status of the PSCI implementation are provided in the
587"Power State Coordination Interface" section below.
588
589AArch64 BL32 (Secure-EL1 Payload) image initialization
590^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
591
592If a BL32 image is present then there must be a matching Secure-EL1 Payload
593Dispatcher (SPD) service (see later for details). During initialization
594that service must register a function to carry out initialization of BL32
595once the runtime services are fully initialized. BL31 invokes such a
596registered function to initialize BL32 before running BL33. This initialization
597is not necessary for AArch32 SPs.
598
599Details on BL32 initialization and the SPD's role are described in the
600"Secure-EL1 Payloads and Dispatchers" section below.
601
602BL33 (Non-trusted Firmware) execution
603^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
604
605EL3 Runtime Software initializes the EL2 or EL1 processor context for normal-
606world cold boot, ensuring that no secure state information finds its way into
607the non-secure execution state. EL3 Runtime Software uses the entrypoint
608information provided by BL2 to jump to the Non-trusted firmware image (BL33)
609at the highest available Exception Level (EL2 if available, otherwise EL1).
610
611Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only)
612~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
613
614Some platforms have existing implementations of Trusted Boot Firmware that
Dan Handley610e7e12018-03-01 18:44:00 +0000615would like to use TF-A BL31 for the EL3 Runtime Software. To enable this
616firmware architecture it is important to provide a fully documented and stable
617interface between the Trusted Boot Firmware and BL31.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100618
619Future changes to the BL31 interface will be done in a backwards compatible
620way, and this enables these firmware components to be independently enhanced/
621updated to develop and exploit new functionality.
622
623Required CPU state when calling ``bl31_entrypoint()`` during cold boot
624^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
625
626This function must only be called by the primary CPU.
627
628On entry to this function the calling primary CPU must be executing in AArch64
629EL3, little-endian data access, and all interrupt sources masked:
630
631::
632
633 PSTATE.EL = 3
634 PSTATE.RW = 1
635 PSTATE.DAIF = 0xf
636 SCTLR_EL3.EE = 0
637
638X0 and X1 can be used to pass information from the Trusted Boot Firmware to the
639platform code in BL31:
640
641::
642
Dan Handley610e7e12018-03-01 18:44:00 +0000643 X0 : Reserved for common TF-A information
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100644 X1 : Platform specific information
645
646BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry,
647these will be zero filled prior to invoking platform setup code.
648
649Use of the X0 and X1 parameters
650'''''''''''''''''''''''''''''''
651
652The parameters are platform specific and passed from ``bl31_entrypoint()`` to
653``bl31_early_platform_setup()``. The value of these parameters is never directly
654used by the common BL31 code.
655
656The convention is that ``X0`` conveys information regarding the BL31, BL32 and
657BL33 images from the Trusted Boot firmware and ``X1`` can be used for other
Dan Handley610e7e12018-03-01 18:44:00 +0000658platform specific purpose. This convention allows platforms which use TF-A's
659BL1 and BL2 images to transfer additional platform specific information from
660Secure Boot without conflicting with future evolution of TF-A using ``X0`` to
661pass a ``bl31_params`` structure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100662
663BL31 common and SPD initialization code depends on image and entrypoint
664information about BL33 and BL32, which is provided via BL31 platform APIs.
665This information is required until the start of execution of BL33. This
666information can be provided in a platform defined manner, e.g. compiled into
667the platform code in BL31, or provided in a platform defined memory location
668by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the
669Cold boot Initialization parameters. This data may need to be cleaned out of
670the CPU caches if it is provided by an earlier boot stage and then accessed by
671BL31 platform code before the caches are enabled.
672
Dan Handley610e7e12018-03-01 18:44:00 +0000673TF-A's BL2 implementation passes a ``bl31_params`` structure in
674``X0`` and the Arm development platforms interpret this in the BL31 platform
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100675code.
676
677MMU, Data caches & Coherency
678''''''''''''''''''''''''''''
679
680BL31 does not depend on the enabled state of the MMU, data caches or
681interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled
682on entry, these should be enabled during ``bl31_plat_arch_setup()``.
683
684Data structures used in the BL31 cold boot interface
685''''''''''''''''''''''''''''''''''''''''''''''''''''
686
687These structures are designed to support compatibility and independent
688evolution of the structures and the firmware images. For example, a version of
689BL31 that can interpret the BL3x image information from different versions of
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100690BL2, a platform that uses an extended entry_point_info structure to convey
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100691additional register information to BL31, or a ELF image loader that can convey
692more details about the firmware images.
693
694To support these scenarios the structures are versioned and sized, which enables
695BL31 to detect which information is present and respond appropriately. The
696``param_header`` is defined to capture this information:
697
698.. code:: c
699
700 typedef struct param_header {
701 uint8_t type; /* type of the structure */
702 uint8_t version; /* version of this structure */
703 uint16_t size; /* size of this structure in bytes */
704 uint32_t attr; /* attributes: unused bits SBZ */
705 } param_header_t;
706
707The structures using this format are ``entry_point_info``, ``image_info`` and
708``bl31_params``. The code that allocates and populates these structures must set
709the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined
710to simplify this action.
711
712Required CPU state for BL31 Warm boot initialization
713^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
714
Dan Handley610e7e12018-03-01 18:44:00 +0000715When requesting a CPU power-on, or suspending a running CPU, TF-A provides
716the platform power management code with a Warm boot initialization
717entry-point, to be invoked by the CPU immediately after the reset handler.
718On entry to the Warm boot initialization function the calling CPU must be in
719AArch64 EL3, little-endian data access and all interrupt sources masked:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100720
721::
722
723 PSTATE.EL = 3
724 PSTATE.RW = 1
725 PSTATE.DAIF = 0xf
726 SCTLR_EL3.EE = 0
727
728The PSCI implementation will initialize the processor state and ensure that the
729platform power management code is then invoked as required to initialize all
730necessary system, cluster and CPU resources.
731
732AArch32 EL3 Runtime Software entrypoint interface
733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
734
735To enable this firmware architecture it is important to provide a fully
736documented and stable interface between the Trusted Boot Firmware and the
737AArch32 EL3 Runtime Software.
738
739Future changes to the entrypoint interface will be done in a backwards
740compatible way, and this enables these firmware components to be independently
741enhanced/updated to develop and exploit new functionality.
742
743Required CPU state when entering during cold boot
744^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
745
746This function must only be called by the primary CPU.
747
748On entry to this function the calling primary CPU must be executing in AArch32
749EL3, little-endian data access, and all interrupt sources masked:
750
751::
752
753 PSTATE.AIF = 0x7
754 SCTLR.EE = 0
755
756R0 and R1 are used to pass information from the Trusted Boot Firmware to the
757platform code in AArch32 EL3 Runtime Software:
758
759::
760
Dan Handley610e7e12018-03-01 18:44:00 +0000761 R0 : Reserved for common TF-A information
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100762 R1 : Platform specific information
763
764Use of the R0 and R1 parameters
765'''''''''''''''''''''''''''''''
766
767The parameters are platform specific and the convention is that ``R0`` conveys
768information regarding the BL3x images from the Trusted Boot firmware and ``R1``
769can be used for other platform specific purpose. This convention allows
Dan Handley610e7e12018-03-01 18:44:00 +0000770platforms which use TF-A's BL1 and BL2 images to transfer additional platform
771specific information from Secure Boot without conflicting with future
772evolution of TF-A using ``R0`` to pass a ``bl_params`` structure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100773
774The AArch32 EL3 Runtime Software is responsible for entry into BL33. This
775information can be obtained in a platform defined manner, e.g. compiled into
776the AArch32 EL3 Runtime Software, or provided in a platform defined memory
777location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware
778via the Cold boot Initialization parameters. This data may need to be cleaned
779out of the CPU caches if it is provided by an earlier boot stage and then
780accessed by AArch32 EL3 Runtime Software before the caches are enabled.
781
Dan Handley610e7e12018-03-01 18:44:00 +0000782When using AArch32 EL3 Runtime Software, the Arm development platforms pass a
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100783``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime
784Software platform code.
785
786MMU, Data caches & Coherency
787''''''''''''''''''''''''''''
788
789AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU,
790data caches or interconnect coherency in its entrypoint. They must be explicitly
791enabled if required.
792
793Data structures used in cold boot interface
794'''''''''''''''''''''''''''''''''''''''''''
795
796The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead
797of ``bl31_params``. The ``bl_params`` structure is based on the convention
798described in AArch64 BL31 cold boot interface section.
799
800Required CPU state for warm boot initialization
801^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
802
803When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3
804Runtime Software must ensure execution of a warm boot initialization entrypoint.
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100805If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false,
Dan Handley610e7e12018-03-01 18:44:00 +0000806then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm
807boot entrypoint by arranging for the BL1 platform function,
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100808plat_get_my_entrypoint(), to return a non-zero value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100809
810In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian
811data access and all interrupt sources masked:
812
813::
814
815 PSTATE.AIF = 0x7
816 SCTLR.EE = 0
817
Dan Handley610e7e12018-03-01 18:44:00 +0000818The warm boot entrypoint may be implemented by using TF-A
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100819``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil
Paul Beesleyf8640672019-04-12 14:19:42 +0100820the pre-requisites mentioned in the
821:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100822
823EL3 runtime services framework
824------------------------------
825
826Software executing in the non-secure state and in the secure state at exception
827levels lower than EL3 will request runtime services using the Secure Monitor
828Call (SMC) instruction. These requests will follow the convention described in
829the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function
830identifiers to each SMC request and describes how arguments are passed and
831returned.
832
833The EL3 runtime services framework enables the development of services by
834different providers that can be easily integrated into final product firmware.
835The following sections describe the framework which facilitates the
836registration, initialization and use of runtime services in EL3 Runtime
837Software (BL31).
838
839The design of the runtime services depends heavily on the concepts and
840definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning
841Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling
842conventions. Please refer to that document for more detailed explanation of
843these terms.
844
845The following runtime services are expected to be implemented first. They have
846not all been instantiated in the current implementation.
847
848#. Standard service calls
849
850 This service is for management of the entire system. The Power State
851 Coordination Interface (`PSCI`_) is the first set of standard service calls
Dan Handley610e7e12018-03-01 18:44:00 +0000852 defined by Arm (see PSCI section later).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100853
854#. Secure-EL1 Payload Dispatcher service
855
856 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then
857 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor
858 context between the normal world (EL1/EL2) and trusted world (Secure-EL1).
859 The Secure Monitor will make these world switches in response to SMCs. The
860 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted
861 Application Call OEN ranges.
862
863 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is
864 not defined by the `SMCCC`_ or any other standard. As a result, each
865 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000866 service - within TF-A this service is referred to as the Secure-EL1 Payload
867 Dispatcher (SPD).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100868
Dan Handley610e7e12018-03-01 18:44:00 +0000869 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher
870 (TSPD). Details of SPD design and TSP/TSPD operation are described in the
871 "Secure-EL1 Payloads and Dispatchers" section below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100872
873#. CPU implementation service
874
875 This service will provide an interface to CPU implementation specific
876 services for a given platform e.g. access to processor errata workarounds.
877 This service is currently unimplemented.
878
Dan Handley610e7e12018-03-01 18:44:00 +0000879Additional services for Arm Architecture, SiP and OEM calls can be implemented.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100880Each implemented service handles a range of SMC function identifiers as
881described in the `SMCCC`_.
882
883Registration
884~~~~~~~~~~~~
885
886A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying
887the name of the service, the range of OENs covered, the type of service and
888initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``).
889This structure is allocated in a special ELF section ``rt_svc_descs``, enabling
890the framework to find all service descriptors included into BL31.
891
892The specific service for a SMC Function is selected based on the OEN and call
893type of the Function ID, and the framework uses that information in the service
894descriptor to identify the handler for the SMC Call.
895
896The service descriptors do not include information to identify the precise set
897of SMC function identifiers supported by this service implementation, the
898security state from which such calls are valid nor the capability to support
89964-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately
900to these aspects of a SMC call is the responsibility of the service
901implementation, the framework is focused on integration of services from
902different providers and minimizing the time taken by the framework before the
903service handler is invoked.
904
905Details of the parameters, requirements and behavior of the initialization and
906call handling functions are provided in the following sections.
907
908Initialization
909~~~~~~~~~~~~~~
910
911``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services
912framework running on the primary CPU during cold boot as part of the BL31
913initialization. This happens prior to initializing a Trusted OS and running
914Normal world boot firmware that might in turn use these services.
915Initialization involves validating each of the declared runtime service
916descriptors, calling the service initialization function and populating the
917index used for runtime lookup of the service.
918
919The BL31 linker script collects all of the declared service descriptors into a
920single array and defines symbols that allow the framework to locate and traverse
921the array, and determine its size.
922
923The framework does basic validation of each descriptor to halt firmware
924initialization if service declaration errors are detected. The framework does
925not check descriptors for the following error conditions, and may behave in an
926unpredictable manner under such scenarios:
927
928#. Overlapping OEN ranges
929#. Multiple descriptors for the same range of OENs and ``call_type``
930#. Incorrect range of owning entity numbers for a given ``call_type``
931
932Once validated, the service ``init()`` callback is invoked. This function carries
933out any essential EL3 initialization before servicing requests. The ``init()``
934function is only invoked on the primary CPU during cold boot. If the service
935uses per-CPU data this must either be initialized for all CPUs during this call,
936or be done lazily when a CPU first issues an SMC call to that service. If
937``init()`` returns anything other than ``0``, this is treated as an initialization
938error and the service is ignored: this does not cause the firmware to halt.
939
940The OEN and call type fields present in the SMC Function ID cover a total of
941128 distinct services, but in practice a single descriptor can cover a range of
942OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a
943service handler, the framework uses an array of 128 indices that map every
944distinct OEN/call-type combination either to one of the declared services or to
945indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is
946populated for all of the OENs covered by a service after the service ``init()``
947function has reported success. So a service that fails to initialize will never
948have it's ``handle()`` function invoked.
949
950The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC
951Function ID call type and OEN onto a specific service handler in the
952``rt_svc_descs[]`` array.
953
954|Image 1|
955
956Handling an SMC
957~~~~~~~~~~~~~~~
958
959When the EL3 runtime services framework receives a Secure Monitor Call, the SMC
960Function ID is passed in W0 from the lower exception level (as per the
961`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an
962SMC Function which indicates the SMC64 calling convention: such calls are
963ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF``
964in R0/X0.
965
966Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC
967Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The
968resulting value might indicate a service that has no handler, in this case the
969framework will also report an Unknown SMC Function ID. Otherwise, the value is
970used as a further index into the ``rt_svc_descs[]`` array to locate the required
971service and handler.
972
973The service's ``handle()`` callback is provided with five of the SMC parameters
974directly, the others are saved into memory for retrieval (if needed) by the
975handler. The handler is also provided with an opaque ``handle`` for use with the
976supporting library for parameter retrieval, setting return values and context
977manipulation; and with ``flags`` indicating the security state of the caller. The
978framework finally sets up the execution stack for the handler, and invokes the
979services ``handle()`` function.
980
981On return from the handler the result registers are populated in X0-X3 before
982restoring the stack and CPU state and returning from the original SMC.
983
Jeenu Viswambharancbb40d52017-10-18 14:30:53 +0100984Exception Handling Framework
985----------------------------
986
987Please refer to the `Exception Handling Framework`_ document.
988
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100989Power State Coordination Interface
990----------------------------------
991
992TODO: Provide design walkthrough of PSCI implementation.
993
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100994The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the
995mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100996`Power State Coordination Interface PDD`_ are implemented. The table lists
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100997the PSCI v1.1 APIs and their support in generic code.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100998
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100999An API implementation might have a dependency on platform code e.g. CPU_SUSPEND
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001000requires the platform to export a part of the implementation. Hence the level
1001of support of the mandatory APIs depends upon the support exported by the
1002platform port as well. The Juno and FVP (all variants) platforms export all the
1003required support.
1004
1005+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001006| PSCI v1.1 API | Supported | Comments |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001007+=============================+=============+===============================+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001008| ``PSCI_VERSION`` | Yes | The version returned is 1.1 |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001009+-----------------------------+-------------+-------------------------------+
1010| ``CPU_SUSPEND`` | Yes\* | |
1011+-----------------------------+-------------+-------------------------------+
1012| ``CPU_OFF`` | Yes\* | |
1013+-----------------------------+-------------+-------------------------------+
1014| ``CPU_ON`` | Yes\* | |
1015+-----------------------------+-------------+-------------------------------+
1016| ``AFFINITY_INFO`` | Yes | |
1017+-----------------------------+-------------+-------------------------------+
1018| ``MIGRATE`` | Yes\*\* | |
1019+-----------------------------+-------------+-------------------------------+
1020| ``MIGRATE_INFO_TYPE`` | Yes\*\* | |
1021+-----------------------------+-------------+-------------------------------+
1022| ``MIGRATE_INFO_CPU`` | Yes\*\* | |
1023+-----------------------------+-------------+-------------------------------+
1024| ``SYSTEM_OFF`` | Yes\* | |
1025+-----------------------------+-------------+-------------------------------+
1026| ``SYSTEM_RESET`` | Yes\* | |
1027+-----------------------------+-------------+-------------------------------+
1028| ``PSCI_FEATURES`` | Yes | |
1029+-----------------------------+-------------+-------------------------------+
1030| ``CPU_FREEZE`` | No | |
1031+-----------------------------+-------------+-------------------------------+
1032| ``CPU_DEFAULT_SUSPEND`` | No | |
1033+-----------------------------+-------------+-------------------------------+
1034| ``NODE_HW_STATE`` | Yes\* | |
1035+-----------------------------+-------------+-------------------------------+
1036| ``SYSTEM_SUSPEND`` | Yes\* | |
1037+-----------------------------+-------------+-------------------------------+
1038| ``PSCI_SET_SUSPEND_MODE`` | No | |
1039+-----------------------------+-------------+-------------------------------+
1040| ``PSCI_STAT_RESIDENCY`` | Yes\* | |
1041+-----------------------------+-------------+-------------------------------+
1042| ``PSCI_STAT_COUNT`` | Yes\* | |
1043+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001044| ``SYSTEM_RESET2`` | Yes\* | |
1045+-----------------------------+-------------+-------------------------------+
1046| ``MEM_PROTECT`` | Yes\* | |
1047+-----------------------------+-------------+-------------------------------+
1048| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | |
1049+-----------------------------+-------------+-------------------------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001050
1051\*Note : These PSCI APIs require platform power management hooks to be
1052registered with the generic PSCI code to be supported.
1053
1054\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher
1055hooks to be registered with the generic PSCI code to be supported.
1056
Dan Handley610e7e12018-03-01 18:44:00 +00001057The PSCI implementation in TF-A is a library which can be integrated with
1058AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to
1059integrating PSCI library with AArch32 EL3 Runtime Software can be found
Paul Beesleyf8640672019-04-12 14:19:42 +01001060at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
1061
1062.. _firmware_design_sel1_spd:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001063
1064Secure-EL1 Payloads and Dispatchers
1065-----------------------------------
1066
1067On a production system that includes a Trusted OS running in Secure-EL1/EL0,
1068the Trusted OS is coupled with a companion runtime service in the BL31
1069firmware. This service is responsible for the initialisation of the Trusted
1070OS and all communications with it. The Trusted OS is the BL32 stage of the
Dan Handley610e7e12018-03-01 18:44:00 +00001071boot flow in TF-A. The firmware will attempt to locate, load and execute a
1072BL32 image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001073
Dan Handley610e7e12018-03-01 18:44:00 +00001074TF-A uses a more general term for the BL32 software that runs at Secure-EL1 -
1075the *Secure-EL1 Payload* - as it is not always a Trusted OS.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001076
Dan Handley610e7e12018-03-01 18:44:00 +00001077TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload
1078Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a
1079production system using the Runtime Services Framework. On such a system, the
1080Test BL32 image and service are replaced by the Trusted OS and its dispatcher
1081service. The TF-A build system expects that the dispatcher will define the
1082build flag ``NEED_BL32`` to enable it to include the BL32 in the build either
1083as a binary or to compile from source depending on whether the ``BL32`` build
1084option is specified or not.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001085
1086The TSP runs in Secure-EL1. It is designed to demonstrate synchronous
1087communication with the normal-world software running in EL1/EL2. Communication
1088is initiated by the normal-world software
1089
1090- either directly through a Fast SMC (as defined in the `SMCCC`_)
1091
1092- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn
1093 informs the TSPD about the requested power management operation. This allows
1094 the TSP to prepare for or respond to the power state change
1095
1096The TSPD service is responsible for.
1097
1098- Initializing the TSP
1099
1100- Routing requests and responses between the secure and the non-secure
1101 states during the two types of communications just described
1102
1103Initializing a BL32 Image
1104~~~~~~~~~~~~~~~~~~~~~~~~~
1105
1106The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing
1107the BL32 image. It needs access to the information passed by BL2 to BL31 to do
1108so. This is provided by:
1109
1110.. code:: c
1111
1112 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t);
1113
1114which returns a reference to the ``entry_point_info`` structure corresponding to
1115the image which will be run in the specified security state. The SPD uses this
1116API to get entry point information for the SECURE image, BL32.
1117
1118In the absence of a BL32 image, BL31 passes control to the normal world
1119bootloader image (BL33). When the BL32 image is present, it is typical
1120that the SPD wants control to be passed to BL32 first and then later to BL33.
1121
1122To do this the SPD has to register a BL32 initialization function during
1123initialization of the SPD service. The BL32 initialization function has this
1124prototype:
1125
1126.. code:: c
1127
1128 int32_t init(void);
1129
1130and is registered using the ``bl31_register_bl32_init()`` function.
1131
Dan Handley610e7e12018-03-01 18:44:00 +00001132TF-A supports two approaches for the SPD to pass control to BL32 before
1133returning through EL3 and running the non-trusted firmware (BL33):
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001134
1135#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to
1136 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in
1137 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by
1138 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``.
1139
1140 When the BL32 has completed initialization at Secure-EL1, it returns to
1141 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On
1142 receipt of this SMC, the SPD service handler should switch the CPU context
1143 from trusted to normal world and use the ``bl31_set_next_image_type()`` and
1144 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to
1145 the normal world firmware BL33. On return from the handler the framework
1146 will exit to EL2 and run BL33.
1147
1148#. The BL32 setup function registers an initialization function using
1149 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to
1150 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32
1151 entrypoint.
Paul Beesleyba3ed402019-03-13 16:20:44 +00001152
1153 .. note::
1154 The Test SPD service included with TF-A provides one implementation
1155 of such a mechanism.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001156
1157 On completion BL32 returns control to BL31 via a SMC, and on receipt the
1158 SPD service handler invokes the synchronous call return mechanism to return
1159 to the BL32 initialization function. On return from this function,
1160 ``bl31_main()`` will set up the return to the normal world firmware BL33 and
1161 continue the boot process in the normal world.
1162
Jeenu Viswambharanb60420a2017-08-24 15:43:44 +01001163Crash Reporting in BL31
1164-----------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001165
1166BL31 implements a scheme for reporting the processor state when an unhandled
1167exception is encountered. The reporting mechanism attempts to preserve all the
1168register contents and report it via a dedicated UART (PL011 console). BL31
1169reports the general purpose, EL3, Secure EL1 and some EL2 state registers.
1170
1171A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via
1172the per-CPU pointer cache. The implementation attempts to minimise the memory
1173required for this feature. The file ``crash_reporting.S`` contains the
1174implementation for crash reporting.
1175
1176The sample crash output is shown below.
1177
1178::
1179
1180 x0 :0x000000004F00007C
1181 x1 :0x0000000007FFFFFF
1182 x2 :0x0000000004014D50
1183 x3 :0x0000000000000000
1184 x4 :0x0000000088007998
1185 x5 :0x00000000001343AC
1186 x6 :0x0000000000000016
1187 x7 :0x00000000000B8A38
1188 x8 :0x00000000001343AC
1189 x9 :0x00000000000101A8
1190 x10 :0x0000000000000002
1191 x11 :0x000000000000011C
1192 x12 :0x00000000FEFDC644
1193 x13 :0x00000000FED93FFC
1194 x14 :0x0000000000247950
1195 x15 :0x00000000000007A2
1196 x16 :0x00000000000007A4
1197 x17 :0x0000000000247950
1198 x18 :0x0000000000000000
1199 x19 :0x00000000FFFFFFFF
1200 x20 :0x0000000004014D50
1201 x21 :0x000000000400A38C
1202 x22 :0x0000000000247950
1203 x23 :0x0000000000000010
1204 x24 :0x0000000000000024
1205 x25 :0x00000000FEFDC868
1206 x26 :0x00000000FEFDC86A
1207 x27 :0x00000000019EDEDC
1208 x28 :0x000000000A7CFDAA
1209 x29 :0x0000000004010780
1210 x30 :0x000000000400F004
1211 scr_el3 :0x0000000000000D3D
1212 sctlr_el3 :0x0000000000C8181F
1213 cptr_el3 :0x0000000000000000
1214 tcr_el3 :0x0000000080803520
1215 daif :0x00000000000003C0
1216 mair_el3 :0x00000000000004FF
1217 spsr_el3 :0x00000000800003CC
1218 elr_el3 :0x000000000400C0CC
1219 ttbr0_el3 :0x00000000040172A0
1220 esr_el3 :0x0000000096000210
1221 sp_el3 :0x0000000004014D50
1222 far_el3 :0x000000004F00007C
1223 spsr_el1 :0x0000000000000000
1224 elr_el1 :0x0000000000000000
1225 spsr_abt :0x0000000000000000
1226 spsr_und :0x0000000000000000
1227 spsr_irq :0x0000000000000000
1228 spsr_fiq :0x0000000000000000
1229 sctlr_el1 :0x0000000030C81807
1230 actlr_el1 :0x0000000000000000
1231 cpacr_el1 :0x0000000000300000
1232 csselr_el1 :0x0000000000000002
1233 sp_el1 :0x0000000004028800
1234 esr_el1 :0x0000000000000000
1235 ttbr0_el1 :0x000000000402C200
1236 ttbr1_el1 :0x0000000000000000
1237 mair_el1 :0x00000000000004FF
1238 amair_el1 :0x0000000000000000
1239 tcr_el1 :0x0000000000003520
1240 tpidr_el1 :0x0000000000000000
1241 tpidr_el0 :0x0000000000000000
1242 tpidrro_el0 :0x0000000000000000
1243 dacr32_el2 :0x0000000000000000
1244 ifsr32_el2 :0x0000000000000000
1245 par_el1 :0x0000000000000000
1246 far_el1 :0x0000000000000000
1247 afsr0_el1 :0x0000000000000000
1248 afsr1_el1 :0x0000000000000000
1249 contextidr_el1 :0x0000000000000000
1250 vbar_el1 :0x0000000004027000
1251 cntp_ctl_el0 :0x0000000000000000
1252 cntp_cval_el0 :0x0000000000000000
1253 cntv_ctl_el0 :0x0000000000000000
1254 cntv_cval_el0 :0x0000000000000000
1255 cntkctl_el1 :0x0000000000000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001256 sp_el0 :0x0000000004010780
1257
1258Guidelines for Reset Handlers
1259-----------------------------
1260
Dan Handley610e7e12018-03-01 18:44:00 +00001261TF-A implements a framework that allows CPU and platform ports to perform
1262actions very early after a CPU is released from reset in both the cold and warm
1263boot paths. This is done by calling the ``reset_handler()`` function in both
1264the BL1 and BL31 images. It in turn calls the platform and CPU specific reset
1265handling functions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001266
1267Details for implementing a CPU specific reset handler can be found in
1268Section 8. Details for implementing a platform specific reset handler can be
Paul Beesleyf8640672019-04-12 14:19:42 +01001269found in the :ref:`Porting Guide` (see the ``plat_reset_handler()`` function).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001270
1271When adding functionality to a reset handler, keep in mind that if a different
1272reset handling behavior is required between the first and the subsequent
1273invocations of the reset handling code, this should be detected at runtime.
1274In other words, the reset handler should be able to detect whether an action has
1275already been performed and act as appropriate. Possible courses of actions are,
1276e.g. skip the action the second time, or undo/redo it.
1277
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001278Configuring secure interrupts
1279-----------------------------
1280
1281The GIC driver is responsible for performing initial configuration of secure
1282interrupts on the platform. To this end, the platform is expected to provide the
1283GIC driver (either GICv2 or GICv3, as selected by the platform) with the
1284interrupt configuration during the driver initialisation.
1285
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001286Secure interrupt configuration are specified in an array of secure interrupt
1287properties. In this scheme, in both GICv2 and GICv3 driver data structures, the
1288``interrupt_props`` member points to an array of interrupt properties. Each
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00001289element of the array specifies the interrupt number and its attributes
1290(priority, group, configuration). Each element of the array shall be populated
1291by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments:
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001292
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001293- 10-bit interrupt number,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001294
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001295- 8-bit interrupt priority,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001296
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001297- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``,
1298 ``INTR_TYPE_NS``),
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001299
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001300- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or
1301 ``GIC_INTR_CFG_EDGE``).
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001302
Paul Beesleyf8640672019-04-12 14:19:42 +01001303.. _firmware_design_cpu_ops_fwk:
1304
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001305CPU specific operations framework
1306---------------------------------
1307
Dan Handley610e7e12018-03-01 18:44:00 +00001308Certain aspects of the Armv8-A architecture are implementation defined,
1309that is, certain behaviours are not architecturally defined, but must be
1310defined and documented by individual processor implementations. TF-A
1311implements a framework which categorises the common implementation defined
1312behaviours and allows a processor to export its implementation of that
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001313behaviour. The categories are:
1314
1315#. Processor specific reset sequence.
1316
1317#. Processor specific power down sequences.
1318
1319#. Processor specific register dumping as a part of crash reporting.
1320
1321#. Errata status reporting.
1322
1323Each of the above categories fulfils a different requirement.
1324
1325#. allows any processor specific initialization before the caches and MMU
1326 are turned on, like implementation of errata workarounds, entry into
1327 the intra-cluster coherency domain etc.
1328
1329#. allows each processor to implement the power down sequence mandated in
1330 its Technical Reference Manual (TRM).
1331
1332#. allows a processor to provide additional information to the developer
1333 in the event of a crash, for example Cortex-A53 has registers which
1334 can expose the data cache contents.
1335
1336#. allows a processor to define a function that inspects and reports the status
1337 of all errata workarounds on that processor.
1338
1339Please note that only 2. is mandated by the TRM.
1340
1341The CPU specific operations framework scales to accommodate a large number of
1342different CPUs during power down and reset handling. The platform can specify
1343any CPU optimization it wants to enable for each CPU. It can also specify
1344the CPU errata workarounds to be applied for each CPU type during reset
1345handling by defining CPU errata compile time macros. Details on these macros
Paul Beesleyf8640672019-04-12 14:19:42 +01001346can be found in the :ref:`Arm CPU Specific Build Macros` document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001347
1348The CPU specific operations framework depends on the ``cpu_ops`` structure which
1349needs to be exported for each type of CPU in the platform. It is defined in
1350``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``,
1351``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and
1352``cpu_reg_dump()``.
1353
1354The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with
1355suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S``
1356exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform
1357configuration, these CPU specific files must be included in the build by
1358the platform makefile. The generic CPU specific operations framework code exists
1359in ``lib/cpus/aarch64/cpu_helpers.S``.
1360
1361CPU specific Reset Handling
1362~~~~~~~~~~~~~~~~~~~~~~~~~~~
1363
1364After a reset, the state of the CPU when it calls generic reset handler is:
1365MMU turned off, both instruction and data caches turned off and not part
1366of any coherency domain.
1367
1368The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow
1369the platform to perform any system initialization required and any system
1370errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads
1371the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops``
1372array and returns it. Note that only the part number and implementer fields
1373in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in
1374the returned ``cpu_ops`` is then invoked which executes the required reset
1375handling for that CPU and also any errata workarounds enabled by the platform.
1376This function must preserve the values of general purpose registers x20 to x29.
1377
1378Refer to Section "Guidelines for Reset Handlers" for general guidelines
1379regarding placement of code in a reset handler.
1380
1381CPU specific power down sequence
1382~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1383
1384During the BL31 initialization sequence, the pointer to the matching ``cpu_ops``
1385entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly
1386retrieved during power down sequences.
1387
1388Various CPU drivers register handlers to perform power down at certain power
1389levels for that specific CPU. The PSCI service, upon receiving a power down
1390request, determines the highest power level at which to execute power down
1391sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to
1392pick the right power down handler for the requested level. The function
1393retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further
1394retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the
1395requested power level is higher than what a CPU driver supports, the handler
1396registered for highest level is invoked.
1397
1398At runtime the platform hooks for power down are invoked by the PSCI service to
1399perform platform specific operations during a power down sequence, for example
1400turning off CCI coherency during a cluster power down.
1401
1402CPU specific register reporting during crash
1403~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1404
1405If the crash reporting is enabled in BL31, when a crash occurs, the crash
1406reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching
1407``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in
1408``cpu_ops`` is invoked, which then returns the CPU specific register values to
1409be reported and a pointer to the ASCII list of register names in a format
1410expected by the crash reporting framework.
1411
Paul Beesleyf8640672019-04-12 14:19:42 +01001412.. _firmware_design_cpu_errata_reporting:
1413
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001414CPU errata status reporting
1415~~~~~~~~~~~~~~~~~~~~~~~~~~~
1416
Dan Handley610e7e12018-03-01 18:44:00 +00001417Errata workarounds for CPUs supported in TF-A are applied during both cold and
1418warm boots, shortly after reset. Individual Errata workarounds are enabled as
1419build options. Some errata workarounds have potential run-time implications;
1420therefore some are enabled by default, others not. Platform ports shall
1421override build options to enable or disable errata as appropriate. The CPU
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001422drivers take care of applying errata workarounds that are enabled and applicable
Paul Beesleyf8640672019-04-12 14:19:42 +01001423to a given CPU. Refer to :ref:`arm_cpu_macros_errata_workarounds` for more
1424information.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001425
1426Functions in CPU drivers that apply errata workaround must follow the
1427conventions listed below.
1428
1429The errata workaround must be authored as two separate functions:
1430
1431- One that checks for errata. This function must determine whether that errata
1432 applies to the current CPU. Typically this involves matching the current
1433 CPUs revision and variant against a value that's known to be affected by the
1434 errata. If the function determines that the errata applies to this CPU, it
1435 must return ``ERRATA_APPLIES``; otherwise, it must return
1436 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and
1437 ``cpu_rev_var_ls`` functions may come in handy for this purpose.
1438
1439For an errata identified as ``E``, the check function must be named
1440``check_errata_E``.
1441
1442This function will be invoked at different times, both from assembly and from
1443C run time. Therefore it must follow AAPCS, and must not use stack.
1444
1445- Another one that applies the errata workaround. This function would call the
1446 check function described above, and applies errata workaround if required.
1447
1448CPU drivers that apply errata workaround can optionally implement an assembly
1449function that report the status of errata workarounds pertaining to that CPU.
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00001450For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001451macro, the errata reporting function, if it exists, must be named
1452``cpux_errata_report``. This function will always be called with MMU enabled; it
1453must follow AAPCS and may use stack.
1454
Dan Handley610e7e12018-03-01 18:44:00 +00001455In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the
1456runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata
1457status reporting function, if one exists, for that type of CPU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001458
1459To report the status of each errata workaround, the function shall use the
1460assembler macro ``report_errata``, passing it:
1461
1462- The build option that enables the errata;
1463
1464- The name of the CPU: this must be the same identifier that CPU driver
1465 registered itself with, using ``declare_cpu_ops``;
1466
1467- And the errata identifier: the identifier must match what's used in the
1468 errata's check function described above.
1469
1470The errata status reporting function will be called once per CPU type/errata
1471combination during the software's active life time.
1472
Dan Handley610e7e12018-03-01 18:44:00 +00001473It's expected that whenever an errata workaround is submitted to TF-A, the
1474errata reporting function is appropriately extended to report its status as
1475well.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001476
1477Reporting the status of errata workaround is for informational purpose only; it
1478has no functional significance.
1479
1480Memory layout of BL images
1481--------------------------
1482
1483Each bootloader image can be divided in 2 parts:
1484
1485- the static contents of the image. These are data actually stored in the
1486 binary on the disk. In the ELF terminology, they are called ``PROGBITS``
1487 sections;
1488
1489- the run-time contents of the image. These are data that don't occupy any
1490 space in the binary on the disk. The ELF binary just contains some
1491 metadata indicating where these data will be stored at run-time and the
1492 corresponding sections need to be allocated and initialized at run-time.
1493 In the ELF terminology, they are called ``NOBITS`` sections.
1494
1495All PROGBITS sections are grouped together at the beginning of the image,
Dan Handley610e7e12018-03-01 18:44:00 +00001496followed by all NOBITS sections. This is true for all TF-A images and it is
1497governed by the linker scripts. This ensures that the raw binary images are
1498as small as possible. If a NOBITS section was inserted in between PROGBITS
1499sections then the resulting binary file would contain zero bytes in place of
1500this NOBITS section, making the image unnecessarily bigger. Smaller images
1501allow faster loading from the FIP to the main memory.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001502
1503Linker scripts and symbols
1504~~~~~~~~~~~~~~~~~~~~~~~~~~
1505
1506Each bootloader stage image layout is described by its own linker script. The
1507linker scripts export some symbols into the program symbol table. Their values
Dan Handley610e7e12018-03-01 18:44:00 +00001508correspond to particular addresses. TF-A code can refer to these symbols to
1509figure out the image memory layout.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001510
Dan Handley610e7e12018-03-01 18:44:00 +00001511Linker symbols follow the following naming convention in TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001512
1513- ``__<SECTION>_START__``
1514
1515 Start address of a given section named ``<SECTION>``.
1516
1517- ``__<SECTION>_END__``
1518
1519 End address of a given section named ``<SECTION>``. If there is an alignment
1520 constraint on the section's end address then ``__<SECTION>_END__`` corresponds
1521 to the end address of the section's actual contents, rounded up to the right
1522 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the
1523 actual end address of the section's contents.
1524
1525- ``__<SECTION>_UNALIGNED_END__``
1526
1527 End address of a given section named ``<SECTION>`` without any padding or
1528 rounding up due to some alignment constraint.
1529
1530- ``__<SECTION>_SIZE__``
1531
1532 Size (in bytes) of a given section named ``<SECTION>``. If there is an
1533 alignment constraint on the section's end address then ``__<SECTION>_SIZE__``
1534 corresponds to the size of the section's actual contents, rounded up to the
1535 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__``
1536 to know the actual size of the section's contents.
1537
1538- ``__<SECTION>_UNALIGNED_SIZE__``
1539
1540 Size (in bytes) of a given section named ``<SECTION>`` without any padding or
1541 rounding up due to some alignment constraint. In other words,
1542 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``.
1543
Dan Handley610e7e12018-03-01 18:44:00 +00001544Some of the linker symbols are mandatory as TF-A code relies on them to be
1545defined. They are listed in the following subsections. Some of them must be
1546provided for each bootloader stage and some are specific to a given bootloader
1547stage.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001548
1549The linker scripts define some extra, optional symbols. They are not actually
1550used by any code but they help in understanding the bootloader images' memory
1551layout as they are easy to spot in the link map files.
1552
1553Common linker symbols
1554^^^^^^^^^^^^^^^^^^^^^
1555
1556All BL images share the following requirements:
1557
1558- The BSS section must be zero-initialised before executing any C code.
1559- The coherent memory section (if enabled) must be zero-initialised as well.
1560- The MMU setup code needs to know the extents of the coherent and read-only
1561 memory regions to set the right memory attributes. When
1562 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the
1563 read-only memory region is divided between code and data.
1564
1565The following linker symbols are defined for this purpose:
1566
1567- ``__BSS_START__``
1568- ``__BSS_SIZE__``
1569- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary.
1570- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary.
1571- ``__COHERENT_RAM_UNALIGNED_SIZE__``
1572- ``__RO_START__``
1573- ``__RO_END__``
1574- ``__TEXT_START__``
1575- ``__TEXT_END__``
1576- ``__RODATA_START__``
1577- ``__RODATA_END__``
1578
1579BL1's linker symbols
1580^^^^^^^^^^^^^^^^^^^^
1581
1582BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and
1583it is entirely executed in place but it needs some read-write memory for its
1584mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be
1585relocated from ROM to RAM before executing any C code.
1586
1587The following additional linker symbols are defined for BL1:
1588
1589- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code
1590 and ``.data`` section in ROM.
1591- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be
1592 aligned on a 16-byte boundary.
1593- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be
1594 copied over. Must be aligned on a 16-byte boundary.
1595- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM).
1596- ``__BL1_RAM_START__`` Start address of BL1 read-write data.
1597- ``__BL1_RAM_END__`` End address of BL1 read-write data.
1598
1599How to choose the right base addresses for each bootloader stage image
1600~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1601
Dan Handley610e7e12018-03-01 18:44:00 +00001602There is currently no support for dynamic image loading in TF-A. This means
1603that all bootloader images need to be linked against their ultimate runtime
1604locations and the base addresses of each image must be chosen carefully such
1605that images don't overlap each other in an undesired way. As the code grows,
1606the base addresses might need adjustments to cope with the new memory layout.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001607
1608The memory layout is completely specific to the platform and so there is no
1609general recipe for choosing the right base addresses for each bootloader image.
1610However, there are tools to aid in understanding the memory layout. These are
1611the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>``
1612being the stage bootloader. They provide a detailed view of the memory usage of
1613each image. Among other useful information, they provide the end address of
1614each image.
1615
1616- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address.
1617- ``bl2.map`` link map file provides ``__BL2_END__`` address.
1618- ``bl31.map`` link map file provides ``__BL31_END__`` address.
1619- ``bl32.map`` link map file provides ``__BL32_END__`` address.
1620
1621For each bootloader image, the platform code must provide its start address
1622as well as a limit address that it must not overstep. The latter is used in the
1623linker scripts to check that the image doesn't grow past that address. If that
1624happens, the linker will issue a message similar to the following:
1625
1626::
1627
1628 aarch64-none-elf-ld: BLx has exceeded its limit.
1629
1630Additionally, if the platform memory layout implies some image overlaying like
1631on FVP, BL31 and TSP need to know the limit address that their PROGBITS
1632sections must not overstep. The platform code must provide those.
1633
Soby Mathew97b1bff2018-09-27 16:46:41 +01001634TF-A does not provide any mechanism to verify at boot time that the memory
1635to load a new image is free to prevent overwriting a previously loaded image.
1636The platform must specify the memory available in the system for all the
1637relevant BL images to be loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001638
1639For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will
1640return the region defined by the platform where BL1 intends to load BL2. The
1641``load_image()`` function performs bounds check for the image size based on the
1642base and maximum image size provided by the platforms. Platforms must take
1643this behaviour into account when defining the base/size for each of the images.
1644
Dan Handley610e7e12018-03-01 18:44:00 +00001645Memory layout on Arm development platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001646^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1647
Dan Handley610e7e12018-03-01 18:44:00 +00001648The following list describes the memory layout on the Arm development platforms:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001649
1650- A 4KB page of shared memory is used for communication between Trusted
1651 Firmware and the platform's power controller. This is located at the base of
1652 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader
1653 images is reduced by the size of the shared memory.
1654
1655 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno,
1656 this is also used for the MHU payload when passing messages to and from the
1657 SCP.
1658
Soby Mathew492e2452018-06-06 16:03:10 +01001659- Another 4 KB page is reserved for passing memory layout between BL1 and BL2
1660 and also the dynamic firmware configurations.
1661
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001662- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On
1663 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write
1664 data are relocated to the top of Trusted SRAM at runtime.
1665
Soby Mathew492e2452018-06-06 16:03:10 +01001666- BL2 is loaded below BL1 RW
1667
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001668- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN),
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001669 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will
Soby Mathew492e2452018-06-06 16:03:10 +01001670 overwrite BL1 R/W data and BL2. This implies that BL1 global variables
1671 remain valid only until execution reaches the EL3 Runtime Software entry
1672 point during a cold boot.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001673
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001674- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory
Paul Beesleyf2ec7142019-10-04 16:17:46 +00001675 region and transferred to the SCP before being overwritten by EL3 Runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001676 Software.
1677
1678- BL32 (for AArch64) can be loaded in one of the following locations:
1679
1680 - Trusted SRAM
1681 - Trusted DRAM (FVP only)
1682 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone
1683 controller)
1684
Soby Mathew492e2452018-06-06 16:03:10 +01001685 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below
1686 BL31.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001687
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001688The location of the BL32 image will result in different memory maps. This is
1689illustrated for both FVP and Juno in the following diagrams, using the TSP as
1690an example.
1691
Paul Beesleyba3ed402019-03-13 16:20:44 +00001692.. note::
1693 Loading the BL32 image in TZC secured DRAM doesn't change the memory
1694 layout of the other images in Trusted SRAM.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001695
Sathees Balya90950092018-11-15 14:22:30 +00001696CONFIG section in memory layouts shown below contains:
1697
1698::
1699
1700 +--------------------+
1701 |bl2_mem_params_descs|
1702 |--------------------|
1703 | fw_configs |
1704 +--------------------+
1705
1706``bl2_mem_params_descs`` contains parameters passed from BL2 to next the
1707BL image during boot.
1708
1709``fw_configs`` includes soc_fw_config, tos_fw_config and tb_fw_config.
1710
Soby Mathew492e2452018-06-06 16:03:10 +01001711**FVP with TSP in Trusted SRAM with firmware configs :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001712(These diagrams only cover the AArch64 case)
1713
1714::
1715
Soby Mathew492e2452018-06-06 16:03:10 +01001716 DRAM
1717 0xffffffff +----------+
1718 : :
1719 |----------|
1720 |HW_CONFIG |
1721 0x83000000 |----------| (non-secure)
1722 | |
1723 0x80000000 +----------+
1724
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001725 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001726 0x04040000 +----------+ loaded by BL2 +----------------+
1727 | BL1 (rw) | <<<<<<<<<<<<< | |
1728 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1729 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001730 |----------| <<<<<<<<<<<<< |----------------|
1731 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001732 | | <<<<<<<<<<<<< |----------------|
1733 | | <<<<<<<<<<<<< | BL32 |
1734 0x04002000 +----------+ +----------------+
Sathees Balya90950092018-11-15 14:22:30 +00001735 | CONFIG |
Soby Mathew492e2452018-06-06 16:03:10 +01001736 0x04001000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001737 | Shared |
1738 0x04000000 +----------+
1739
1740 Trusted ROM
1741 0x04000000 +----------+
1742 | BL1 (ro) |
1743 0x00000000 +----------+
1744
Soby Mathew492e2452018-06-06 16:03:10 +01001745**FVP with TSP in Trusted DRAM with firmware configs (default option):**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001746
1747::
1748
Soby Mathewb1bf0442018-02-16 14:52:52 +00001749 DRAM
1750 0xffffffff +--------------+
1751 : :
1752 |--------------|
1753 | HW_CONFIG |
1754 0x83000000 |--------------| (non-secure)
1755 | |
1756 0x80000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001757
Soby Mathewb1bf0442018-02-16 14:52:52 +00001758 Trusted DRAM
1759 0x08000000 +--------------+
1760 | BL32 |
1761 0x06000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001762
Soby Mathewb1bf0442018-02-16 14:52:52 +00001763 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001764 0x04040000 +--------------+ loaded by BL2 +----------------+
1765 | BL1 (rw) | <<<<<<<<<<<<< | |
1766 |--------------| <<<<<<<<<<<<< | BL31 NOBITS |
1767 | BL2 | <<<<<<<<<<<<< | |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001768 |--------------| <<<<<<<<<<<<< |----------------|
1769 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001770 | | +----------------+
1771 +--------------+
Sathees Balya90950092018-11-15 14:22:30 +00001772 | CONFIG |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001773 0x04001000 +--------------+
1774 | Shared |
1775 0x04000000 +--------------+
1776
1777 Trusted ROM
1778 0x04000000 +--------------+
1779 | BL1 (ro) |
1780 0x00000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001781
Soby Mathew492e2452018-06-06 16:03:10 +01001782**FVP with TSP in TZC-Secured DRAM with firmware configs :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001783
1784::
1785
1786 DRAM
1787 0xffffffff +----------+
Soby Mathewb1bf0442018-02-16 14:52:52 +00001788 | BL32 | (secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001789 0xff000000 +----------+
1790 | |
Soby Mathew492e2452018-06-06 16:03:10 +01001791 |----------|
1792 |HW_CONFIG |
1793 0x83000000 |----------| (non-secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001794 | |
1795 0x80000000 +----------+
1796
1797 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001798 0x04040000 +----------+ loaded by BL2 +----------------+
1799 | BL1 (rw) | <<<<<<<<<<<<< | |
1800 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1801 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001802 |----------| <<<<<<<<<<<<< |----------------|
1803 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001804 | | +----------------+
1805 0x04002000 +----------+
Sathees Balya90950092018-11-15 14:22:30 +00001806 | CONFIG |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001807 0x04001000 +----------+
1808 | Shared |
1809 0x04000000 +----------+
1810
1811 Trusted ROM
1812 0x04000000 +----------+
1813 | BL1 (ro) |
1814 0x00000000 +----------+
1815
Soby Mathew492e2452018-06-06 16:03:10 +01001816**Juno with BL32 in Trusted SRAM :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001817
1818::
1819
1820 Flash0
1821 0x0C000000 +----------+
1822 : :
1823 0x0BED0000 |----------|
1824 | BL1 (ro) |
1825 0x0BEC0000 |----------|
1826 : :
1827 0x08000000 +----------+ BL31 is loaded
1828 after SCP_BL2 has
1829 Trusted SRAM been sent to SCP
Soby Mathew492e2452018-06-06 16:03:10 +01001830 0x04040000 +----------+ loaded by BL2 +----------------+
1831 | BL1 (rw) | <<<<<<<<<<<<< | |
1832 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1833 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001834 |----------| <<<<<<<<<<<<< |----------------|
1835 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001836 |----------| <<<<<<<<<<<<< |----------------|
Soby Mathew492e2452018-06-06 16:03:10 +01001837 | | <<<<<<<<<<<<< | BL32 |
1838 | | +----------------+
1839 | |
1840 0x04001000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001841 | MHU |
1842 0x04000000 +----------+
1843
Soby Mathew492e2452018-06-06 16:03:10 +01001844**Juno with BL32 in TZC-secured DRAM :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001845
1846::
1847
1848 DRAM
1849 0xFFE00000 +----------+
Soby Mathewb1bf0442018-02-16 14:52:52 +00001850 | BL32 | (secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001851 0xFF000000 |----------|
1852 | |
1853 : : (non-secure)
1854 | |
1855 0x80000000 +----------+
1856
1857 Flash0
1858 0x0C000000 +----------+
1859 : :
1860 0x0BED0000 |----------|
1861 | BL1 (ro) |
1862 0x0BEC0000 |----------|
1863 : :
1864 0x08000000 +----------+ BL31 is loaded
1865 after SCP_BL2 has
1866 Trusted SRAM been sent to SCP
Soby Mathew492e2452018-06-06 16:03:10 +01001867 0x04040000 +----------+ loaded by BL2 +----------------+
1868 | BL1 (rw) | <<<<<<<<<<<<< | |
1869 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1870 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001871 |----------| <<<<<<<<<<<<< |----------------|
1872 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001873 |----------| +----------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001874 0x04001000 +----------+
1875 | MHU |
1876 0x04000000 +----------+
1877
Sathees Balya17d8eed2019-01-30 15:56:44 +00001878Library at ROM
1879---------------
1880
Paul Beesleyf8640672019-04-12 14:19:42 +01001881Please refer to the :ref:`Library at ROM` document.
Sathees Balya17d8eed2019-01-30 15:56:44 +00001882
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001883Firmware Image Package (FIP)
1884----------------------------
1885
1886Using a Firmware Image Package (FIP) allows for packing bootloader images (and
Dan Handley610e7e12018-03-01 18:44:00 +00001887potentially other payloads) into a single archive that can be loaded by TF-A
1888from non-volatile platform storage. A driver to load images from a FIP has
1889been added to the storage layer and allows a package to be read from supported
1890platform storage. A tool to create Firmware Image Packages is also provided
1891and described below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001892
1893Firmware Image Package layout
1894~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1895
1896The FIP layout consists of a table of contents (ToC) followed by payload data.
1897The ToC itself has a header followed by one or more table entries. The ToC is
Jett Zhou75566102017-11-24 16:03:58 +08001898terminated by an end marker entry, and since the size of the ToC is 0 bytes,
1899the offset equals the total size of the FIP file. All ToC entries describe some
1900payload data that has been appended to the end of the binary package. With the
1901information provided in the ToC entry the corresponding payload data can be
1902retrieved.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001903
1904::
1905
1906 ------------------
1907 | ToC Header |
1908 |----------------|
1909 | ToC Entry 0 |
1910 |----------------|
1911 | ToC Entry 1 |
1912 |----------------|
1913 | ToC End Marker |
1914 |----------------|
1915 | |
1916 | Data 0 |
1917 | |
1918 |----------------|
1919 | |
1920 | Data 1 |
1921 | |
1922 ------------------
1923
1924The ToC header and entry formats are described in the header file
1925``include/tools_share/firmware_image_package.h``. This file is used by both the
Dan Handley610e7e12018-03-01 18:44:00 +00001926tool and TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001927
1928The ToC header has the following fields:
1929
1930::
1931
1932 `name`: The name of the ToC. This is currently used to validate the header.
1933 `serial_number`: A non-zero number provided by the creation tool
1934 `flags`: Flags associated with this data.
1935 Bits 0-31: Reserved
1936 Bits 32-47: Platform defined
1937 Bits 48-63: Reserved
1938
1939A ToC entry has the following fields:
1940
1941::
1942
1943 `uuid`: All files are referred to by a pre-defined Universally Unique
1944 IDentifier [UUID] . The UUIDs are defined in
1945 `include/tools_share/firmware_image_package.h`. The platform translates
1946 the requested image name into the corresponding UUID when accessing the
1947 package.
1948 `offset_address`: The offset address at which the corresponding payload data
1949 can be found. The offset is calculated from the ToC base address.
1950 `size`: The size of the corresponding payload data in bytes.
Etienne Carriere7421bf12017-08-23 15:43:33 +02001951 `flags`: Flags associated with this entry. None are yet defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001952
1953Firmware Image Package creation tool
1954~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1955
Dan Handley610e7e12018-03-01 18:44:00 +00001956The FIP creation tool can be used to pack specified images into a binary
1957package that can be loaded by TF-A from platform storage. The tool currently
1958only supports packing bootloader images. Additional image definitions can be
1959added to the tool as required.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001960
1961The tool can be found in ``tools/fiptool``.
1962
1963Loading from a Firmware Image Package (FIP)
1964~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1965
1966The Firmware Image Package (FIP) driver can load images from a binary package on
Dan Handley610e7e12018-03-01 18:44:00 +00001967non-volatile platform storage. For the Arm development platforms, this is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001968currently NOR FLASH.
1969
1970Bootloader images are loaded according to the platform policy as specified by
Dan Handley610e7e12018-03-01 18:44:00 +00001971the function ``plat_get_image_source()``. For the Arm development platforms, this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001972means the platform will attempt to load images from a Firmware Image Package
1973located at the start of NOR FLASH0.
1974
Dan Handley610e7e12018-03-01 18:44:00 +00001975The Arm development platforms' policy is to only allow loading of a known set of
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001976images. The platform policy can be modified to allow additional images.
1977
Dan Handley610e7e12018-03-01 18:44:00 +00001978Use of coherent memory in TF-A
1979------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001980
1981There might be loss of coherency when physical memory with mismatched
1982shareability, cacheability and memory attributes is accessed by multiple CPUs
Dan Handley610e7e12018-03-01 18:44:00 +00001983(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs
1984in TF-A during power up/down sequences when coherency, MMU and caches are
1985turned on/off incrementally.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001986
Dan Handley610e7e12018-03-01 18:44:00 +00001987TF-A defines coherent memory as a region of memory with Device nGnRE attributes
1988in the translation tables. The translation granule size in TF-A is 4KB. This
1989is the smallest possible size of the coherent memory region.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001990
1991By default, all data structures which are susceptible to accesses with
1992mismatched attributes from various CPUs are allocated in a coherent memory
Paul Beesleyf8640672019-04-12 14:19:42 +01001993region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory
1994region accesses are Outer Shareable, non-cacheable and they can be accessed with
1995the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of
1996at least an extra page of memory, TF-A is able to work around coherency issues
1997due to mismatched memory attributes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001998
1999The alternative to the above approach is to allocate the susceptible data
2000structures in Normal WriteBack WriteAllocate Inner shareable memory. This
2001approach requires the data structures to be designed so that it is possible to
2002work around the issue of mismatched memory attributes by performing software
2003cache maintenance on them.
2004
Dan Handley610e7e12018-03-01 18:44:00 +00002005Disabling the use of coherent memory in TF-A
2006~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002007
2008It might be desirable to avoid the cost of allocating coherent memory on
Dan Handley610e7e12018-03-01 18:44:00 +00002009platforms which are memory constrained. TF-A enables inclusion of coherent
2010memory in firmware images through the build flag ``USE_COHERENT_MEM``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002011This flag is enabled by default. It can be disabled to choose the second
2012approach described above.
2013
2014The below sections analyze the data structures allocated in the coherent memory
2015region and the changes required to allocate them in normal memory.
2016
2017Coherent memory usage in PSCI implementation
2018~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2019
2020The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain
2021tree information for state management of power domains. By default, this data
Dan Handley610e7e12018-03-01 18:44:00 +00002022structure is allocated in the coherent memory region in TF-A because it can be
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002023accessed by multiple CPUs, either with caches enabled or disabled.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002024
2025.. code:: c
2026
2027 typedef struct non_cpu_pwr_domain_node {
2028 /*
2029 * Index of the first CPU power domain node level 0 which has this node
2030 * as its parent.
2031 */
2032 unsigned int cpu_start_idx;
2033
2034 /*
2035 * Number of CPU power domains which are siblings of the domain indexed
2036 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
2037 * -> cpu_start_idx + ncpus' have this node as their parent.
2038 */
2039 unsigned int ncpus;
2040
2041 /*
2042 * Index of the parent power domain node.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002043 */
2044 unsigned int parent_node;
2045
2046 plat_local_state_t local_state;
2047
2048 unsigned char level;
2049
2050 /* For indexing the psci_lock array*/
2051 unsigned char lock_index;
2052 } non_cpu_pd_node_t;
2053
2054In order to move this data structure to normal memory, the use of each of its
2055fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node``
2056``level`` and ``lock_index`` are only written once during cold boot. Hence removing
2057them from coherent memory involves only doing a clean and invalidate of the
2058cache lines after these fields are written.
2059
2060The field ``local_state`` can be concurrently accessed by multiple CPUs in
2061different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002062mutual exclusion to this field and a clean and invalidate is needed after it
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002063is written.
2064
2065Bakery lock data
2066~~~~~~~~~~~~~~~~
2067
2068The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory
2069and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is
2070defined as follows:
2071
2072.. code:: c
2073
2074 typedef struct bakery_lock {
2075 /*
2076 * The lock_data is a bit-field of 2 members:
2077 * Bit[0] : choosing. This field is set when the CPU is
2078 * choosing its bakery number.
2079 * Bits[1 - 15] : number. This is the bakery number allocated.
2080 */
2081 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS];
2082 } bakery_lock_t;
2083
2084It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU
2085fields can be read by all CPUs but only written to by the owning CPU.
2086
2087Depending upon the data cache line size, the per-CPU fields of the
2088``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line.
2089These per-CPU fields can be read and written during lock contention by multiple
2090CPUs with mismatched memory attributes. Since these fields are a part of the
2091lock implementation, they do not have access to any other locking primitive to
2092safeguard against the resulting coherency issues. As a result, simple software
2093cache maintenance is not enough to allocate them in coherent memory. Consider
2094the following example.
2095
2096CPU0 updates its per-CPU field with data cache enabled. This write updates a
2097local cache line which contains a copy of the fields for other CPUs as well. Now
2098CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache
2099disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of
2100its field in any other cache line in the system. This operation will invalidate
2101the update made by CPU0 as well.
2102
2103To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure
2104has been redesigned. The changes utilise the characteristic of Lamport's Bakery
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002105algorithm mentioned earlier. The bakery_lock structure only allocates the memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002106for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks
2107needed for a CPU into a section ``bakery_lock``. The linker allocates the memory
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002108for other cores by using the total size allocated for the bakery_lock section
2109and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002110perform software cache maintenance on the lock data structure without running
2111into coherency issues associated with mismatched attributes.
2112
2113The bakery lock data structure ``bakery_info_t`` is defined for use when
2114``USE_COHERENT_MEM`` is disabled as follows:
2115
2116.. code:: c
2117
2118 typedef struct bakery_info {
2119 /*
2120 * The lock_data is a bit-field of 2 members:
2121 * Bit[0] : choosing. This field is set when the CPU is
2122 * choosing its bakery number.
2123 * Bits[1 - 15] : number. This is the bakery number allocated.
2124 */
2125 volatile uint16_t lock_data;
2126 } bakery_info_t;
2127
2128The ``bakery_info_t`` represents a single per-CPU field of one lock and
2129the combination of corresponding ``bakery_info_t`` structures for all CPUs in the
2130system represents the complete bakery lock. The view in memory for a system
2131with n bakery locks are:
2132
2133::
2134
2135 bakery_lock section start
2136 |----------------|
2137 | `bakery_info_t`| <-- Lock_0 per-CPU field
2138 | Lock_0 | for CPU0
2139 |----------------|
2140 | `bakery_info_t`| <-- Lock_1 per-CPU field
2141 | Lock_1 | for CPU0
2142 |----------------|
2143 | .... |
2144 |----------------|
2145 | `bakery_info_t`| <-- Lock_N per-CPU field
2146 | Lock_N | for CPU0
2147 ------------------
2148 | XXXXX |
2149 | Padding to |
2150 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate
2151 | Granule | continuous memory for remaining CPUs.
2152 ------------------
2153 | `bakery_info_t`| <-- Lock_0 per-CPU field
2154 | Lock_0 | for CPU1
2155 |----------------|
2156 | `bakery_info_t`| <-- Lock_1 per-CPU field
2157 | Lock_1 | for CPU1
2158 |----------------|
2159 | .... |
2160 |----------------|
2161 | `bakery_info_t`| <-- Lock_N per-CPU field
2162 | Lock_N | for CPU1
2163 ------------------
2164 | XXXXX |
2165 | Padding to |
2166 | next Cache WB |
2167 | Granule |
2168 ------------------
2169
2170Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002171operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002172``bakery_lock`` section need to be fetched and appropriate cache operations need
2173to be performed for each access.
2174
Dan Handley610e7e12018-03-01 18:44:00 +00002175On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002176driver (``arm_lock``).
2177
2178Non Functional Impact of removing coherent memory
2179~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2180
2181Removal of the coherent memory region leads to the additional software overhead
2182of performing cache maintenance for the affected data structures. However, since
2183the memory where the data structures are allocated is cacheable, the overhead is
2184mostly mitigated by an increase in performance.
2185
2186There is however a performance impact for bakery locks, due to:
2187
2188- Additional cache maintenance operations, and
2189- Multiple cache line reads for each lock operation, since the bakery locks
2190 for each CPU are distributed across different cache lines.
2191
2192The implementation has been optimized to minimize this additional overhead.
2193Measurements indicate that when bakery locks are allocated in Normal memory, the
2194minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas
2195in Device memory the same is 2 micro seconds. The measurements were done on the
Dan Handley610e7e12018-03-01 18:44:00 +00002196Juno Arm development platform.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002197
2198As mentioned earlier, almost a page of memory can be saved by disabling
2199``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide
2200whether coherent memory should be used. If a platform disables
2201``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can
2202optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the
Paul Beesleyf8640672019-04-12 14:19:42 +01002203:ref:`Porting Guide`). Refer to the reference platform code for examples.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002204
2205Isolating code and read-only data on separate memory pages
2206----------------------------------------------------------
2207
Dan Handley610e7e12018-03-01 18:44:00 +00002208In the Armv8-A VMSA, translation table entries include fields that define the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002209properties of the target memory region, such as its access permissions. The
2210smallest unit of memory that can be addressed by a translation table entry is
2211a memory page. Therefore, if software needs to set different permissions on two
2212memory regions then it needs to map them using different memory pages.
2213
2214The default memory layout for each BL image is as follows:
2215
2216::
2217
2218 | ... |
2219 +-------------------+
2220 | Read-write data |
2221 +-------------------+ Page boundary
2222 | <Padding> |
2223 +-------------------+
2224 | Exception vectors |
2225 +-------------------+ 2 KB boundary
2226 | <Padding> |
2227 +-------------------+
2228 | Read-only data |
2229 +-------------------+
2230 | Code |
2231 +-------------------+ BLx_BASE
2232
Paul Beesleyba3ed402019-03-13 16:20:44 +00002233.. note::
2234 The 2KB alignment for the exception vectors is an architectural
2235 requirement.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002236
2237The read-write data start on a new memory page so that they can be mapped with
2238read-write permissions, whereas the code and read-only data below are configured
2239as read-only.
2240
2241However, the read-only data are not aligned on a page boundary. They are
2242contiguous to the code. Therefore, the end of the code section and the beginning
2243of the read-only data one might share a memory page. This forces both to be
2244mapped with the same memory attributes. As the code needs to be executable, this
2245means that the read-only data stored on the same memory page as the code are
2246executable as well. This could potentially be exploited as part of a security
2247attack.
2248
2249TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and
2250read-only data on separate memory pages. This in turn allows independent control
2251of the access permissions for the code and read-only data. In this case,
2252platform code gets a finer-grained view of the image layout and can
2253appropriately map the code region as executable and the read-only data as
2254execute-never.
2255
2256This has an impact on memory footprint, as padding bytes need to be introduced
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002257between the code and read-only data to ensure the segregation of the two. To
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002258limit the memory cost, this flag also changes the memory layout such that the
2259code and exception vectors are now contiguous, like so:
2260
2261::
2262
2263 | ... |
2264 +-------------------+
2265 | Read-write data |
2266 +-------------------+ Page boundary
2267 | <Padding> |
2268 +-------------------+
2269 | Read-only data |
2270 +-------------------+ Page boundary
2271 | <Padding> |
2272 +-------------------+
2273 | Exception vectors |
2274 +-------------------+ 2 KB boundary
2275 | <Padding> |
2276 +-------------------+
2277 | Code |
2278 +-------------------+ BLx_BASE
2279
2280With this more condensed memory layout, the separation of read-only data will
2281add zero or one page to the memory footprint of each BL image. Each platform
2282should consider the trade-off between memory footprint and security.
2283
Dan Handley610e7e12018-03-01 18:44:00 +00002284This build flag is disabled by default, minimising memory footprint. On Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002285platforms, it is enabled.
2286
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002287Publish and Subscribe Framework
2288-------------------------------
2289
2290The Publish and Subscribe Framework allows EL3 components to define and publish
2291events, to which other EL3 components can subscribe.
2292
2293The following macros are provided by the framework:
2294
2295- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument,
2296 the event name, which must be a valid C identifier. All calls to
2297 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file
2298 ``pubsub_events.h``.
2299
2300- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating
2301 subscribed handlers and calling them in turn. The handlers will be passed the
2302 parameter ``arg``. The expected use-case is to broadcast an event.
2303
2304- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value
2305 ``NULL`` is passed to subscribed handlers.
2306
2307- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to
2308 subscribe to ``event``. The handler will be executed whenever the ``event``
2309 is published.
2310
2311- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers
2312 subscribed for ``event``. ``subscriber`` must be a local variable of type
2313 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during
2314 iteration. This macro can be used for those patterns that none of the
2315 ``PUBLISH_EVENT_*()`` macros cover.
2316
2317Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will
2318result in build error. Subscribing to an undefined event however won't.
2319
2320Subscribed handlers must be of type ``pubsub_cb_t``, with following function
2321signature:
2322
Paul Beesley493e3492019-03-13 15:11:04 +00002323.. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002324
2325 typedef void* (*pubsub_cb_t)(const void *arg);
2326
2327There may be arbitrary number of handlers registered to the same event. The
2328order in which subscribed handlers are notified when that event is published is
2329not defined. Subscribed handlers may be executed in any order; handlers should
2330not assume any relative ordering amongst them.
2331
2332Publishing an event on a PE will result in subscribed handlers executing on that
2333PE only; it won't cause handlers to execute on a different PE.
2334
2335Note that publishing an event on a PE blocks until all the subscribed handlers
2336finish executing on the PE.
2337
Dan Handley610e7e12018-03-01 18:44:00 +00002338TF-A generic code publishes and subscribes to some events within. Platform
2339ports are discouraged from subscribing to them. These events may be withdrawn,
2340renamed, or have their semantics altered in the future. Platforms may however
2341register, publish, and subscribe to platform-specific events.
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01002342
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002343Publish and Subscribe Example
2344~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2345
2346A publisher that wants to publish event ``foo`` would:
2347
2348- Define the event ``foo`` in the ``pubsub_events.h``.
2349
Paul Beesley493e3492019-03-13 15:11:04 +00002350 .. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002351
2352 REGISTER_PUBSUB_EVENT(foo);
2353
2354- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to
2355 publish the event at the appropriate path and time of execution.
2356
2357A subscriber that wants to subscribe to event ``foo`` published above would
2358implement:
2359
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002360.. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002361
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002362 void *foo_handler(const void *arg)
2363 {
2364 void *result;
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002365
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002366 /* Do handling ... */
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002367
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002368 return result;
2369 }
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002370
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002371 SUBSCRIBE_TO_EVENT(foo, foo_handler);
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002372
Daniel Boulby468f0d72018-09-18 11:45:51 +01002373
2374Reclaiming the BL31 initialization code
2375~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2376
2377A significant amount of the code used for the initialization of BL31 is never
2378needed again after boot time. In order to reduce the runtime memory
2379footprint, the memory used for this code can be reclaimed after initialization
2380has finished and be used for runtime data.
2381
2382The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code
2383with a ``.text.init.*`` attribute which can be filtered and placed suitably
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002384within the BL image for later reclamation by the platform. The platform can
2385specify the filter and the memory region for this init section in BL31 via the
Daniel Boulby468f0d72018-09-18 11:45:51 +01002386plat.ld.S linker script. For example, on the FVP, this section is placed
2387overlapping the secondary CPU stacks so that after the cold boot is done, this
2388memory can be reclaimed for the stacks. The init memory section is initially
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002389mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has
Daniel Boulby468f0d72018-09-18 11:45:51 +01002390completed, the FVP changes the attributes of this section to ``RW``,
2391``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes
2392are changed within the ``bl31_plat_runtime_setup`` platform hook. The init
2393section section can be reclaimed for any data which is accessed after cold
2394boot initialization and it is upto the platform to make the decision.
2395
Paul Beesleyf8640672019-04-12 14:19:42 +01002396.. _firmware_design_pmf:
2397
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002398Performance Measurement Framework
2399---------------------------------
2400
2401The Performance Measurement Framework (PMF) facilitates collection of
Dan Handley610e7e12018-03-01 18:44:00 +00002402timestamps by registered services and provides interfaces to retrieve them
2403from within TF-A. A platform can choose to expose appropriate SMCs to
2404retrieve these collected timestamps.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002405
2406By default, the global physical counter is used for the timestamp
2407value and is read via ``CNTPCT_EL0``. The framework allows to retrieve
2408timestamps captured by other CPUs.
2409
2410Timestamp identifier format
2411~~~~~~~~~~~~~~~~~~~~~~~~~~~
2412
2413A PMF timestamp is uniquely identified across the system via the
2414timestamp ID or ``tid``. The ``tid`` is composed as follows:
2415
2416::
2417
2418 Bits 0-7: The local timestamp identifier.
2419 Bits 8-9: Reserved.
2420 Bits 10-15: The service identifier.
2421 Bits 16-31: Reserved.
2422
2423#. The service identifier. Each PMF service is identified by a
2424 service name and a service identifier. Both the service name and
2425 identifier are unique within the system as a whole.
2426
2427#. The local timestamp identifier. This identifier is unique within a given
2428 service.
2429
2430Registering a PMF service
2431~~~~~~~~~~~~~~~~~~~~~~~~~
2432
2433To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h``
2434is used. The arguments required are the service name, the service ID,
2435the total number of local timestamps to be captured and a set of flags.
2436
2437The ``flags`` field can be specified as a bitwise-OR of the following values:
2438
2439::
2440
2441 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval.
2442 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console.
2443
2444The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured
2445timestamps in a PMF specific linker section at build time.
2446Additionally, it defines necessary functions to capture and
2447retrieve a particular timestamp for the given service at runtime.
2448
Dan Handley610e7e12018-03-01 18:44:00 +00002449The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps
2450from within TF-A. In order to retrieve timestamps from outside of TF-A, the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002451``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro
2452accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()``
2453macro but additionally supports retrieving timestamps using SMCs.
2454
2455Capturing a timestamp
2456~~~~~~~~~~~~~~~~~~~~~
2457
2458PMF timestamps are stored in a per-service timestamp region. On a
2459system with multiple CPUs, each timestamp is captured and stored
2460in a per-CPU cache line aligned memory region.
2461
2462Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be
2463used to capture a timestamp at the location where it is used. The macro
2464takes the service name, a local timestamp identifier and a flag as arguments.
2465
2466The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which
2467instructs PMF to do cache maintenance following the capture. Cache
2468maintenance is required if any of the service's timestamps are captured
2469with data cache disabled.
2470
2471To capture a timestamp in assembly code, the caller should use
2472``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to
2473calculate the address of where the timestamp would be stored. The
2474caller should then read ``CNTPCT_EL0`` register to obtain the timestamp
2475and store it at the determined address for later retrieval.
2476
2477Retrieving a timestamp
2478~~~~~~~~~~~~~~~~~~~~~~
2479
Dan Handley610e7e12018-03-01 18:44:00 +00002480From within TF-A, timestamps for individual CPUs can be retrieved using either
2481``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros.
2482These macros accept the CPU's MPIDR value, or its ordinal position
2483respectively.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002484
Dan Handley610e7e12018-03-01 18:44:00 +00002485From outside TF-A, timestamps for individual CPUs can be retrieved by calling
2486into ``pmf_smc_handler()``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002487
Paul Beesley493e3492019-03-13 15:11:04 +00002488::
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002489
2490 Interface : pmf_smc_handler()
2491 Argument : unsigned int smc_fid, u_register_t x1,
2492 u_register_t x2, u_register_t x3,
2493 u_register_t x4, void *cookie,
2494 void *handle, u_register_t flags
2495 Return : uintptr_t
2496
2497 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32`
2498 when the caller of the SMC is running in AArch32 mode
2499 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode.
2500 x1: Timestamp identifier.
2501 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved.
2502 This can be the `mpidr` of a different core to the one initiating
2503 the SMC. In that case, service specific cache maintenance may be
2504 required to ensure the updated copy of the timestamp is returned.
2505 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If
2506 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a
2507 cache invalidate before reading the timestamp. This ensures
2508 an updated copy is returned.
2509
2510The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused
2511in this implementation.
2512
2513PMF code structure
2514~~~~~~~~~~~~~~~~~~
2515
2516#. ``pmf_main.c`` consists of core functions that implement service registration,
2517 initialization, storing, dumping and retrieving timestamps.
2518
2519#. ``pmf_smc.c`` contains the SMC handling for registered PMF services.
2520
2521#. ``pmf.h`` contains the public interface to Performance Measurement Framework.
2522
2523#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in
2524 assembly code.
2525
2526#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``.
2527
Dan Handley610e7e12018-03-01 18:44:00 +00002528Armv8-A Architecture Extensions
2529-------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002530
Dan Handley610e7e12018-03-01 18:44:00 +00002531TF-A makes use of Armv8-A Architecture Extensions where applicable. This
2532section lists the usage of Architecture Extensions, and build flags
2533controlling them.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002534
2535In general, and unless individually mentioned, the build options
Alexei Fedorovb567e5d2019-03-11 16:51:47 +00002536``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` select the Architecture Extension to
Dan Handley610e7e12018-03-01 18:44:00 +00002537target when building TF-A. Subsequent Arm Architecture Extensions are backward
2538compatible with previous versions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002539
2540The build system only requires that ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` have a
2541valid numeric value. These build options only control whether or not
Dan Handley610e7e12018-03-01 18:44:00 +00002542Architecture Extension-specific code is included in the build. Otherwise, TF-A
2543targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8
2544and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002545
Paul Beesleyf8640672019-04-12 14:19:42 +01002546See also the *Summary of build options* in :ref:`User Guide`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002547
2548For details on the Architecture Extension and available features, please refer
2549to the respective Architecture Extension Supplement.
2550
Dan Handley610e7e12018-03-01 18:44:00 +00002551Armv8.1-A
2552~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002553
2554This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when
2555``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1.
2556
Soby Mathewad042012019-09-25 14:03:41 +01002557- By default, a load-/store-exclusive instruction pair is used to implement
2558 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the
2559 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction.
2560 Notice this instruction is only available in AArch64 execution state, so
2561 the option is only available to AArch64 builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002562
Dan Handley610e7e12018-03-01 18:44:00 +00002563Armv8.2-A
2564~~~~~~~~~
Isla Mitchellc4a1a072017-08-07 11:20:13 +01002565
Antonio Nino Diaz633703a2019-02-19 13:14:06 +00002566- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the
2567 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple
Sandrine Bailleuxfee6e262018-01-29 14:48:15 +01002568 Processing Elements in the same Inner Shareable domain use the same
2569 translation table entries for a given stage of translation for a particular
2570 translation regime.
Isla Mitchellc4a1a072017-08-07 11:20:13 +01002571
Jeenu Viswambharancbad6612018-08-15 14:29:29 +01002572Armv8.3-A
2573~~~~~~~~~
2574
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00002575- Pointer authentication features of Armv8.3-A are unconditionally enabled in
2576 the Non-secure world so that lower ELs are allowed to use them without
2577 causing a trap to EL3.
2578
2579 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS``
2580 must be set to 1. This will add all pointer authentication system registers
2581 to the context that is saved when doing a world switch.
Jeenu Viswambharancbad6612018-08-15 14:29:29 +01002582
Alexei Fedorov2831d582019-03-13 11:05:07 +00002583 The TF-A itself has support for pointer authentication at runtime
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002584 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002585 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1,
2586 BL2, BL31, and the TSP if it is used.
2587
Alexei Fedorov2831d582019-03-13 11:05:07 +00002588 These options are experimental features.
2589
2590 Note that Pointer Authentication is enabled for Non-secure world irrespective
2591 of the value of these build flags if the CPU supports it.
2592
Alexei Fedorovb567e5d2019-03-11 16:51:47 +00002593 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of
2594 enabling PAuth is lower because the compiler will use the optimized
2595 PAuth instructions rather than the backwards-compatible ones.
2596
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002597Armv8.5-A
2598~~~~~~~~~
2599
2600- Branch Target Identification feature is selected by ``BRANCH_PROTECTION``
Justin Chadwell55c73512019-07-18 16:16:32 +01002601 option set to 1. This option defaults to 0 and this is an experimental
2602 feature.
2603
2604- Memory Tagging Extension feature is unconditionally enabled for both worlds
2605 (at EL0 and S-EL0) if it is only supported at EL0. If instead it is
2606 implemented at all ELs, it is unconditionally enabled for only the normal
2607 world. To enable it for the secure world as well, the build option
2608 ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement
2609 MTE support at all, it is always disabled, no matter what build options
2610 are used.
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002611
Dan Handley610e7e12018-03-01 18:44:00 +00002612Armv7-A
2613~~~~~~~
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002614
2615This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7.
2616
Dan Handley610e7e12018-03-01 18:44:00 +00002617There are several Armv7-A extensions available. Obviously the TrustZone
2618extension is mandatory to support the TF-A bootloader and runtime services.
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002619
Dan Handley610e7e12018-03-01 18:44:00 +00002620Platform implementing an Armv7-A system can to define from its target
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002621Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002622``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002623Cortex-A15 target.
2624
2625Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support.
Paul Beesleyf2ec7142019-10-04 16:17:46 +00002626Note that using neon at runtime has constraints on non secure world context.
Dan Handley610e7e12018-03-01 18:44:00 +00002627TF-A does not yet provide VFP context management.
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002628
2629Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set
2630the toolchain target architecture directive.
2631
2632Platform may choose to not define straight the toolchain target architecture
2633directive by defining ``MARCH32_DIRECTIVE``.
2634I.e:
2635
Paul Beesley493e3492019-03-13 15:11:04 +00002636.. code:: make
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002637
2638 MARCH32_DIRECTIVE := -mach=armv7-a
2639
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002640Code Structure
2641--------------
2642
Dan Handley610e7e12018-03-01 18:44:00 +00002643TF-A code is logically divided between the three boot loader stages mentioned
2644in the previous sections. The code is also divided into the following
2645categories (present as directories in the source code):
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002646
2647- **Platform specific.** Choice of architecture specific code depends upon
2648 the platform.
2649- **Common code.** This is platform and architecture agnostic code.
2650- **Library code.** This code comprises of functionality commonly used by all
2651 other code. The PSCI implementation and other EL3 runtime frameworks reside
2652 as Library components.
2653- **Stage specific.** Code specific to a boot stage.
2654- **Drivers.**
2655- **Services.** EL3 runtime services (eg: SPD). Specific SPD services
2656 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``).
2657
2658Each boot loader stage uses code from one or more of the above mentioned
2659categories. Based upon the above, the code layout looks like this:
2660
2661::
2662
2663 Directory Used by BL1? Used by BL2? Used by BL31?
2664 bl1 Yes No No
2665 bl2 No Yes No
2666 bl31 No No Yes
2667 plat Yes Yes Yes
2668 drivers Yes No Yes
2669 common Yes Yes Yes
2670 lib Yes Yes Yes
2671 services No No Yes
2672
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002673The build system provides a non configurable build option IMAGE_BLx for each
2674boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be
Dan Handley610e7e12018-03-01 18:44:00 +00002675defined by the build system. This enables TF-A to compile certain code only
2676for specific boot loader stages
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002677
2678All assembler files have the ``.S`` extension. The linker source files for each
2679boot stage have the extension ``.ld.S``. These are processed by GCC to create the
2680linker scripts which have the extension ``.ld``.
2681
2682FDTs provide a description of the hardware platform and are used by the Linux
2683kernel at boot time. These can be found in the ``fdts`` directory.
2684
Paul Beesleyf8640672019-04-12 14:19:42 +01002685.. rubric:: References
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002686
Paul Beesleyf8640672019-04-12 14:19:42 +01002687- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_
2688
2689- `Power State Coordination Interface PDD`_
2690
2691- `SMC Calling Convention PDD`_
2692
2693- :ref:`Interrupt Management Framework`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002694
2695--------------
2696
Antonio Nino Diaz633703a2019-02-19 13:14:06 +00002697*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002698
Paul Beesleyf8640672019-04-12 14:19:42 +01002699.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002700.. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
2701.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2702.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
Dan Handley610e7e12018-03-01 18:44:00 +00002703.. _Arm ARM: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002704.. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
Sandrine Bailleux30918422019-04-24 10:41:24 +02002705.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002706
Paul Beesley814f8c02019-03-13 15:49:27 +00002707.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png